diff options
| author | elagil <[email protected]> | 2025-08-25 21:10:59 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2025-09-05 14:43:29 +0200 |
| commit | 50224583db79fcbfe340056eef855414c884f281 (patch) | |
| tree | 96460c0d5697792e5fe9fbccb89818e10a4f3e76 | |
| parent | bfd82ff82c1a1cc5159fc07997af2ca87622a679 (diff) | |
fix: load/store ordering
| -rw-r--r-- | embassy-stm32/src/dma/gpdma/mod.rs | 6 | ||||
| -rw-r--r-- | embassy-stm32/src/dma/gpdma/ringbuffered.rs | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/embassy-stm32/src/dma/gpdma/mod.rs b/embassy-stm32/src/dma/gpdma/mod.rs index e906c7559..a158d30b8 100644 --- a/embassy-stm32/src/dma/gpdma/mod.rs +++ b/embassy-stm32/src/dma/gpdma/mod.rs | |||
| @@ -178,15 +178,15 @@ impl AnyChannel { | |||
| 178 | if sr.tcf() { | 178 | if sr.tcf() { |
| 179 | ch.fcr().write(|w| w.set_tcf(true)); | 179 | ch.fcr().write(|w| w.set_tcf(true)); |
| 180 | 180 | ||
| 181 | let lli_count = state.lli_state.count.load(Ordering::Relaxed); | 181 | let lli_count = state.lli_state.count.load(Ordering::Acquire); |
| 182 | let complete = if lli_count > 0 { | 182 | let complete = if lli_count > 0 { |
| 183 | let next_lli_index = state.lli_state.index.load(Ordering::Relaxed) + 1; | 183 | let next_lli_index = state.lli_state.index.load(Ordering::Acquire) + 1; |
| 184 | let complete = next_lli_index >= lli_count; | 184 | let complete = next_lli_index >= lli_count; |
| 185 | 185 | ||
| 186 | state | 186 | state |
| 187 | .lli_state | 187 | .lli_state |
| 188 | .index | 188 | .index |
| 189 | .store(if complete { 0 } else { next_lli_index }, Ordering::Relaxed); | 189 | .store(if complete { 0 } else { next_lli_index }, Ordering::Release); |
| 190 | 190 | ||
| 191 | complete | 191 | complete |
| 192 | } else { | 192 | } else { |
diff --git a/embassy-stm32/src/dma/gpdma/ringbuffered.rs b/embassy-stm32/src/dma/gpdma/ringbuffered.rs index c49c6c73d..20f46b103 100644 --- a/embassy-stm32/src/dma/gpdma/ringbuffered.rs +++ b/embassy-stm32/src/dma/gpdma/ringbuffered.rs | |||
| @@ -20,11 +20,11 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> { | |||
| 20 | let state = &STATE[self.0.id as usize]; | 20 | let state = &STATE[self.0.id as usize]; |
| 21 | let current_remaining = self.0.get_remaining_transfers() as usize; | 21 | let current_remaining = self.0.get_remaining_transfers() as usize; |
| 22 | 22 | ||
| 23 | let lli_count = state.lli_state.count.load(Ordering::Relaxed); | 23 | let lli_count = state.lli_state.count.load(Ordering::Acquire); |
| 24 | 24 | ||
| 25 | if lli_count > 0 { | 25 | if lli_count > 0 { |
| 26 | let lli_index = state.lli_state.index.load(Ordering::Relaxed); | 26 | let lli_index = state.lli_state.index.load(Ordering::Acquire); |
| 27 | let single_transfer_count = state.lli_state.transfer_count.load(Ordering::Relaxed) / lli_count; | 27 | let single_transfer_count = state.lli_state.transfer_count.load(Ordering::Acquire) / lli_count; |
| 28 | 28 | ||
| 29 | (lli_count - lli_index - 1) * single_transfer_count + current_remaining | 29 | (lli_count - lli_index - 1) * single_transfer_count + current_remaining |
| 30 | } else { | 30 | } else { |
