usb: centralize all control logging in control.rs

3 files changed, 17 insertions, 13 deletions

diff --git a/embassy-nrf/src/usb.rs b/embassy-nrf/src/usb.rs
index 4614389f0..124316a29 100644
--- a/embassy-nrf/src/usb.rs
+++ b/embassy-nrf/src/usb.rs
@@ -615,14 +615,12 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
     }
 
     fn accept(&mut self) {
-        debug!("control accept");
         let regs = T::regs();
         regs.tasks_ep0status
             .write(|w| w.tasks_ep0status().bit(true));
     }
 
     fn reject(&mut self) {
-        debug!("control reject");
         let regs = T::regs();
         regs.tasks_ep0stall.write(|w| w.tasks_ep0stall().bit(true));
     }
diff --git a/embassy-usb/src/control.rs b/embassy-usb/src/control.rs
index 9f1115ff2..da48dccaf 100644
--- a/embassy-usb/src/control.rs
+++ b/embassy-usb/src/control.rs
@@ -231,6 +231,8 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
 
     pub(crate) async fn setup(&mut self) -> Setup {
         let req = self.control.setup().await;
+        trace!("control request: {:02x}", req);
+
         match (req.direction, req.length) {
             (UsbDirection::Out, n) => Setup::DataOut(
                 req,
@@ -267,15 +269,21 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
                 }
             }
 
-            Ok((&buf[0..total], StatusStage {}))
+            let res = &buf[0..total];
+            #[cfg(feature = "defmt")]
+            trace!("  control out data: {:02x}", buf);
+            #[cfg(not(feature = "defmt"))]
+            trace!("  control out data: {:02x?}", buf);
+
+            Ok((res, StatusStage {}))
         }
     }
 
     pub(crate) async fn accept_in(&mut self, buf: &[u8], stage: DataInStage) {
         #[cfg(feature = "defmt")]
-        debug!("control in accept {:x}", buf);
+        trace!("  control in accept {:02x}", buf);
         #[cfg(not(feature = "defmt"))]
-        debug!("control in accept {:x?}", buf);
+        trace!("  control in accept {:02x?}", buf);
 
         let req_len = stage.length;
         let len = buf.len().min(req_len);
@@ -305,10 +313,12 @@ impl<C: driver::ControlPipe> ControlPipe<C> {
     }
 
     pub(crate) fn accept(&mut self, _: StatusStage) {
+        trace!("  control accept");
         self.control.accept();
     }
 
     pub(crate) fn reject(&mut self) {
+        trace!("  control reject");
         self.control.reject();
     }
 }
diff --git a/embassy-usb/src/lib.rs b/embassy-usb/src/lib.rs
index 067b5b07f..1b189383e 100644
--- a/embassy-usb/src/lib.rs
+++ b/embassy-usb/src/lib.rs
@@ -128,14 +128,10 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
                         self.device_state = UsbDeviceState::Suspend;
                     }
                 },
-                Either::Right(req) => {
-                    debug!("control request: {:x}", req);
-
-                    match req {
-                        Setup::DataIn(req, stage) => self.handle_control_in(req, stage).await,
-                        Setup::DataOut(req, stage) => self.handle_control_out(req, stage).await,
-                    }
-                }
+                Either::Right(req) => match req {
+                    Setup::DataIn(req, stage) => self.handle_control_in(req, stage).await,
+                    Setup::DataOut(req, stage) => self.handle_control_out(req, stage).await,
+                },
             }
         }
     }