diff options
| author | Jaxter Kim <[email protected]> | 2022-11-14 14:56:30 +0100 |
|---|---|---|
| committer | Jaxter Kim <[email protected]> | 2022-11-15 12:56:47 +0100 |
| commit | 551b54ddcbb104f881a3333215f4a828b33d029a (patch) | |
| tree | 572a7787a1a9c1449fbb311f82ab8ce6697fa123 | |
| parent | 2528f451387e6c7b27c3140cd87d47521d1971a2 (diff) | |
stm32g0: Fix ADC for channels above 14
| -rw-r--r-- | embassy-stm32/src/adc/v3.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index 8f81cb7a3..90aa7d3b9 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs | |||
| @@ -71,7 +71,7 @@ impl<'d, T: Instance> Adc<'d, T> { | |||
| 71 | 71 | ||
| 72 | #[cfg(adc_g0)] | 72 | #[cfg(adc_g0)] |
| 73 | T::regs().cfgr1().modify(|reg| { | 73 | T::regs().cfgr1().modify(|reg| { |
| 74 | reg.set_chselrmod(true); | 74 | reg.set_chselrmod(false); |
| 75 | }); | 75 | }); |
| 76 | } | 76 | } |
| 77 | 77 | ||
| @@ -200,7 +200,7 @@ impl<'d, T: Instance> Adc<'d, T> { | |||
| 200 | #[cfg(not(stm32g0))] | 200 | #[cfg(not(stm32g0))] |
| 201 | T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel())); | 201 | T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel())); |
| 202 | #[cfg(stm32g0)] | 202 | #[cfg(stm32g0)] |
| 203 | T::regs().chselr().write(|reg| reg.set_chsel(pin.channel() as u32)); | 203 | T::regs().chselr().write(|reg| reg.set_chsel(1 << pin.channel())); |
| 204 | 204 | ||
| 205 | // Some models are affected by an erratum: | 205 | // Some models are affected by an erratum: |
| 206 | // If we perform conversions slower than 1 kHz, the first read ADC value can be | 206 | // If we perform conversions slower than 1 kHz, the first read ADC value can be |