Merge pull request #1 from bogdan-petru/import/mcxa276-initial

feat(mcxa276): initial HAL import

61 files changed, 8157 insertions, 244 deletions

diff --git a/.cargo/config.toml b/.cargo/config.toml
new file mode 100644
index 000000000..3286be01c
--- /dev/null
+++ b/.cargo/config.toml
@@ -0,0 +1,19 @@
+[build]
+target = "thumbv8m.main-none-eabihf"
+
+[target.thumbv8m.main-none-eabihf]
+runner = "./run.sh"
+# Use our custom ram.ld for RAM-execution
+rustflags = ["-C", "link-arg=-Tdefmt.x", "-C", "link-arg=-Tram.ld"]
+
+[alias]
+# Build examples with defmt+RTT and LPUART2 enabled
+build-defmt = ["build", "--features", "defmt defmt-rtt lpuart2", "--examples"]
+# Blocking run (uses run.sh). Good for one-terminal flash+run.
+run-defmt = ["run", "--features", "defmt defmt-rtt lpuart2", "--example", "hello"]
+# Non-blocking flash to RAM via J-Link; frees probe for RTT attach
+flash-nb = ["!./tools/run_jlink_noblock.sh", "target/thumbv8m.main-none-eabihf/debug/examples/hello", "1366:0101:000600110607", "MCXA276", "500"]
+# Attach-only viewer that decodes defmt over RTT using J-Link
+# Requires PROBE_RS_PROBE exported (or it will prompt)
+defmt-attach = ["embed", "--features", "defmt defmt-rtt lpuart2", "--example", "hello"]
+
diff --git a/.github/DOCS.md b/.github/DOCS.md
new file mode 100644
index 000000000..e932784c7
--- /dev/null
+++ b/.github/DOCS.md
@@ -0,0 +1,23 @@
+# Github config and workflows
+
+In this folder there is configuration for codecoverage, dependabot, and ci
+workflows that check the library more deeply than the default configurations.
+
+This folder can be or was merged using a --allow-unrelated-histories merge
+strategy from <https://github.com/jonhoo/rust-ci-conf/> which provides a
+reasonably sensible base for writing your own ci on. By using this strategy
+the history of the CI repo is included in your repo, and future updates to
+the CI can be merged later.
+
+To perform this merge run:
+
+```shell
+git remote add ci https://github.com/jonhoo/rust-ci-conf.git
+git fetch ci
+git merge --allow-unrelated-histories ci/main
+```
+
+An overview of the files in this project is available at:
+<https://www.youtube.com/watch?v=xUH-4y92jPg&t=491s>, which contains some
+rationale for decisions and runs through an example of solving minimal version
+and OpenSSL issues.
diff --git a/.github/codecov.yml b/.github/codecov.yml
new file mode 100644
index 000000000..cd5ce8fc1
--- /dev/null
+++ b/.github/codecov.yml
@@ -0,0 +1,21 @@
+# ref: https://docs.codecov.com/docs/codecovyml-reference
+coverage:
+  # Hold ourselves to a high bar
+  range: 85..100
+  round: down
+  precision: 1
+  status:
+    # ref: https://docs.codecov.com/docs/commit-status
+    project:
+      default:
+        # Avoid false negatives
+        threshold: 1%
+
+# Test files aren't important for coverage
+ignore:
+  - "tests"
+
+# Make comments less noisy
+comment:
+  layout: "files"
+  require_changes: true
diff --git a/.github/dependabot.yml b/.github/dependabot.yml
new file mode 100644
index 000000000..d0f091e7b
--- /dev/null
+++ b/.github/dependabot.yml
@@ -0,0 +1,19 @@
+version: 2
+updates:
+  - package-ecosystem: github-actions
+    directory: /
+    schedule:
+      interval: daily
+  - package-ecosystem: cargo
+    directory: /
+    schedule:
+      interval: daily
+    ignore:
+      - dependency-name: "*"
+        # patch and minor updates don't matter for libraries as consumers of this library build
+        # with their own lockfile, rather than the version specified in this library's lockfile
+        # remove this ignore rule if your package has binaries to ensure that the binaries are
+        # built with the exact set of dependencies and those are up to date.
+        update-types:
+          - "version-update:semver-patch"
+          - "version-update:semver-minor"
diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml
index 9bf402d61..1a09a1492 100644
--- a/.github/workflows/check.yml
+++ b/.github/workflows/check.yml
@@ -1,6 +1,5 @@
 # This workflow runs whenever a PR is opened or updated, or a commit is pushed to main. It runs
 # several checks:
-# - commit_list: produces a list of commits to be checked
 # - fmt: checks that the code is formatted according to rustfmt
 # - clippy: checks that the code does not contain any clippy warnings
 # - doc: checks that the code can be documented without errors
@@ -8,66 +7,84 @@
 # - msrv: check that the msrv specified in the crate is correct
 permissions:
   contents: read
+
 # This configuration allows maintainers of this repo to create a branch and pull request based on
 # the new branch. Restricting the push trigger to the main branch ensures that the PR only gets
 # built once.
 on:
+
   push:
-    branches: [main]
+    branches: [main, main-nextgen]
   pull_request:
+
 # If new code is pushed to a PR branch, then cancel in progress workflows for that PR. Ensures that
 # we don't waste CI time, and returns results quicker https://github.com/jonhoo/rust-ci-conf/pull/5
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
   cancel-in-progress: true
+
 name: check
+
 jobs:
+
   fmt:
     runs-on: ubuntu-latest
-    name: stable / fmt
+    name: nightly / fmt
+
+    strategy:
+      fail-fast: false
+      matrix:
+        workdir: [ ".", "examples/rt633", "examples/rt685s-evk",]
+
     steps:
       - uses: actions/checkout@v4
         with:
           submodules: true
-      - name: Install stable
-        uses: dtolnay/rust-toolchain@stable
+
+      - name: Install nightly
+        uses: dtolnay/rust-toolchain@nightly
         with:
           components: rustfmt
+
       - name: cargo fmt --check
         run: cargo fmt --check
+        working-directory: ${{ matrix.workdir }}
 
-  clippy:
+  clippy-examples:
     runs-on: ubuntu-latest
     name: ${{ matrix.toolchain }} / clippy
+
     permissions:
       contents: read
       checks: write
+
     strategy:
       fail-fast: false
       matrix:
         # Get early warning of new lints which are regularly introduced in beta channels.
-        toolchain: [stable, beta]
+        toolchain: [stable]
+        workdir: ["examples"]
+
     steps:
       - uses: actions/checkout@v4
         with:
           submodules: true
+
       - name: Install ${{ matrix.toolchain }}
         uses: dtolnay/rust-toolchain@master
         with:
           toolchain: ${{ matrix.toolchain }}
           components: clippy
+
       - name: cargo clippy
-        uses: giraffate/clippy-action@v1
-        with:
-          reporter: 'github-pr-check'
-          github_token: ${{ secrets.GITHUB_TOKEN }}
+        working-directory: ${{ matrix.workdir }}
+        run: |
+          cargo clippy --locked -- -Dwarnings -D clippy::suspicious -D clippy::correctness -D clippy::perf -D clippy::style
 
   # Enable once we have a released crate
   # semver:
   #   runs-on: ubuntu-latest
   #   name: semver
-  #   strategy:
-  #     fail-fast: false
   #   steps:
   #     - uses: actions/checkout@v4
   #       with:
@@ -85,14 +102,18 @@ jobs:
     # API be documented as only available in some specific platforms.
     runs-on: ubuntu-latest
     name: nightly / doc
+
     steps:
       - uses: actions/checkout@v4
         with:
           submodules: true
+
       - name: Install nightly
         uses: dtolnay/rust-toolchain@nightly
+
       - name: cargo doc
-        run: cargo doc --no-deps --all-features
+        run: |
+          cargo doc --no-deps --all-features --locked
         env:
           RUSTDOCFLAGS: --cfg docsrs
 
@@ -101,16 +122,24 @@ jobs:
     # which is required for feature unification
     runs-on: ubuntu-latest
     name: ubuntu / stable / features
+
+    strategy:
+      fail-fast: false
+
     steps:
       - uses: actions/checkout@v4
         with:
           submodules: true
+
       - name: Install stable
         uses: dtolnay/rust-toolchain@stable
-      - name: cargo install cargo-hack
-        uses: taiki-e/install-action@cargo-hack
-      # intentionally no target specifier; see https://github.com/jonhoo/rust-ci-conf/pull/4
-      # --feature-powerset runs for every combination of features
+        with:
+          toolchain: stable
+          components: clippy
+
+      - name: rustup target add thumbv8m.main-none-eabihf
+        run: rustup target add thumbv8m.main-none-eabihf
+
       - name: cargo hack
         run: cargo hack --feature-powerset check
 
@@ -119,33 +148,22 @@ jobs:
     # our dependencies.
     runs-on: ubuntu-latest
     name: ubuntu / stable / deny
+
     steps:
       - uses: actions/checkout@v4
         with:
           submodules: true
+
       - name: Install stable
         uses: dtolnay/rust-toolchain@stable
+
       - name: cargo install cargo-deny
         uses: EmbarkStudios/cargo-deny-action@v2
         with:
           log-level: warn
           manifest-path: ./Cargo.toml
           command: check
-          arguments: --all-features
-
-  test:
-    runs-on: ubuntu-latest
-    name: ubuntu / stable / test
-    steps:
-      - uses: actions/checkout@v4
-        with:
-          submodules: true
-      - name: Install stable
-        uses: dtolnay/rust-toolchain@stable
-      - name: cargo install cargo-hack
-        uses: taiki-e/install-action@cargo-hack
-      - name: cargo test
-        run: cargo hack --feature-powerset test
+          arguments: --all-features --locked
 
   msrv:
     # check that we can build using the minimal rust version that is specified by this crate
@@ -155,15 +173,33 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        msrv: ["1.85"]
+        msrv: ["1.90"] # We're relying on namespaced-features, which
+                       # was released in 1.60
+                       #
+                       # We also depend on `fixed' which requires rust
+                       # 1.71
+                       #
+                       # Additionally, we depend on embedded-hal-async
+                       # which requires 1.75
+                       #
+                       # embassy-time requires 1.79 due to
+                       # collapse_debuginfo
+                       #
+                       # embassy upstream switched to rust 1.85
+                       #
+                       # unsigned_is_multiple_of requires 1.90, else we get clippy warnings
+
     name: ubuntu / ${{ matrix.msrv }}
     steps:
       - uses: actions/checkout@v4
         with:
           submodules: true
+
       - name: Install ${{ matrix.msrv }}
         uses: dtolnay/rust-toolchain@master
         with:
           toolchain: ${{ matrix.msrv }}
+
       - name: cargo +${{ matrix.msrv }} check
-        run: cargo check
+        run: |
+          cargo check --all-features --locked
diff --git a/.github/workflows/nostd.yml b/.github/workflows/nostd.yml
index 532235851..92460bd0f 100644
--- a/.github/workflows/nostd.yml
+++ b/.github/workflows/nostd.yml
@@ -3,28 +3,41 @@
 # information about how the concurrency cancellation and workflow triggering works
 permissions:
   contents: read
+
 on:
   push:
-    branches: [main]
+    branches: [main, main-nextgen]
   pull_request:
+
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
   cancel-in-progress: true
+
 name: no-std
+
 jobs:
   nostd:
     runs-on: ubuntu-latest
     name: ${{ matrix.target }}
+
     strategy:
       matrix:
         target: [thumbv8m.main-none-eabihf]
+
     steps:
       - uses: actions/checkout@v4
         with:
           submodules: true
+
       - name: Install stable
         uses: dtolnay/rust-toolchain@stable
+
       - name: rustup target add ${{ matrix.target }}
         run: rustup target add ${{ matrix.target }}
+
+      - name: Show variable
+        run: echo ${{ env.TOKEN }}
+
       - name: cargo check
-        run: cargo check --target ${{ matrix.target }}
+        run: |
+          cargo check --target ${{ matrix.target }} --all-features --locked
diff --git a/.github/workflows/rolling.yml b/.github/workflows/rolling.yml
new file mode 100644
index 000000000..f572954f9
--- /dev/null
+++ b/.github/workflows/rolling.yml
@@ -0,0 +1,68 @@
+# This workflow runs every morning at midnight. It will run cargo hack
+# and a build with msrv. If any dependency breaks our crate, we will
+# know ASAP.
+#
+# - check: build with all features
+# - msrv: check that the msrv specified in the crate is correct
+permissions:
+  contents: read
+
+on:
+  schedule:
+    - cron: '0 0 * * *'
+
+name: rolling
+jobs:
+
+  check:
+    runs-on: ubuntu-latest
+    name: ubuntu / stable / features
+    strategy:
+      fail-fast: false
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          submodules: true
+      - name: Install stable
+        uses: dtolnay/rust-toolchain@stable
+      - name: cargo install cargo-hack
+        uses: taiki-e/install-action@cargo-hack
+      - name: cargo check
+        run: |
+          cargo update
+          cargo check --all-features check
+
+  msrv:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        msrv: ["1.85"] # We're relying on namespaced-features, which
+                       # was released in 1.60
+                       #
+                       # We also depend on `fixed' which requires rust
+                       # 1.71
+                       #
+                       # Additionally, we depend on embedded-hal-async
+                       # which requires 1.75
+                       #
+                       # embassy-time requires 1.79 due to
+                       # collapse_debuginfo
+                       #
+                       # embassy upstream switched to rust 1.83
+                       #
+                       # embedded-services (storage bus) dependency
+                       # requires 1.85
+    name: ubuntu / ${{ matrix.msrv }} (${{ matrix.commit }})
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          submodules: true
+      - name: Install ${{ matrix.msrv }}
+        uses: dtolnay/rust-toolchain@master
+        with:
+          toolchain: ${{ matrix.msrv }}
+      - name: cargo +${{ matrix.msrv }} check
+        run: |
+          cargo update
+          cargo check --all-features check
diff --git a/.gitignore b/.gitignore
index 6985cf1bd..a23881a76 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,14 +1,20 @@
-# Generated by Cargo
-# will have compiled files and executables
-debug/
-target/
-
-# Remove Cargo.lock from gitignore if creating an executable, leave it for libraries
-# More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html
+# Rust
+/target/
 Cargo.lock
 
-# These are backup files generated by rustfmt
-**/*.rs.bk
+# IDE
+.vscode/
+.idea/
+
+# OS
+.DS_Store
+Thumbs.db
+
+# Embedded
+*.bin
+*.hex
+*.elf
+*.map
 
-# MSVC Windows builds of rustc generate these, which store debugging information
-*.pdb
+# Debug
+*.log
diff --git a/.vscode/settings.json b/.vscode/settings.json
deleted file mode 100644
index ace00d468..000000000
--- a/.vscode/settings.json
+++ /dev/null
@@ -1,14 +0,0 @@
-{
-    "editor.formatOnSave": true,
-    "rust-analyzer.checkOnSave": true,
-    "rust-analyzer.check.allTargets": false,
-    "rust-analyzer.cargo.target": "thumbv8m.main-none-eabihf",
-    "rust-analyzer.cargo.features": "all",
-    "rust-analyzer.check.command": "clippy",
-    "[toml]": {
-        "editor.defaultFormatter": "tamasfe.even-better-toml"
-    },
-    "[rust]": {
-        "editor.defaultFormatter": "rust-lang.rust-analyzer"
-    }
-}
diff --git a/CODEOWNERS b/CODEOWNERS
deleted file mode 100644
index e2a52ae39..000000000
--- a/CODEOWNERS
+++ /dev/null
@@ -1 +0,0 @@
-* @felipebalbi @jerrysxie @tullom @RobertZ2011 @dymk
diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md
index 8603671fb..54a673e04 100644
--- a/CODE_OF_CONDUCT.md
+++ b/CODE_OF_CONDUCT.md
@@ -129,4 +129,4 @@ For answers to common questions about this code of conduct, see the FAQ at
 [v2.1]: https://www.contributor-covenant.org/version/2/1/code_of_conduct.html
 [Mozilla CoC]: https://github.com/mozilla/diversity
 [FAQ]: https://www.contributor-covenant.org/faq
-[translations]: https://www.contributor-covenant.org/translations
\ No newline at end of file
+[translations]: https://www.contributor-covenant.org/translations
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
index c45bc8e43..7c8289a58 100644
--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -14,22 +14,35 @@ you have the right to submit those contributions under those terms.
 If you wish to contribute code or documentation authored by others, or using the terms of any other license, please indicate that clearly in your
 pull request so that the project team can discuss the situation with you.
 
-## Commit Message
+# Contribution Guideline
 
+* For any new HAL driver added, please add corresponding test in the examples
+* Format the code with `cargo fmt`. Or better yet, enable format on save in your IDE for rust source files.
 * Use meaningful commit messages. See [this blogpost](http://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html)
 
-## PR Etiquette
+# PR Etiquette
 
 * Create a draft PR first
 * Make sure that your branch has `.github` folder and all the code linting/sanity check workflows are passing in your draft PR before sending it out to code reviewers.
 
-## Clean Commit History
+# Careful Use of `Unsafe`
 
-We disabled squashing of commit and would like to maintain a clean commit history. So please reorganize your commits with the following items:
+Working with embedded, using of `unsafe` is a necessity. However, please wrap unsafe code with safe interfaces to prevent `unsafe` keyword being sprinkled everywhere.
+
+# RFC Draft PR
+
+If you want feedback on your design or HAL driver early, please create a draft PR with title prefix `RFC:`.
+
+# Branch Naming Scheme
 
-* Each commit builds successfully without warning
-* Miscellaneous commits to fix typos + formatting are squashed
+For now, we're not using forks. Eventually a personal fork will be required for any PRs to limit the amount of people with merge access to the main branch. Until that happens, please use meaningful branch names like this `user_alias/feature` and avoid sending PRs from branches containing prefixes such as "wip", "test", etc. Prior to sending a PR, please rename the branch.
+
+# Clean Commit History
+
+We disabled squashing of commit and would like to maintain a clean commit history. So please reorganize your commits with the following items:
+  * Each commit builds successfully without warning from `rustc` or `clippy`
+  * Miscellaneous commits to fix typos + formatting are squashed
 
-## Regressions
+# Regressions
 
 When reporting a regression, please ensure that you use `git bisect` to find the first offending commit, as that will help us finding the culprit a lot faster.
diff --git a/Cargo.toml b/Cargo.toml
index 71c4806fe..8ec547494 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,19 +1,110 @@
 [package]
-name = "embedded-rust-template"
+name = "embassy-mcxa276"
 version = "0.1.0"
 edition = "2021"
-license = "MIT"
-repository = "https://github.com/OpenDevicePartnership/embedded-rust-template"
-rust-version = "1.85"
+license = "MIT OR Apache-2.0"
+description = "Embassy Hardware Abstraction Layer (HAL) for NXP MCXA276"
+keywords = ["embedded", "hal", "nxp", "mcxa276", "embassy"]
+categories = ["embedded", "hardware-support", "no-std"]
+
+[lib]
+name = "embassy_mcxa276"
 
 [dependencies]
-# dependencies for all targets
+cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
+cortex-m-rt = { version = "0.7", features = ["device"] }
+critical-section = "1.2.0"
+defmt = { version = "1.0", optional = true }
+embassy-embedded-hal = "0.5.0"
+embassy-executor = { version = "0.9.0", features = ["arch-cortex-m", "executor-interrupt", "executor-thread"], default-features = false }
+embassy-hal-internal = { version = "0.3.0", features = ["cortex-m", "prio-bits-3"] }
+embassy-sync = "0.7.2"
+embassy-time = "0.5.0"
+embassy-time-driver = "0.2.1"
+embedded-io = "0.6"
+heapless = "0.8"
+mcxa-pac = { git = "https://github.com/OpenDevicePartnership/mcxa-pac", features = ["rt"], rev = "f0281344c605ab24c38979553b41a1655c50625c", version = "0.1.0" }
+paste = "1.0.15"
+
+embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = [
+    "unproven",
+] }
+embedded-hal = { package = "embedded-hal", version = "1.0" }
+embedded-hal-async = { version = "1.0" }
+embedded-hal-nb = { version = "1.0" }
+embedded-io-async = { version = "0.6.1" }
+nb = "1.1.0"
+
+[dev-dependencies]
+defmt-rtt = "1.0"
+panic-probe = { version = "1.0", features = ["print-defmt"] }
+
+[features]
+default = []
+
+# Base defmt feature enables core + panic handler
+# Use with one logger feature: defmt-rtt (preferred) or defmt-uart (fallback)
+defmt = ["dep:defmt"]
+
+rt = []
+
+unstable-pac = []
+
+[[example]]
+name = "hello"
+required-features = ["lpuart2"]
+
+[[example]]
+name = "blink"
+required-features = ["gpio", "ostimer0"]
+
+[[example]]
+name = "uart_interrupt"
+required-features = ["lpuart2", "ostimer0"]
+
+[[example]]
+name = "ostimer_alarm"
+required-features = ["lpuart2", "ostimer0"]
+
+[[example]]
+name = "ostimer_async"
+required-features = ["lpuart2", "ostimer0"]
+
+[[example]]
+name = "ostimer_counter"
+required-features = ["lpuart2", "ostimer0"]
+
+[[example]]
+name = "ostimer_race_test"
+required-features = ["lpuart2", "ostimer0"]
+
+[[example]]
+name = "lpuart_polling"
+required-features = ["lpuart2", "ostimer0"]
+
+[[example]]
+name = "lpuart_buffered"
+required-features = ["lpuart2", "ostimer0"]
+
+[[example]]
+name = "rtc_alarm"
+required-features = ["lpuart2", "rtc0"]
+
+[[example]]
+name = "adc_polling"
+required-features = ["adc1", "lpuart2"]
+
+[[example]]
+name = "adc_interrupt"
+required-features = ["adc1", "lpuart2"]
+
+[profile.release]
+debug = 2
+lto = true
+opt-level = "s"
+
+[profile.dev]
+debug = 2
+opt-level = 1
 
-[target.'cfg(target_os = "none")'.dependencies]
-# dependencies for no-std targets
 
-[lints.clippy]
-suspicious = "forbid"
-correctness = "forbid"
-perf = "forbid"
-style = "forbid"
diff --git a/Embed.toml b/Embed.toml
new file mode 100644
index 000000000..40218c8bf
--- /dev/null
+++ b/Embed.toml
@@ -0,0 +1,28 @@
+[default.probe]
+# Use the first available probe
+protocol = "Swd"
+speed = 1000
+
+[default.flashing]
+# Attach-only: don't flash (we already loaded to RAM)
+enabled = false
+
+[default.reset]
+# Don't reset; keep running app started by run_jlink_noblock.sh
+enabled = false
+
+[default.general]
+# The chip name of the target
+chip = "MCXA276"
+
+[default.gdb]
+# Whether or not a GDB server should be opened after loading
+enabled = false
+
+[default.rtt]
+# Enable RTT for debugging output
+enabled = true
+
+# Increase timeout for RTT CB discovery
+up_channels = [ { channel = 0, mode = "BlockIfFull" } ]
+timeout = 5000
diff --git a/LICENSE b/LICENSE
index 75092dc47..479657c89 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,6 +1,6 @@
 MIT License
 
-Copyright (c) 2025 Open Device Partnership
+Copyright (c) 2025 OEMWCSE
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal
@@ -18,4 +18,5 @@ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
\ No newline at end of file
+SOFTWARE.
+
diff --git a/README.md b/README.md
index 60b09c0a6..8a93b5f4a 100644
--- a/README.md
+++ b/README.md
@@ -1,63 +1,362 @@
-# embedded-rust-template
-Template repository for Embedded Rust development
+# Embassy MCXA276 HAL
 
-## Customizing This Template
+A Hardware Abstraction Layer (HAL) for the NXP MCXA276 microcontroller
+using the Embassy async framework. This HAL provides safe, idiomatic
+Rust interfaces for GPIO, UART, and OSTIMER peripherals.
 
-### Changing the Target Architecture
+## Prerequisites
 
-This template is configured for `thumbv8m.main-none-eabihf`, by default, but you can modify it for other targets (i.e. `aarch64-unknown-none`):
+### Ubuntu/Debian Setup
 
-1. **VSCode Settings**: Update the target in `.vscode/settings.json`:
-   ```json
-   "rust-analyzer.cargo.target": "your-target-architecture"
-   ```
+```bash
+# Install Rust toolchain
+curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
+source ~/.cargo/env
 
+# Add target for MCXA276 (ARM Cortex-M33)
+rustup target add thumbv8m.main-none-eabihf
 
-This configuration ensures that:
-- Only the specified target architecture is analyzed, not the host platform
-- Code is checked against the no_std environment
+# Install required tools
+sudo apt update
+sudo apt install -y gdb-multiarch curl wget
 
-To temporarily analyze code for the host platform instead, you can remove the `rust-analyzer.cargo.target` setting.
+# Install probe-rs for running and debugging
+cargo install probe-rs --features cli
+```
+
+### Windows Setup
+
+- Install Rust via https://rustup.rs (default options are fine)
+- Add the MCXA276 target:
+  ```powershell
+  rustup target add thumbv8m.main-none-eabihf
+  ```
+- Install probe-rs CLI (we will use it directly; no GDB required):
+  ```powershell
+  cargo install probe-rs --features cli
+  ```
+- Install a serial terminal (e.g., Tera Term): https://ttssh2.osdn.jp/
+- USB drivers: Windows 10/11 usually picks up the board as a USB CDC device automatically (COM port)
+
+### Hardware Requirements
+
+- NXP FRDM-MCXA276 development board
+- Debug probe (CMSIS-DAP compatible)
+- USB cable for power and programming
+
+## Examples
+
+This HAL includes several examples demonstrating different peripherals:
+
+### GPIO Examples
+
+#### `blink`
+Blinks an LED connected to GPIO pin. Demonstrates basic GPIO output operations.
+
+### UART Examples
+
+#### `hello`
+Interactive UART2 demo: prints a banner and supports `help`, `echo <text>`, `hex <byte>`.
+
+### OSTIMER Examples
+
+#### `ostimer_alarm`
+
+Demonstrates setting and waiting for OSTIMER alarms.
+
+#### `ostimer_async`
+Shows asynchronous OSTIMER operations with Embassy's async runtime.
+
+#### `ostimer_counter`
+Demonstrates OSTIMER counter functionality.
+
+#### `ostimer_race_test`
+Advanced example testing OSTIMER race conditions and synchronization.
+
+### RTC Example
+
+#### `rtc_alarm`
+Demonstrates how to enable and use the RTC to generate an interrupt after 10seconds.
+
+## Build and Run
+
+### Using probe-rs
+
+All examples require specifying your debug probe. First, find your probe ID:
 
-2. **GitHub Workflows**: Modify the target in two workflow files:
-   - `.github/workflows/nostd.yml`: Update the targets in the matrix:
-     ```yaml
-     matrix:
-       target: [your-target-architecture]
-     ```
-   - `.github/workflows/check.yml`: If there are any target-specific checks, update them accordingly.
+```bash
+probe-rs list
+```
+
+Then run examples with your probe ID (replace `1fc9:0143:H3AYDQVQMTROB` with your actual probe):
+
+```bash
+# GPIO blink example
+PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "gpio ostimer0" --example blink
+
+
+
+# UART hello example
+PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example hello
+
+# OSTIMER examples
+PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm
+PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_async
+PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_counter
+PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_race_test
+
+# RTC example
+PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 rtc0" --example rtc_alarm
+```
+
+**Note:** All examples run from RAM, not flash memory. They are loaded directly into RAM for faster development iteration.
+
+**Important:** After pressing the RESET button on the board, the first `cargo run` attempt may fail with a connection error. This is expected - simply run the command again and it will work. The run.sh script now properly sets the Vector Table Offset Register (VTOR) to point to the RAM-based vector table, ensuring the correct stack pointer and reset vector are used.
 
-3. **Cargo Configuration**: If needed, you can add target-specific configuration in a `.cargo/config.toml` file.
+```console
+smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --release --features "gpio ostimer0" --example blink
+    Finished `release` profile [optimized + debuginfo] target(s) in 0.07s
+     Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/release/examples/blink`
+probe-rs gdb server failed to connect to target. Log:
+----- probe-rs gdb log -----
+  Error: Connecting to the chip was unsuccessful.
 
-### Converting from Binary to Library
+  Caused by:
+      0: An ARM specific error occurred.
+      1: Error using access port FullyQualifiedApAddress { dp: Default, ap: V1(0) }.
+      2: Failed to read register DRW at address 0xd0c
+      3: An error occurred in the communication with an access port or debug port.
+      4: Target device responded with a FAULT response to the request.
+smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --release --features "gpio ostimer0" --example blink
+    Finished `release` profile [optimized + debuginfo] target(s) in 0.02s
+     Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/release/examples/blink`
+```
+
+### Additional UART Examples
+
+#### `uart_interrupt`
+Interrupt-driven UART2 echo. Type in the serial terminal; each byte is echoed back from the IRQ handler path.
 
-To convert this project from a binary to a library:
+#### `lpuart_polling`
+Blocking TX/RX echo over UART2 using the simple polling driver.
 
-1. **Cargo.toml**: Update your project structure:
-   ```toml
-   [lib]
-   name = "your_library_name"
-   ```
+#### `lpuart_buffered`
+Async buffered driver with separate TX/RX tasks; echoes typed characters in chunks.
 
-2. **Directory Structure**:
-   - For a library, ensure you have a `src/lib.rs` file instead of `src/main.rs`
-   - Move your code from `main.rs` to `lib.rs` and adjust as needed
+Pins: UART2 TX=P2_2, RX=P2_3 (ALT3), 115200 8N1.
 
-3. **No-std Configuration**: If you're creating a no-std library, ensure you have:
-   ```rust
-   // In lib.rs
-   #![cfg_attr(target_os = "none", no_std)]
-   // Add other attributes as needed
-   ```
+### ADC Examples
 
-### Project Dependencies
+#### `adc_polling`
+Configures ADC1 channel A8 (pin P1_10) and prints conversion values to UART2 periodically.
 
-Update the dependencies in `Cargo.toml` based on your target platform:
+#### `adc_interrupt`
+Triggers a conversion and signals completion via ADC1 interrupt, printing a notification on UART2.
 
-```toml
-[dependencies]
-# Common dependencies for all targets
+```console
+0x20002040 in ?? ()
+Supported Commands:
 
-[target.'cfg(target_os = "none")'.dependencies]
-# Dependencies for no-std targets
+    info - print session information
+    reset - reset target
+    reset halt - reset target and halt afterwards
+
+Loading section .vector_table, size 0x224 lma 0x20000000
+Loading section .text, size 0x97e lma 0x20000224
+Loading section .Reset, size 0x58 lma 0x20000ba4
+Loading section .rodata, size 0x28 lma 0x20000bfc
+Start address 0x20000ba4, load size 3106
+Transfer rate: 13 KB/sec, 776 bytes/write.
 ```
+
+then I see the LED blinking. I press CTRL+C to exit. It will show me ^C
+
+```console
+Program received signal SIGINT, Interrupt.
+0x20000880 in embassy_executor::arch::thread::Executor::run<blink::__cortex_m_rt_main::{closure_env#0}> (self=0x200027e8, init=...) at /home/smw016108/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/embassy-executor-0.9.1/src/arch/cortex_m.rs:106
+106                         asm!("wfe");
+[Inferior 1 (process 1) detached]
+Program loaded and started (no reset)
+smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ \
+
+Then I press RESET again and I want to run another example, like ostimer_alarm. I open the console using sudo picocom -b 115200 /dev/ttyACM0 and I start running the example:
+
+smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.02s
+     Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm`
+probe-rs gdb server failed to connect to target. Log:
+----- probe-rs gdb log -----
+  Error: Connecting to the chip was unsuccessful.
+
+  Caused by:
+      0: An ARM specific error occurred.
+      1: Error using access port FullyQualifiedApAddress { dp: Default, ap: V1(0) }.
+      2: Failed to read register DRW at address 0xd0c
+      3: An error occurred in the communication with an access port or debug port.
+      4: Target device responded with a FAULT response to the request.
+smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$ PROBE=1fc9:0143:H3AYDQVQMTROB cargo run --features "lpuart2 ostimer0" --example ostimer_alarm
+    Finished `dev` profile [optimized + debuginfo] target(s) in 0.02s
+     Running `/home/smw016108/Downloads/nxp/rust/uart/embassy-mcxa276/./run.sh target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm`
+0x20002040 in core::panicking::panic_const::panic_const_mul_overflow () at library/core/src/panicking.rs:175
+warning: 175    library/core/src/panicking.rs: No such file or directory
+Supported Commands:
+
+    info - print session information
+    reset - reset target
+    reset halt - reset target and halt afterwards
+
+Loading section .vector_table, size 0x224 lma 0x20000000
+Loading section .text, size 0x2226 lma 0x20000224
+Loading section .Reset, size 0x58 lma 0x2000244c
+Loading section .rodata, size 0x6dc lma 0x200024a4
+Start address 0x2000244c, load size 11134
+Transfer rate: 16 KB/sec, 1855 bytes/write.
+```
+
+I can see in the console
+
+```console
+OSTIMER Alarm Example
+Scheduling alarm for 2 seconds...
+Alarm scheduled successfully
+Alarm expired! Callback executed.
+Scheduling another alarm for 3 seconds...
+Alarm scheduled. Waiting 1 second then canceling...
+Alarm canceled
+Alarm was successfully canceled
+Example complete
+```
+
+then I press CTRL+C to stop running
+
+```console
+^C
+Program received signal SIGINT, Interrupt.
+0x20000e64 in embassy_executor::arch::thread::Executor::run<ostimer_alarm::__cortex_m_rt_main::{closure_env#0}> (self=0x200027e8, init=...) at /home/smw016108/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/embassy-executor-0.9.1/src/arch/cortex_m.rs:106
+106                         asm!("wfe");
+[Inferior 1 (process 1) detached]
+Program loaded and started (no reset)
+smw016108@smw016108:~/Downloads/nxp/rust/uart/embassy-mcxa276$
+```
+
+### Windows: Running examples (RAM, no RTT/defmt)
+
+Important: On Windows, do not use `cargo run` because `.cargo/config.toml` sets a Linux-only runner (`./run.sh`). Instead, use `probe-rs run` directly.
+
+1) Find your probe and COM port
+- List probes:
+
+  ```console
+  probe-rs list
+  ```
+- If multiple probes are attached, set the specific one (replace with your ID):
+
+  ```console
+  $env:PROBE_RS_PROBE = "1366:0101:000600110607"
+  ```
+
+- Check Windows Device Manager → Ports (COM & LPT) for the board’s COM port.
+
+2) Build the example
+
+```console
+cargo build --example hello --features "lpuart2"
+```
+
+3) Run from RAM with probe-rs
+
+```console
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/hello
+```
+You will see a short probe-rs warning like "unknown variant, try to set watch point"; it’s harmless.
+
+4) View output in Tera Term
+- Open Tera Term, select the board’s COMx port, 115200 8N1
+- Expected behavior per example:
+  - hello: prints a banner; simple UART output
+  - lpuart_polling / lpuart_buffered / uart_interrupt: echo typed characters
+  - adc_polling: prints ADC values periodically (ADC1 channel A8 on P1_10)
+  - adc_interrupt: prints "*** ADC interrupt TRIGGERED! ***" upon conversion completion
+  - blink: LED on PIO3_18 blinks "SOS" pattern
+  - rtc_alarm: schedules, cancels and reports alarm events on UART
+
+Notes
+- All examples run from RAM (not flashed). Reset clears the program.
+- If the first attempt after a reset fails to connect, just run the command again.
+- UART2 pins: TX=P2_2, RX=P2_3 (ALT3), 115200 8N1.
+
+Quick commands for other examples:
+
+```console
+# Build
+cargo build --example blink            --features "gpio ostimer0"
+cargo build --example lpuart_polling   --features "lpuart2 ostimer0"
+cargo build --example lpuart_buffered  --features "lpuart2 ostimer0"
+cargo build --example uart_interrupt   --features "lpuart2 ostimer0"
+cargo build --example rtc_alarm        --features "lpuart2 rtc0"
+cargo build --example adc_polling      --features "adc1 lpuart2"
+cargo build --example adc_interrupt    --features "adc1 lpuart2"
+
+# Run (RAM)
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/blink
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/lpuart_polling
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/lpuart_buffered
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/uart_interrupt
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/rtc_alarm
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_polling
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/adc_interrupt
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_alarm
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_async
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_counter
+probe-rs run --chip MCXA276 --protocol swd --speed 1000 target/thumbv8m.main-none-eabihf/debug/examples/ostimer_race_test
+```
+
+How I tested on Windows
+- Windows 11; Rust stable; probe-rs 0.29.x
+- Built each example as above; ran with `probe-rs run` (RAM execution)
+- Observed UART output in Tera Term at 115200 8N1; all examples behaved as expected
+- No RTT/defmt used; purely UART or LED observation
+
+### Build Only
+
+To build without running:
+
+```console
+cargo build --features "gpio ostimer0" --example blink
+cargo build --features "lpuart2 ostimer0" --example hello
+cargo build --features "lpuart2 ostimer0" --example ostimer_alarm
+cargo build --features "lpuart2 rtc0" --example rtc_alarm
+# etc.
+```
+
+## Development Notes
+
+### Critical Fix: MCXA276 Interrupt Vector Table
+
+
+Update (SVD 25.06.00, mcxa-pac a9dd33): No manual PAC edits are required anymore. OS_EVENT and WAKETIMER0 are present and the vector table is correct. The section below is kept for historical context.
+**Problem:** The OSTIMER examples crashed during interrupt handling with a hardfault (SP=0x00000000). Investigation revealed the OS_EVENT interrupt vector was NULL in the vector table, causing the CPU to jump to address 0 when OSTIMER interrupts fired.
+
+**Root Cause:** The `mcxa276-pac/src/lib.rs` file (generated from the SVD file) was missing the `WAKETIMER0` interrupt handler declaration. This caused the `__INTERRUPTS` array to have an off-by-one error, placing OS_EVENT at IRQ 58 instead of the correct IRQ 57 position.
+
+**Solution:** Manually edited `mcxa276-pac/src/lib.rs` to add the missing WAKETIMER0 interrupt:
+
+1. Added `fn WAKETIMER0()` to the `extern "C"` block
+2. Fixed the `__INTERRUPTS: [Vector; 122]` array sequence:
+   - Changed from: `LPTMR0, _reserved, _reserved, OS_EVENT, _reserved, UTICK0, ...`
+   - Changed to: `LPTMR0, _reserved, OS_EVENT, WAKETIMER0, UTICK0, WWDT0, _reserved, ADC0, ...`
+3. Added `WAKETIMER0 = 58` to the `Interrupt` enum
+
+**Verification:** Binary analysis confirmed OS_EVENT is now at the correct position:
+- IRQ 57 = word 73 = offset 0x124 in vector table
+- OS_EVENT handler: 0x20000BB1 (verified with `arm-none-eabi-objdump`)
+
+**Note:** This is likely an issue with the NXP MCXA276.svd file or svd2rust generation. The WAKETIMER0 peripheral exists in the PAC but the interrupt handler was missing. Future regeneration of the PAC from SVD may require reapplying this fix.
+
+### Warning: Avoid `#[inline(always)]` in Performance-Critical Code
+
+Using `#[inline(always)]` can cause the Rust compiler to generate incorrect assembly, leading to register corruption or unexpected behavior. For example, in tight polling loops like those in the OSTIMER driver, this attribute may result in invalid instructions that zero registers (e.g., `movs r1, r0` causing r1=0), triggering hardfaults.
+
+## License
+
+This project is licensed under MIT OR Apache-2.0.
diff --git a/SECURITY.md b/SECURITY.md
index 6ed358156..5357b8824 100644
--- a/SECURITY.md
+++ b/SECURITY.md
@@ -63,4 +63,4 @@ An embargo can be called for in various cases:
 If we determine that an issue you report requires an embargo, we will discuss
 this with you and try to find a reasonable expiry date (aka “embargo
 completion date”), as well as who should be included in the list of
-need-to-know people.
\ No newline at end of file
+need-to-know people.
diff --git a/SW-Content-Register.txt b/SW-Content-Register.txt
new file mode 100644
index 000000000..09f879c2f
--- /dev/null
+++ b/SW-Content-Register.txt
@@ -0,0 +1,78 @@
+Release Name: Embassy MCXA276 HAL
+Release Version: 0.1.0
+Package License: MIT (see ./License.txt)
+Note: The crate is dual-licensed “MIT OR Apache-2.0” per Cargo.toml; choosing MIT satisfies the dual-license terms.
+
+Scope of this Register
+This file documents software content that is part of this repository and, for transparency, lists major non-vendored Rust dependencies that are resolved from crates.io during builds. Components that are not present in the repository (e.g., external crates) are listed under “Non‑vendored Rust dependencies”.
+
+Repository Components (included in this release)
+
+embassy_mcxa276_hal           Name: Embassy MCXA276 HAL (library + examples)
+                               Version: 0.1.0
+                               Outgoing License: MIT
+                               License File: ./License.txt
+                               Format: Rust source code, examples, scripts, linker scripts
+                               Description: Hardware Abstraction Layer for NXP MCXA276 using the Embassy async framework. Implements drivers and helpers for:
+                                 - LPUART2 (UART), OSTIMER0, RTC0, ADC1, GPIO
+                                 - Embassy integration (executors, time)
+                               Location: ./src, ./examples, ./build.rs, ./memory.x, ./ram.ld, ./defmt.x, ./.cargo/config.toml, ./run.sh, ./tools/
+                               Origin: OEMWCSE (MIT)
+                               URL: https://bitbucket.sw.nxp.com/scm/oemwcse/mcxa_rust.git
+
+mcxa276_pac                   Name: MCXA276 Peripheral Access Crate (PAC)
+                               Version: 0.1.0
+                               Outgoing License: MIT OR Apache-2.0
+                               License File: (see crate metadata)
+                               Format: Rust source code (auto-generated PAC)
+                               Description: Auto-generated register mappings for MCXA276 peripherals (svd2rust). Includes device.x and interrupt vectors.
+                               Location: External (git): https://github.com/bogdan-petru/mcxa-pac (pinned rev a9dd3301)
+                               Origin: Generated by svdtools + svd2rust from NXP SVD 25.06.00
+                               URL: N/A (generated from NXP SVD)
+
+examples                      Name: Example applications
+                               Version: N/A
+                               Outgoing License: MIT
+                               License File: ./License.txt
+                               Format: Rust source code (examples)
+                               Description: Demonstrations for HAL peripherals and features:
+                                 - hello, blink
+                                 - lpuart_polling, lpuart_buffered, uart_interrupt
+                                 - rtc_alarm
+                                 - adc_polling, adc_interrupt
+                                 - ostimer_alarm, ostimer_async, ostimer_counter, ostimer_race_test
+                               Location: ./examples
+                               Origin: OEMWCSE (MIT)
+
+Non‑vendored Rust dependencies (resolved from crates.io at build time)
+The following crates are not vendored in this repository. They are fetched during builds via Cargo. See Cargo.lock for exact versions. License summaries below are for convenience; consult each crate for authoritative terms.
+
+cortex-m                      License: MIT OR Apache-2.0    Purpose: Cortex-M core support
+cortex-m-rt                   License: MIT OR Apache-2.0    Purpose: Cortex-M runtime (vectors, reset)
+embassy-executor              License: MIT OR Apache-2.0    Purpose: Async executor for Cortex-M
+embassy-time (+ driver)       License: MIT OR Apache-2.0    Purpose: Time abstraction and drivers
+embassy-sync                  License: MIT OR Apache-2.0    Purpose: No-std synchronization primitives
+embassy-embedded-hal          License: MIT OR Apache-2.0    Purpose: Traits/adapters for embedded-hal
+embassy-hal-internal          License: MIT OR Apache-2.0    Purpose: HAL building blocks (peripherals!)
+embedded-hal (1.0)            License: MIT OR Apache-2.0    Purpose: Core embedded hardware traits
+embedded-hal (0.2.6)          License: MIT OR Apache-2.0    Purpose: Legacy HAL traits ("unproven")
+embedded-hal-async            License: MIT OR Apache-2.0    Purpose: Async HAL traits
+embedded-hal-nb               License: MIT OR Apache-2.0    Purpose: Non-blocking HAL traits
+embedded-io / embedded-io-async License: MIT OR Apache-2.0  Purpose: IO traits
+critical-section              License: MIT OR Apache-2.0    Purpose: Critical-section abstraction
+heapless                      License: MIT OR Apache-2.0    Purpose: Fixed-capacity data structures
+paste                         License: MIT OR Apache-2.0    Purpose: Macro hygiene utility
+nb                            License: MIT OR Apache-2.0    Purpose: Non-blocking result type
+vcell                         License: MIT OR Apache-2.0    Purpose: Volatile cell (PAC dependency)
+
+defmt, defmt-rtt, rtt-target, panic-probe   License: MIT OR Apache-2.0    Purpose: Optional (feature-gated) logging/panic crates
+
+Attribution notes
+- MCXA276 PAC is sourced as an external dependency (see Cargo.toml). SVD 25.06.00 already includes OS_EVENT and WAKETIMER0 interrupts (no local fixes).
+- Examples run from RAM using custom linker setup; see README.txt for platform-specific instructions.
+
+Compliance
+- This repository’s distributed source is covered by MIT (see License.txt). Where crates are pulled from crates.io, those crates retain their own licenses; the dual-license compatibility (MIT OR Apache-2.0) is standard in the Rust embedded ecosystem and is compatible with this project’s selected MIT distribution.
+
+
+
diff --git a/build.rs b/build.rs
new file mode 100644
index 000000000..645843590
--- /dev/null
+++ b/build.rs
@@ -0,0 +1,20 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+
+    // Generate memory.x - put "FLASH" at start of RAM, RAM after "FLASH"
+    // cortex-m-rt expects FLASH for code, RAM for data/bss/stack
+    // Both are in RAM, but separated to satisfy cortex-m-rt's expectations
+    // MCXA276 has 128KB RAM total
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(b"/* MCXA276 RAM-execution: FLASH region holds code, RAM region for data/stack */\nMEMORY { FLASH : ORIGIN = 0x20000000, LENGTH = 64K\n         RAM : ORIGIN = 0x20010000, LENGTH = 64K }\n")
+        .unwrap();
+
+    println!("cargo:rustc-link-search={}", out.display());
+    println!("cargo:rerun-if-changed=memory.x");
+}
diff --git a/defmt.x b/defmt.x
new file mode 100644
index 000000000..dbd6d0850
--- /dev/null
+++ b/defmt.x
@@ -0,0 +1,6 @@
+/*
+ Dummy defmt.x to satisfy -Tdefmt.x when building without the `defmt` feature.
+ When `defmt` is enabled, the real defmt.x provided by the defmt crate is used via the linker search path.
+ This file intentionally contains no SECTIONS so it won't override ram.ld.
+*/
+
diff --git a/deny.toml b/deny.toml
index 9ddd12fca..7097f2f55 100644
--- a/deny.toml
+++ b/deny.toml
@@ -74,8 +74,9 @@ ignore = [
     #{ id = "RUSTSEC-0000-0000", reason = "you can specify a reason the advisory is ignored" },
     #"[email protected]", # you can also ignore yanked crate versions if you wish
     #{ crate = "[email protected]", reason = "you can specify why you are ignoring the yanked crate" },
-    { id = "RUSTSEC-2024-0370", reason = "proc-macro-error is unmaintained, no safe upgrade available, need upstream dependencies to migrate away from it." },
+    # { id = "RUSTSEC-2024-0370", reason = "proc-macro-error is unmaintained, no safe upgrade available, need upstream dependencies to migrate away from it." },
     { id = "RUSTSEC-2024-0436", reason = "there are no suitable replacements for paste right now; paste has been archived as read-only. It only affects compile time concatenation in macros. We will allow it for now" },
+    # { id = "RUSTSEC-2023-0089", reason = "this is a deprecation warning for a dependency of a dependency. https://github.com/jamesmunns/postcard/issues/223 tracks fixing the dependency; until that's resolved, we can accept the deprecated code as it has no known vulnerabilities."}
 ]
 # If this is true, then cargo deny will use the git executable to fetch advisory database.
 # If this is false, then it uses a built-in git library.
@@ -93,8 +94,9 @@ ignore = [
 allow = [
     "MIT",
     "Apache-2.0",
+
+    # unicode-ident 1.0.14 switched from Unicode-DFS-2016 to Unicode-3.0 license.
     "Unicode-3.0",
-    "BSD-3-Clause",
     #"Apache-2.0 WITH LLVM-exception",
 ]
 # The confidence threshold for detecting a license from license text.
@@ -232,7 +234,7 @@ allow-git = []
 
 [sources.allow-org]
 # github.com organizations to allow git sources for
-github = ["embassy-rs"]
+github = ["OpenDevicePartnership"]
 # gitlab.com organizations to allow git sources for
 gitlab = []
 # bitbucket.org organizations to allow git sources for
diff --git a/examples/adc_interrupt.rs b/examples/adc_interrupt.rs
new file mode 100644
index 000000000..f0df3196c
--- /dev/null
+++ b/examples/adc_interrupt.rs
@@ -0,0 +1,89 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use hal::adc::{LpadcConfig, TriggerPriorityPolicy};
+use hal::pac::adc1::cfg::{Pwrsel, Refsel};
+use hal::pac::adc1::cmdl1::{Adch, Mode};
+use hal::pac::adc1::ctrl::CalAvgs;
+use hal::pac::adc1::tctrl::Tcmd;
+use hal::uart;
+use {cortex_m, embassy_mcxa276 as hal};
+mod common;
+
+use hal::{bind_interrupts, InterruptExt};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    ADC1 => hal::adc::AdcHandler;
+});
+
+#[used]
+#[no_mangle]
+static KEEP_ADC: unsafe extern "C" fn() = ADC1;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    unsafe {
+        common::init_uart2(hal::pac());
+    }
+
+    let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
+    let uart = uart::Uart::<uart::Lpuart2>::new(p.LPUART2, uart::Config::new(src));
+
+    uart.write_str_blocking("\r\n=== ADC interrupt Example ===\r\n");
+
+    unsafe {
+        common::init_adc(hal::pac());
+    }
+
+    let adc_config = LpadcConfig {
+        enable_in_doze_mode: true,
+        conversion_average_mode: CalAvgs::Average128,
+        enable_analog_preliminary: true,
+        power_up_delay: 0x80,
+        reference_voltage_source: Refsel::Option3,
+        power_level_mode: Pwrsel::Lowest,
+        trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
+        enable_conv_pause: false,
+        conv_pause_delay: 0,
+        fifo_watermark: 0,
+    };
+    let adc = hal::adc::Adc::<hal::adc::Adc1>::new(p.ADC1, adc_config);
+
+    adc.do_offset_calibration();
+    adc.do_auto_calibration();
+
+    let mut conv_command_config = adc.get_default_conv_command_config();
+    conv_command_config.channel_number = Adch::SelectCorrespondingChannel8;
+    conv_command_config.conversion_resolution_mode = Mode::Data16Bits;
+    adc.set_conv_command_config(1, &conv_command_config);
+
+    let mut conv_trigger_config = adc.get_default_conv_trigger_config();
+    conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1;
+    conv_trigger_config.enable_hardware_trigger = false;
+    adc.set_conv_trigger_config(0, &conv_trigger_config);
+
+    uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n");
+
+    adc.enable_interrupt(0x1);
+
+    unsafe {
+        hal::interrupt::ADC1.enable();
+    }
+
+    unsafe {
+        cortex_m::interrupt::enable();
+    }
+
+    loop {
+        adc.do_software_trigger(1);
+        while !adc.is_interrupt_triggered() {
+            // Wait until the interrupt is triggered
+        }
+        uart.write_str_blocking("\r\n*** ADC interrupt TRIGGERED! ***\r\n");
+        //TBD need to print the value
+    }
+}
diff --git a/examples/adc_polling.rs b/examples/adc_polling.rs
new file mode 100644
index 000000000..561500d2d
--- /dev/null
+++ b/examples/adc_polling.rs
@@ -0,0 +1,79 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa276 as hal;
+use hal::adc::{ConvResult, LpadcConfig, TriggerPriorityPolicy};
+use hal::pac::adc1::cfg::{Pwrsel, Refsel};
+use hal::pac::adc1::cmdl1::{Adch, Mode};
+use hal::pac::adc1::ctrl::CalAvgs;
+use hal::pac::adc1::tctrl::Tcmd;
+use hal::uart;
+
+mod common;
+
+use core::fmt::Write;
+
+use heapless::String;
+use {defmt_rtt as _, panic_probe as _};
+
+const G_LPADC_RESULT_SHIFT: u32 = 0;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    unsafe {
+        common::init_uart2(hal::pac());
+    }
+
+    let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
+    let uart = uart::Uart::<uart::Lpuart2>::new(p.LPUART2, uart::Config::new(src));
+
+    uart.write_str_blocking("\r\n=== ADC polling Example ===\r\n");
+
+    unsafe {
+        common::init_adc(hal::pac());
+    }
+
+    let adc_config = LpadcConfig {
+        enable_in_doze_mode: true,
+        conversion_average_mode: CalAvgs::Average128,
+        enable_analog_preliminary: true,
+        power_up_delay: 0x80,
+        reference_voltage_source: Refsel::Option3,
+        power_level_mode: Pwrsel::Lowest,
+        trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
+        enable_conv_pause: false,
+        conv_pause_delay: 0,
+        fifo_watermark: 0,
+    };
+    let adc = hal::adc::Adc::<hal::adc::Adc1>::new(p.ADC1, adc_config);
+
+    adc.do_offset_calibration();
+    adc.do_auto_calibration();
+
+    let mut conv_command_config = adc.get_default_conv_command_config();
+    conv_command_config.channel_number = Adch::SelectCorrespondingChannel8;
+    conv_command_config.conversion_resolution_mode = Mode::Data16Bits;
+    adc.set_conv_command_config(1, &conv_command_config);
+
+    let mut conv_trigger_config = adc.get_default_conv_trigger_config();
+    conv_trigger_config.target_command_id = Tcmd::ExecuteCmd1;
+    conv_trigger_config.enable_hardware_trigger = false;
+    adc.set_conv_trigger_config(0, &conv_trigger_config);
+
+    uart.write_str_blocking("\r\n=== ADC configuration done... ===\r\n");
+
+    loop {
+        adc.do_software_trigger(1);
+        let mut result: Option<ConvResult> = None;
+        while result.is_none() {
+            result = hal::adc::get_conv_result();
+        }
+        let value = result.unwrap().conv_value >> G_LPADC_RESULT_SHIFT;
+        let mut buf: String<16> = String::new(); // adjust size as needed
+        write!(buf, "\r\nvalue: {}\r\n", value).unwrap();
+        uart.write_str_blocking(&buf);
+    }
+}
diff --git a/examples/blink.rs b/examples/blink.rs
new file mode 100644
index 000000000..564353d5c
--- /dev/null
+++ b/examples/blink.rs
@@ -0,0 +1,84 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa276 as hal;
+use embassy_time::{Duration, Timer};
+use hal::gpio::pins::PIO3_18;
+use hal::gpio::{Level, Output};
+
+mod common;
+
+use embassy_mcxa276::bind_interrupts;
+
+// Bind only OS_EVENT for timer interrupts
+bind_interrupts!(struct Irqs {
+    OS_EVENT => hal::ostimer::time_driver::OsEventHandler;
+});
+
+#[used]
+#[no_mangle]
+static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let _p = hal::init(hal::config::Config::default());
+
+    // Board-style init: enable LED GPIO/PORT clocks used by blink
+    unsafe {
+        common::init_led(hal::pac());
+    }
+    // Initialize OSTIMER for async timing
+    unsafe {
+        common::init_ostimer0(hal::pac());
+    }
+
+    // Initialize embassy-time global driver backed by OSTIMER0
+    hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000);
+
+    // Configure LED pin for GPIO mode
+    PIO3_18::set_mux_gpio();
+
+    let mut led = Output::new(PIO3_18::degrade(), Level::High);
+
+    // Complex blinking pattern: SOS in Morse code
+    // S: ... (3 short)
+    // O: --- (3 long)
+    // S: ... (3 short)
+    // With pauses between letters and words
+
+    loop {
+        // S: three short blinks
+        for _ in 0..3 {
+            led.set_low();
+            Timer::after(Duration::from_millis(150)).await;
+            led.set_high();
+            Timer::after(Duration::from_millis(150)).await;
+        }
+
+        // Pause between letters
+        Timer::after(Duration::from_millis(300)).await;
+
+        // O: three long blinks
+        for _ in 0..3 {
+            led.set_low();
+            Timer::after(Duration::from_millis(450)).await;
+            led.set_high();
+            Timer::after(Duration::from_millis(150)).await;
+        }
+
+        // Pause between letters
+        Timer::after(Duration::from_millis(300)).await;
+
+        // S: three short blinks
+        for _ in 0..3 {
+            led.set_low();
+            Timer::after(Duration::from_millis(150)).await;
+            led.set_high();
+            Timer::after(Duration::from_millis(150)).await;
+        }
+
+        // Long pause between words (SOS repeats)
+        Timer::after(Duration::from_millis(1000)).await;
+    }
+}
diff --git a/examples/common/mod.rs b/examples/common/mod.rs
new file mode 100644
index 000000000..7ada4c456
--- /dev/null
+++ b/examples/common/mod.rs
@@ -0,0 +1,45 @@
+//! Shared board-specific helpers for the FRDM-MCXA276 examples.
+//! These live with the examples so the HAL stays generic.
+
+use embassy_mcxa276 as hal;
+use hal::{clocks, pins, reset};
+
+/// Initialize clocks and pin muxing for UART2 debug console.
+/// Safe to call multiple times; writes are idempotent for our use.
+#[allow(dead_code)]
+pub unsafe fn init_uart2(p: &hal::pac::Peripherals) {
+    clocks::ensure_frolf_running(p);
+    clocks::enable_uart2_port2(p);
+    reset::release_reset_port2(p);
+    reset::release_reset_lpuart2(p);
+    pins::configure_uart2_pins_port2();
+    clocks::select_uart2_clock(p);
+}
+
+/// Initialize clocks for the LED GPIO/PORT used by the blink example.
+#[allow(dead_code)]
+pub unsafe fn init_led(p: &hal::pac::Peripherals) {
+    clocks::enable_led_port(p);
+    reset::release_reset_gpio3(p);
+    reset::release_reset_port3(p);
+}
+
+/// Initialize clocks for OSTIMER0 (1 MHz source).
+#[allow(dead_code)]
+pub unsafe fn init_ostimer0(p: &hal::pac::Peripherals) {
+    clocks::ensure_frolf_running(p);
+    clocks::enable_ostimer0(p);
+    reset::release_reset_ostimer0(p);
+    clocks::select_ostimer0_clock_1m(p);
+}
+
+/// Initialize clocks and pin muxing for ADC.
+#[allow(dead_code)]
+pub unsafe fn init_adc(p: &hal::pac::Peripherals) {
+    clocks::ensure_frolf_running(p);
+    clocks::enable_adc(p);
+    reset::release_reset_port1(p);
+    reset::release_reset_adc1(p);
+    pins::configure_adc_pins();
+    clocks::select_adc_clock(p);
+}
diff --git a/examples/hello.rs b/examples/hello.rs
new file mode 100644
index 000000000..e39adaced
--- /dev/null
+++ b/examples/hello.rs
@@ -0,0 +1,114 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa276 as hal;
+use hal::uart;
+
+mod common;
+
+use {defmt_rtt as _, panic_probe as _};
+
+/// Simple helper to write a byte as hex to UART
+fn write_hex_byte(uart: &hal::uart::Uart<hal::uart::Lpuart2>, byte: u8) {
+    const HEX_DIGITS: &[u8] = b"0123456789ABCDEF";
+    uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]);
+    uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]);
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    defmt::info!("boot");
+
+    // Board-level init for UART2 clocks and pins.
+    unsafe {
+        common::init_uart2(hal::pac());
+    }
+
+    // Get UART source frequency from clock configuration
+    // Using hardcoded frequency for now - dynamic detection may have issues
+    let src = 12_000_000; // FRO_LF_DIV at 12MHz with DIV=0
+    let uart = uart::Uart::<uart::Lpuart2>::new(p.LPUART2, uart::Config::new(src));
+
+    // Print welcome message before any async delays to guarantee early console output
+    uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n");
+    uart.write_str_blocking("Available commands:\r\n");
+    uart.write_str_blocking("  help     - Show this help\r\n");
+    uart.write_str_blocking("  echo <text> - Echo back the text\r\n");
+    uart.write_str_blocking("  hex <byte> - Display byte in hex (0-255)\r\n");
+    uart.write_str_blocking("Type a command: ");
+
+    let mut buffer = [0u8; 64];
+    let mut buf_idx = 0;
+
+    loop {
+        // Read a byte from UART
+        let byte = uart.read_byte_blocking();
+
+        // Echo the character back
+        if byte == b'\r' || byte == b'\n' {
+            // Enter pressed - process command
+            uart.write_str_blocking("\r\n");
+
+            if buf_idx > 0 {
+                let command = &buffer[0..buf_idx];
+
+                if command == b"help" {
+                    uart.write_str_blocking("Available commands:\r\n");
+                    uart.write_str_blocking("  help     - Show this help\r\n");
+                    uart.write_str_blocking("  echo <text> - Echo back the text\r\n");
+                    uart.write_str_blocking("  hex <byte> - Display byte in hex (0-255)\r\n");
+                } else if command.starts_with(b"echo ") && command.len() > 5 {
+                    uart.write_str_blocking("Echo: ");
+                    uart.write_str_blocking(core::str::from_utf8(&command[5..]).unwrap_or(""));
+                    uart.write_str_blocking("\r\n");
+                } else if command.starts_with(b"hex ") && command.len() > 4 {
+                    // Parse the byte value
+                    let num_str = &command[4..];
+                    if let Ok(num) = parse_u8(num_str) {
+                        uart.write_str_blocking("Hex: 0x");
+                        write_hex_byte(&uart, num);
+                        uart.write_str_blocking("\r\n");
+                    } else {
+                        uart.write_str_blocking("Invalid number for hex command\r\n");
+                    }
+                } else if command.len() > 0 {
+                    uart.write_str_blocking("Unknown command: ");
+                    uart.write_str_blocking(core::str::from_utf8(command).unwrap_or(""));
+                    uart.write_str_blocking("\r\n");
+                }
+            }
+
+            // Reset buffer and prompt
+            buf_idx = 0;
+            uart.write_str_blocking("Type a command: ");
+        } else if byte == 8 || byte == 127 {
+            // Backspace
+            if buf_idx > 0 {
+                buf_idx -= 1;
+                uart.write_str_blocking("\x08 \x08"); // Erase character
+            }
+        } else if buf_idx < buffer.len() - 1 {
+            // Regular character
+            buffer[buf_idx] = byte;
+            buf_idx += 1;
+            uart.write_byte(byte);
+        }
+    }
+}
+
+/// Simple parser for u8 from ASCII bytes
+fn parse_u8(bytes: &[u8]) -> Result<u8, ()> {
+    let mut result = 0u8;
+    for &b in bytes {
+        if b >= b'0' && b <= b'9' {
+            result = result.checked_mul(10).ok_or(())?;
+            result = result.checked_add(b - b'0').ok_or(())?;
+        } else {
+            return Err(());
+        }
+    }
+    Ok(result)
+}
diff --git a/examples/lpuart_buffered.rs b/examples/lpuart_buffered.rs
new file mode 100644
index 000000000..30ba3f333
--- /dev/null
+++ b/examples/lpuart_buffered.rs
@@ -0,0 +1,77 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa276 as hal;
+use embassy_mcxa276::interrupt::typelevel::Handler;
+use embassy_mcxa276::lpuart::buffered::BufferedLpuart;
+use embassy_mcxa276::{bind_interrupts, lpuart};
+use embedded_io_async::{Read, Write};
+
+mod common;
+
+// Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver
+bind_interrupts!(struct Irqs {
+    LPUART2 => lpuart::buffered::BufferedInterruptHandler::<lpuart::lib::peripherals::LPUART2>;
+});
+
+// Wrapper function for the interrupt handler
+unsafe extern "C" fn lpuart2_handler() {
+    lpuart::buffered::BufferedInterruptHandler::<lpuart::lib::peripherals::LPUART2>::on_interrupt();
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let _p = hal::init(hal::config::Config::default());
+    let p2 = lpuart::lib::init();
+
+    unsafe {
+        hal::interrupt::install_irq_handler(mcxa276_pac::Interrupt::LPUART2, lpuart2_handler);
+    }
+
+    // Configure NVIC for LPUART2
+    hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3);
+
+    unsafe {
+        common::init_uart2(hal::pac());
+        common::init_ostimer0(hal::pac());
+    }
+
+    // UART configuration (enable both TX and RX)
+    let config = lpuart::Config {
+        baudrate_bps: 115_200,
+        enable_tx: true,
+        enable_rx: true,
+        rx_fifo_watermark: 0,
+        tx_fifo_watermark: 0,
+        ..Default::default()
+    };
+
+    let mut tx_buf = [0u8; 256];
+    let mut rx_buf = [0u8; 256];
+
+    // Create a buffered LPUART2 instance with both TX and RX
+    let mut uart = BufferedLpuart::new(
+        p2.LPUART2,
+        p2.PIO2_2, // TX pin
+        p2.PIO2_3, // RX pin
+        Irqs,
+        &mut tx_buf,
+        &mut rx_buf,
+        config,
+    )
+    .unwrap();
+
+    // Split into TX and RX parts
+    let (tx, rx) = uart.split_ref();
+
+    tx.write(b"Hello buffered LPUART.\r\n").await.unwrap();
+    tx.write(b"Type characters to echo them back.\r\n").await.unwrap();
+
+    // Echo loop
+    let mut buf = [0u8; 4];
+    loop {
+        rx.read_exact(&mut buf[..]).await.unwrap();
+        tx.write_all(&buf[..]).await.unwrap();
+    }
+}
diff --git a/examples/lpuart_polling.rs b/examples/lpuart_polling.rs
new file mode 100644
index 000000000..067c7eb53
--- /dev/null
+++ b/examples/lpuart_polling.rs
@@ -0,0 +1,53 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _};
+
+use crate::hal::lpuart::{lib, Config, Lpuart};
+
+mod common;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let _p = hal::init(hal::config::Config::default());
+    let p2 = lib::init();
+
+    defmt::info!("boot");
+
+    // Board-level init for UART2 clocks and pins.
+    unsafe {
+        common::init_uart2(hal::pac());
+    }
+
+    // Create UART configuration
+    let config = Config {
+        baudrate_bps: 115_200,
+        enable_tx: true,
+        enable_rx: true,
+        ..Default::default()
+    };
+
+    // Create UART instance using LPUART2 with PIO2_2 as TX and PIO2_3 as RX
+    let lpuart = Lpuart::new_blocking(
+        p2.LPUART2, // Peripheral
+        p2.PIO2_2,  // TX pin
+        p2.PIO2_3,  // RX pin
+        config,
+    )
+    .unwrap();
+
+    // Split into separate TX and RX parts
+    let (mut tx, mut rx) = lpuart.split();
+
+    // Write hello messages
+    tx.blocking_write(b"Hello world.\r\n").unwrap();
+    tx.blocking_write(b"Echoing. Type characters...\r\n").unwrap();
+
+    // Echo loop
+    loop {
+        let mut buf = [0u8; 1];
+        rx.blocking_read(&mut buf).unwrap();
+        tx.blocking_write(&buf).unwrap();
+    }
+}
diff --git a/examples/ostimer_alarm.rs b/examples/ostimer_alarm.rs
new file mode 100644
index 000000000..78ca4bbc5
--- /dev/null
+++ b/examples/ostimer_alarm.rs
@@ -0,0 +1,111 @@
+#![no_std]
+#![no_main]
+
+use core::sync::atomic::{AtomicBool, Ordering};
+
+use embassy_executor::Spawner;
+use hal::uart;
+use {cortex_m, embassy_mcxa276 as hal};
+
+mod common;
+
+use embassy_mcxa276::bind_interrupts;
+use {defmt_rtt as _, panic_probe as _};
+
+// Bind only OS_EVENT, and retain the symbol explicitly so it can't be GC'ed.
+bind_interrupts!(struct Irqs {
+    OS_EVENT => hal::ostimer::time_driver::OsEventHandler;
+});
+
+#[used]
+#[no_mangle]
+static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT;
+
+// Global flag for alarm callback
+static ALARM_FLAG: AtomicBool = AtomicBool::new(false);
+
+// Alarm callback function
+fn alarm_callback() {
+    ALARM_FLAG.store(true, Ordering::Release);
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    // Enable/clock OSTIMER0 and UART2 before touching their registers
+    unsafe {
+        common::init_ostimer0(hal::pac());
+    }
+    unsafe {
+        common::init_uart2(hal::pac());
+    }
+    let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
+    let uart = uart::Uart::<uart::Lpuart2>::new(p.LPUART2, uart::Config::new(src));
+    uart.write_str_blocking("OSTIMER Alarm Example\n");
+
+    // Initialize embassy-time global driver backed by OSTIMER0
+    hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000);
+
+    // Create OSTIMER instance
+    let config = hal::ostimer::Config {
+        init_match_max: true,
+        clock_frequency_hz: 1_000_000, // 1MHz
+    };
+    let ostimer = hal::ostimer::Ostimer::<hal::ostimer::Ostimer0>::new(p.OSTIMER0, config, hal::pac());
+
+    // Create alarm with callback
+    let alarm = hal::ostimer::Alarm::new()
+        .with_callback(alarm_callback)
+        .with_flag(&ALARM_FLAG);
+
+    uart.write_str_blocking("Scheduling alarm for 2 seconds...\n");
+
+    // Schedule alarm to expire in 2 seconds (2,000,000 microseconds)
+    let scheduled = ostimer.schedule_alarm_delay(&alarm, 2_000_000);
+    if scheduled {
+        uart.write_str_blocking("Alarm scheduled successfully\n");
+    } else {
+        uart.write_str_blocking("Failed to schedule alarm (would exceed timer capacity)\n");
+        return;
+    }
+
+    // Wait for alarm to expire
+    loop {
+        // Check if alarm has expired
+        if ALARM_FLAG.load(Ordering::Acquire) {
+            uart.write_str_blocking("Alarm expired! Callback executed.\n");
+            break;
+        }
+
+        // Busy wait - don't use Timer::after_millis as it interferes with alarm MATCH
+        for _ in 0..100000 {
+            cortex_m::asm::nop();
+        }
+    }
+
+    // Demonstrate canceling an alarm
+    uart.write_str_blocking("Scheduling another alarm for 3 seconds...\n");
+    ALARM_FLAG.store(false, Ordering::Release); // Reset flag
+
+    let scheduled = ostimer.schedule_alarm_delay(&alarm, 3_000_000);
+    if scheduled {
+        uart.write_str_blocking("Alarm scheduled. Waiting 1 second then canceling...\n");
+
+        // Wait 1 second
+        embassy_time::Timer::after_millis(1000).await;
+
+        // Cancel the alarm
+        ostimer.cancel_alarm(&alarm);
+        uart.write_str_blocking("Alarm canceled\n");
+
+        // Check immediately if alarm flag is set
+        if !ALARM_FLAG.load(Ordering::Acquire) {
+            uart.write_str_blocking("Alarm was successfully canceled\n");
+        } else {
+            uart.write_str_blocking("Alarm fired despite cancellation\n");
+        }
+    }
+
+    uart.write_str_blocking("Example complete\n");
+}
diff --git a/examples/ostimer_async.rs b/examples/ostimer_async.rs
new file mode 100644
index 000000000..27e14e022
--- /dev/null
+++ b/examples/ostimer_async.rs
@@ -0,0 +1,57 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa276 as hal;
+use hal::uart;
+
+mod common;
+
+use embassy_mcxa276::bind_interrupts;
+use embassy_time::{Duration, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+// Bind only OS_EVENT, and retain the symbol explicitly so it can’t be GC’ed.
+bind_interrupts!(struct Irqs {
+    OS_EVENT => hal::ostimer::time_driver::OsEventHandler;
+});
+
+#[used]
+#[no_mangle]
+static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let _p = hal::init(hal::config::Config::default());
+
+    // Enable/clock OSTIMER0 and UART2 before touching their registers
+    unsafe {
+        common::init_ostimer0(hal::pac());
+    }
+    unsafe {
+        common::init_uart2(hal::pac());
+    }
+    let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
+    let uart = uart::Uart::<uart::Lpuart2>::new(_p.LPUART2, uart::Config::new(src));
+    uart.write_str_blocking("boot\n");
+
+    // Avoid mass NVIC writes here; DefaultHandler now safely returns.
+
+    // Initialize embassy-time global driver backed by OSTIMER0 (re-enables OS_EVENT with priority)
+    // The bind_interrupts! macro handles handler binding automatically
+
+    // Initialize OSTIMER with default 1MHz frequency
+    // Adjust this value to match your actual OSTIMER clock frequency
+    hal::ostimer::time_driver::init(hal::config::Config::default().time_interrupt_priority, 1_000_000);
+
+    // Removed force-pend; rely on real hardware match to trigger OS_EVENT.
+
+    // Log using defmt if enabled
+    defmt::info!("OSTIMER async example starting...");
+
+    loop {
+        defmt::info!("tick");
+        uart.write_str_blocking("tick\n");
+        Timer::after(Duration::from_millis(1000)).await;
+    }
+}
diff --git a/examples/ostimer_counter.rs b/examples/ostimer_counter.rs
new file mode 100644
index 000000000..e95140a88
--- /dev/null
+++ b/examples/ostimer_counter.rs
@@ -0,0 +1,128 @@
+//! # OSTIMER Counter Reading and Reset Example
+//!
+//! This example demonstrates the new timer counter reading and reset functionality
+//! of the OSTIMER driver.
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::{Duration, Timer};
+use hal::bind_interrupts;
+use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _};
+
+mod common;
+
+bind_interrupts!(struct Irqs {
+    OS_EVENT => hal::ostimer::time_driver::OsEventHandler;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(Default::default());
+
+    // Enable/clock OSTIMER0 and UART2 before touching their registers
+    unsafe {
+        common::init_ostimer0(hal::pac());
+    }
+    unsafe {
+        common::init_uart2(hal::pac());
+    }
+    let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
+    let mut uart = hal::uart::Uart::<hal::uart::Lpuart2>::new(p.LPUART2, hal::uart::Config::new(src));
+
+    uart.write_str_blocking("OSTIMER Counter Reading and Reset Example\n");
+
+    // Initialize the OSTIMER time driver
+    hal::ostimer::time_driver::init(
+        hal::interrupt::Priority::from(3),
+        1_000_000, // 1MHz clock
+    );
+
+    // Create OSTIMER instance
+    let ostimer = hal::ostimer::Ostimer::<hal::ostimer::Ostimer0>::new(
+        p.OSTIMER0,
+        hal::ostimer::Config {
+            init_match_max: true,
+            clock_frequency_hz: 1_000_000,
+        },
+        hal::pac(),
+    );
+
+    // Read initial counter value
+    let initial_counter = ostimer.now();
+    uart.write_str_blocking("Initial counter value: ");
+    write_u64(&mut uart, initial_counter);
+    uart.write_str_blocking("\n");
+
+    // Wait a bit to let counter increment
+    Timer::after(Duration::from_millis(100)).await;
+
+    // Read counter again
+    let counter_after_wait = ostimer.now();
+    uart.write_str_blocking("Counter after 100ms wait: ");
+    write_u64(&mut uart, counter_after_wait);
+    uart.write_str_blocking("\n");
+    uart.write_str_blocking("Difference: ");
+    write_u64(&mut uart, counter_after_wait - initial_counter);
+    uart.write_str_blocking(" ticks\n");
+
+    // Reset the timer
+    uart.write_str_blocking("Resetting timer...\n");
+    ostimer.reset(hal::pac());
+
+    // Read counter after reset
+    let counter_after_reset = ostimer.now();
+    uart.write_str_blocking("Counter after reset: ");
+    write_u64(&mut uart, counter_after_reset);
+    uart.write_str_blocking("\n");
+
+    // Wait again to verify timer is working
+    Timer::after(Duration::from_millis(50)).await;
+
+    let final_counter = ostimer.now();
+    uart.write_str_blocking("Counter after another 50ms: ");
+    write_u64(&mut uart, final_counter);
+    uart.write_str_blocking("\n");
+    uart.write_str_blocking("Difference after reset: ");
+    write_u64(&mut uart, final_counter - counter_after_reset);
+    uart.write_str_blocking(" ticks\n");
+
+    uart.write_str_blocking("Example complete\n");
+}
+
+// Helper function to write a u64 value as decimal string
+fn write_u64(uart: &mut hal::uart::Uart<hal::uart::Lpuart2>, value: u64) {
+    if value == 0 {
+        uart.write_str_blocking("0");
+        return;
+    }
+
+    let mut buffer = [0u8; 20]; // Enough for max u64
+    let mut i = 0;
+    let mut v = value;
+
+    while v > 0 {
+        buffer[i] = b'0' + (v % 10) as u8;
+        v /= 10;
+        i += 1;
+    }
+
+    // Write digits in reverse order
+    while i > 0 {
+        i -= 1;
+        match buffer[i] {
+            b'0' => uart.write_str_blocking("0"),
+            b'1' => uart.write_str_blocking("1"),
+            b'2' => uart.write_str_blocking("2"),
+            b'3' => uart.write_str_blocking("3"),
+            b'4' => uart.write_str_blocking("4"),
+            b'5' => uart.write_str_blocking("5"),
+            b'6' => uart.write_str_blocking("6"),
+            b'7' => uart.write_str_blocking("7"),
+            b'8' => uart.write_str_blocking("8"),
+            b'9' => uart.write_str_blocking("9"),
+            _ => uart.write_str_blocking("?"),
+        }
+    }
+}
diff --git a/examples/ostimer_race_test.rs b/examples/ostimer_race_test.rs
new file mode 100644
index 000000000..a637b6353
--- /dev/null
+++ b/examples/ostimer_race_test.rs
@@ -0,0 +1,396 @@
+//! # OSTIMER Race Condition Test
+//!
+//! This example tests for race conditions in the OSTIMER driver by:
+//! - Scheduling alarms sequentially (hardware limitation: only one at a time)
+//! - Reading the counter during interrupt-heavy periods
+//! - Testing concurrent timer operations
+//! - Stress testing interrupt handling
+
+#![no_std]
+#![no_main]
+
+use core::sync::atomic::{AtomicU32, Ordering};
+
+use embassy_executor::Spawner;
+use embassy_time::{Duration, Timer};
+use hal::bind_interrupts;
+use {defmt_rtt as _, embassy_mcxa276 as hal, panic_probe as _};
+
+mod common;
+
+bind_interrupts!(struct Irqs {
+    OS_EVENT => hal::ostimer::time_driver::OsEventHandler;
+});
+
+#[used]
+#[no_mangle]
+static KEEP_OS_EVENT: unsafe extern "C" fn() = OS_EVENT;
+
+// Global counters for race condition detection
+static ALARM_CALLBACK_COUNT: AtomicU32 = AtomicU32::new(0);
+static INTERRUPT_COUNT: AtomicU32 = AtomicU32::new(0);
+static RACE_DETECTED: AtomicU32 = AtomicU32::new(0);
+
+// Alarm callback function
+fn alarm_callback() {
+    let _count = ALARM_CALLBACK_COUNT.fetch_add(1, Ordering::SeqCst);
+    INTERRUPT_COUNT.fetch_add(1, Ordering::SeqCst);
+
+    // Simulate some work in the callback to increase chance of races
+    for _ in 0..10 {
+        cortex_m::asm::nop();
+    }
+}
+
+fn report_default_handler(uart: &mut hal::uart::Uart<hal::uart::Lpuart2>) {
+    let snapshot = hal::interrupt::default_handler_snapshot();
+    if snapshot.count == 0 {
+        return;
+    }
+
+    uart.write_str_blocking("WARNING: DefaultHandler executed ");
+    write_u32(uart, snapshot.count);
+    uart.write_str_blocking(" time(s). Vector=");
+    write_u32(uart, snapshot.vector as u32);
+    uart.write_str_blocking(" CFSR=0x");
+    write_hex32(uart, snapshot.cfsr);
+    uart.write_str_blocking(" HFSR=0x");
+    write_hex32(uart, snapshot.hfsr);
+    uart.write_str_blocking(" PC=0x");
+    write_hex32(uart, snapshot.stacked_pc);
+    uart.write_str_blocking(" LR=0x");
+    write_hex32(uart, snapshot.stacked_lr);
+    uart.write_str_blocking(" SP=0x");
+    write_hex32(uart, snapshot.stacked_sp);
+    uart.write_str_blocking("\n");
+
+    hal::interrupt::clear_default_handler_snapshot();
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(Default::default());
+
+    // Enable/clock OSTIMER0 and UART2 before touching their registers
+    unsafe {
+        common::init_ostimer0(hal::pac());
+    }
+    unsafe {
+        common::init_uart2(hal::pac());
+    }
+    let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
+    let mut uart = hal::uart::Uart::<hal::uart::Lpuart2>::new(p.LPUART2, hal::uart::Config::new(src));
+
+    uart.write_str_blocking("OSTIMER Race Condition Test Starting...\n");
+
+    // The bind_interrupts! macro handles handler binding automatically
+
+    // Initialize the OSTIMER time driver FIRST
+    hal::ostimer::time_driver::init(
+        hal::interrupt::Priority::from(3),
+        1_000_000, // 1MHz clock
+    );
+
+    uart.write_str_blocking("Time driver initialized\n");
+
+    // Create OSTIMER instance
+    let ostimer = hal::ostimer::Ostimer::<hal::ostimer::Ostimer0>::new(
+        p.OSTIMER0,
+        hal::ostimer::Config {
+            init_match_max: true,
+            clock_frequency_hz: 1_000_000,
+        },
+        hal::pac(),
+    );
+
+    uart.write_str_blocking("OSTIMER instance created\n");
+
+    // Test 1: Sequential alarm scheduling (OSTIMER only supports one alarm at a time)
+    uart.write_str_blocking("Test 1: Sequential alarm scheduling...\n");
+    test_rapid_alarms(&ostimer, &mut uart).await;
+    report_default_handler(&mut uart);
+
+    // Test 2: Counter reading during interrupts
+    uart.write_str_blocking("Test 2: Counter reading during interrupts...\n");
+    test_counter_reading_during_interrupts(&ostimer, &mut uart).await;
+    report_default_handler(&mut uart);
+
+    // Test 3: Concurrent timer operations
+    uart.write_str_blocking("Test 3: Concurrent timer operations...\n");
+    test_concurrent_operations(&ostimer, &mut uart).await;
+    report_default_handler(&mut uart);
+
+    // Test 4: Timer reset during operation
+    uart.write_str_blocking("Test 4: Timer reset during operation...\n");
+    test_reset_during_operation(&ostimer, &mut uart, hal::pac()).await;
+    report_default_handler(&mut uart);
+
+    // Report results
+    uart.write_str_blocking("Race condition test complete\n");
+    uart.write_str_blocking("Callback count: ");
+    write_u32(&mut uart, ALARM_CALLBACK_COUNT.load(Ordering::SeqCst));
+    uart.write_str_blocking("\nInterrupt count: ");
+    write_u32(&mut uart, INTERRUPT_COUNT.load(Ordering::SeqCst));
+    uart.write_str_blocking("\nRaces detected: ");
+    write_u32(&mut uart, RACE_DETECTED.load(Ordering::SeqCst));
+    uart.write_str_blocking("\n");
+}
+
+// Test rapid alarm scheduling to stress interrupt handling
+async fn test_rapid_alarms(
+    ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>,
+    uart: &mut hal::uart::Uart<hal::uart::Lpuart2>,
+) {
+    let initial_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst);
+
+    // Schedule 10 alarms sequentially (OSTIMER only supports one alarm at a time)
+    for _i in 0..10 {
+        let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback);
+        let delay_us = 1000; // 1ms delay for each alarm
+        if ostimer.schedule_alarm_delay(&alarm, delay_us) {
+            // Wait for this alarm to complete before scheduling the next
+            Timer::after(Duration::from_micros(delay_us + 100)).await;
+            report_default_handler(uart);
+        } else {
+            RACE_DETECTED.fetch_add(1, Ordering::SeqCst);
+            uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm (match not ready)\n");
+        }
+    }
+
+    // All alarms should have completed by now
+    let final_count = ALARM_CALLBACK_COUNT.load(Ordering::SeqCst);
+    let expected_count = initial_count + 10;
+
+    if final_count != expected_count {
+        RACE_DETECTED.fetch_add(1, Ordering::SeqCst);
+        uart.write_str_blocking("ERROR: Expected ");
+        write_u32(uart, expected_count);
+        uart.write_str_blocking(" callbacks, got ");
+        write_u32(uart, final_count);
+        uart.write_str_blocking("\n");
+    } else {
+        uart.write_str_blocking("PASS: All rapid alarms executed\n");
+    }
+}
+
+// Test reading counter while interrupts are firing
+async fn test_counter_reading_during_interrupts(
+    ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>,
+    uart: &mut hal::uart::Uart<hal::uart::Lpuart2>,
+) {
+    let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst);
+
+    // Schedule an alarm that will fire soon
+    let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback);
+    if !ostimer.schedule_alarm_delay(&alarm, 500) {
+        RACE_DETECTED.fetch_add(1, Ordering::SeqCst);
+        uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before counter stress\n");
+    }
+
+    // While alarm is pending, read the counter many times rapidly
+    // This tests if counter reading is atomic and doesn't get corrupted by interrupts
+    let mut last_counter = ostimer.now();
+    let mut consistent_reads = 0;
+    let mut total_reads = 0;
+
+    for _ in 0..1000 {
+        let current_counter = ostimer.now();
+        total_reads += 1;
+
+        // Check if counter is monotonically increasing (basic sanity check)
+        if current_counter >= last_counter {
+            consistent_reads += 1;
+        }
+        last_counter = current_counter;
+
+        // Small delay between reads
+        for _ in 0..10 {
+            cortex_m::asm::nop();
+        }
+
+        report_default_handler(uart);
+    }
+
+    // Wait for alarm to complete
+    Timer::after(Duration::from_millis(1)).await;
+
+    let final_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst);
+
+    if consistent_reads == total_reads {
+        uart.write_str_blocking("PASS: Counter reading consistent during interrupts\n");
+    } else {
+        RACE_DETECTED.fetch_add(1, Ordering::SeqCst);
+        uart.write_str_blocking("ERROR: Counter reading inconsistent: ");
+        write_u32(uart, consistent_reads);
+        uart.write_str_blocking("/");
+        write_u32(uart, total_reads);
+        uart.write_str_blocking(" consistent\n");
+    }
+
+    if final_interrupt_count > initial_interrupt_count {
+        uart.write_str_blocking("PASS: Interrupt fired during counter reading test\n");
+    } else {
+        uart.write_str_blocking("WARNING: No interrupt fired during counter reading test\n");
+    }
+}
+
+// Test concurrent timer operations (embassy-time + alarms)
+async fn test_concurrent_operations(
+    ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>,
+    uart: &mut hal::uart::Uart<hal::uart::Lpuart2>,
+) {
+    let initial_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst);
+
+    // Start an embassy-time timer
+    let timer_future = Timer::after(Duration::from_millis(2));
+
+    // Schedule an alarm that should fire before the timer
+    let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback);
+    if !ostimer.schedule_alarm_delay(&alarm, 1000) {
+        RACE_DETECTED.fetch_add(1, Ordering::SeqCst);
+        uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before concurrent operations\n");
+    }
+
+    // Wait for both to complete
+    timer_future.await;
+
+    let final_interrupt_count = INTERRUPT_COUNT.load(Ordering::SeqCst);
+
+    if final_interrupt_count > initial_interrupt_count {
+        uart.write_str_blocking("PASS: Concurrent operations completed\n");
+    } else {
+        uart.write_str_blocking("WARNING: No interrupts during concurrent operations\n");
+    }
+}
+
+// Test timer reset during active operations
+async fn test_reset_during_operation(
+    ostimer: &hal::ostimer::Ostimer<'_, hal::ostimer::Ostimer0>,
+    uart: &mut hal::uart::Uart<hal::uart::Lpuart2>,
+    peripherals: &hal::pac::Peripherals,
+) {
+    let initial_counter = ostimer.now();
+
+    // Schedule an alarm
+    let alarm = hal::ostimer::Alarm::new().with_callback(alarm_callback);
+    if !ostimer.schedule_alarm_delay(&alarm, 2000) {
+        RACE_DETECTED.fetch_add(1, Ordering::SeqCst);
+        uart.write_str_blocking("ERROR: Failed to program OSTIMER alarm before reset test\n");
+    }
+
+    // Wait a bit then reset the timer
+    Timer::after(Duration::from_millis(1)).await;
+    ostimer.reset(peripherals);
+
+    // Check counter after reset
+    let counter_after_reset = ostimer.now();
+
+    // Wait to see if the alarm still fires (it shouldn't after reset)
+    Timer::after(Duration::from_millis(2)).await;
+
+    let final_counter = ostimer.now();
+
+    if counter_after_reset < initial_counter {
+        uart.write_str_blocking("PASS: Timer reset successful\n");
+    } else {
+        RACE_DETECTED.fetch_add(1, Ordering::SeqCst);
+        uart.write_str_blocking("ERROR: Timer reset may have failed\n");
+    }
+
+    uart.write_str_blocking("Counter progression after reset: ");
+    write_u64(uart, initial_counter);
+    uart.write_str_blocking(" -> ");
+    write_u64(uart, counter_after_reset);
+    uart.write_str_blocking(" -> ");
+    write_u64(uart, final_counter);
+    uart.write_str_blocking("\n");
+}
+
+// Helper function to write a u32 value as decimal string
+fn write_u32(uart: &mut hal::uart::Uart<hal::uart::Lpuart2>, value: u32) {
+    if value == 0 {
+        uart.write_str_blocking("0");
+        return;
+    }
+
+    let mut buffer = [0u8; 10]; // Enough for max u32
+    let mut i = 0;
+    let mut v = value;
+
+    while v > 0 {
+        buffer[i] = b'0' + (v % 10) as u8;
+        v /= 10;
+        i += 1;
+    }
+
+    // Write digits in reverse order
+    while i > 0 {
+        i -= 1;
+        match buffer[i] {
+            b'0' => uart.write_str_blocking("0"),
+            b'1' => uart.write_str_blocking("1"),
+            b'2' => uart.write_str_blocking("2"),
+            b'3' => uart.write_str_blocking("3"),
+            b'4' => uart.write_str_blocking("4"),
+            b'5' => uart.write_str_blocking("5"),
+            b'6' => uart.write_str_blocking("6"),
+            b'7' => uart.write_str_blocking("7"),
+            b'8' => uart.write_str_blocking("8"),
+            b'9' => uart.write_str_blocking("9"),
+            _ => uart.write_str_blocking("?"),
+        }
+    }
+}
+
+fn write_hex32(uart: &mut hal::uart::Uart<hal::uart::Lpuart2>, value: u32) {
+    let mut buf = [b'0'; 8];
+    let mut tmp = value;
+    for i in (0..8).rev() {
+        let digit = (tmp & 0xF) as u8;
+        buf[i] = match digit {
+            0..=9 => b'0' + digit,
+            10..=15 => b'A' + (digit - 10),
+            _ => b'?',
+        };
+        tmp >>= 4;
+    }
+    for b in &buf {
+        uart.write_byte(*b);
+    }
+}
+
+// Helper function to write a u64 value as decimal string
+fn write_u64(uart: &mut hal::uart::Uart<hal::uart::Lpuart2>, value: u64) {
+    if value == 0 {
+        uart.write_str_blocking("0");
+        return;
+    }
+
+    let mut buffer = [0u8; 20]; // Enough for max u64
+    let mut i = 0;
+    let mut v = value;
+
+    while v > 0 {
+        buffer[i] = b'0' + (v % 10) as u8;
+        v /= 10;
+        i += 1;
+    }
+
+    // Write digits in reverse order
+    while i > 0 {
+        i -= 1;
+        match buffer[i] {
+            b'0' => uart.write_str_blocking("0"),
+            b'1' => uart.write_str_blocking("1"),
+            b'2' => uart.write_str_blocking("2"),
+            b'3' => uart.write_str_blocking("3"),
+            b'4' => uart.write_str_blocking("4"),
+            b'5' => uart.write_str_blocking("5"),
+            b'6' => uart.write_str_blocking("6"),
+            b'7' => uart.write_str_blocking("7"),
+            b'8' => uart.write_str_blocking("8"),
+            b'9' => uart.write_str_blocking("9"),
+            _ => uart.write_str_blocking("?"),
+        }
+    }
+}
diff --git a/examples/rtc_alarm.rs b/examples/rtc_alarm.rs
new file mode 100644
index 000000000..c27fd4c55
--- /dev/null
+++ b/examples/rtc_alarm.rs
@@ -0,0 +1,87 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use hal::rtc::{RtcDateTime, RtcInterruptEnable};
+use hal::{uart, InterruptExt};
+use {cortex_m, embassy_mcxa276 as hal};
+
+mod common;
+
+type MyRtc = hal::rtc::Rtc<hal::rtc::Rtc0>;
+
+use embassy_mcxa276::bind_interrupts;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    RTC => hal::rtc::RtcHandler;
+});
+
+#[used]
+#[no_mangle]
+static KEEP_RTC: unsafe extern "C" fn() = RTC;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    unsafe {
+        common::init_uart2(hal::pac());
+    }
+
+    let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
+    let uart = uart::Uart::<uart::Lpuart2>::new(p.LPUART2, uart::Config::new(src));
+
+    uart.write_str_blocking("\r\n=== RTC Alarm Example ===\r\n");
+
+    unsafe { hal::clocks::init_fro16k(hal::pac()) };
+
+    let rtc_config = hal::rtc::get_default_config();
+
+    let rtc = MyRtc::new(p.RTC0, rtc_config);
+
+    let now = RtcDateTime {
+        year: 2025,
+        month: 10,
+        day: 15,
+        hour: 14,
+        minute: 30,
+        second: 0,
+    };
+
+    rtc.stop();
+
+    uart.write_str_blocking("Time set to: 2025-10-15 14:30:00\r\n");
+    rtc.set_datetime(now);
+
+    let mut alarm = now;
+    alarm.second += 10;
+
+    rtc.set_alarm(alarm);
+    uart.write_str_blocking("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)\r\n");
+
+    rtc.set_interrupt(RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE);
+
+    unsafe {
+        hal::interrupt::RTC.enable();
+    }
+
+    unsafe {
+        cortex_m::interrupt::enable();
+    }
+
+    rtc.start();
+
+    uart.write_str_blocking("RTC started, waiting for alarm...\r\n");
+
+    loop {
+        if rtc.is_alarm_triggered() {
+            uart.write_str_blocking("\r\n*** ALARM TRIGGERED! ***\r\n");
+            break;
+        }
+    }
+
+    uart.write_str_blocking("Example complete - Test PASSED!\r\n");
+
+    loop {}
+}
diff --git a/examples/uart_interrupt.rs b/examples/uart_interrupt.rs
new file mode 100644
index 000000000..bd734f859
--- /dev/null
+++ b/examples/uart_interrupt.rs
@@ -0,0 +1,69 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa276 as hal;
+use hal::interrupt::typelevel::Handler;
+use hal::uart;
+
+mod common;
+
+use embassy_mcxa276::bind_interrupts;
+use {defmt_rtt as _, panic_probe as _};
+
+// Bind LPUART2 interrupt to our handler
+bind_interrupts!(struct Irqs {
+    LPUART2 => hal::uart::UartInterruptHandler;
+});
+
+#[used]
+#[no_mangle]
+static KEEP_LPUART2: unsafe extern "C" fn() = LPUART2;
+
+// Wrapper function for the interrupt handler
+unsafe extern "C" fn lpuart2_handler() {
+    hal::uart::UartInterruptHandler::on_interrupt();
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let _p = hal::init(hal::config::Config::default());
+
+    // Enable/clock UART2 before touching its registers
+    unsafe {
+        common::init_uart2(hal::pac());
+    }
+    let src = unsafe { hal::clocks::uart2_src_hz(hal::pac()) };
+    let uart = uart::Uart::<uart::Lpuart2>::new(_p.LPUART2, uart::Config::new(src));
+
+    // Configure LPUART2 interrupt for UART operation BEFORE any UART usage
+    hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::from(3));
+
+    // Manually install the interrupt handler and enable RX IRQs in the peripheral
+    unsafe {
+        hal::interrupt::LPUART2.install_handler(lpuart2_handler);
+        // Enable RX interrupts so the handler actually fires on incoming bytes
+        uart.enable_rx_interrupts();
+    }
+
+    // Print welcome message
+    uart.write_str_blocking("UART interrupt echo demo starting...\r\n");
+    uart.write_str_blocking("Type characters to echo them back.\r\n");
+
+    // Log using defmt if enabled
+    defmt::info!("UART interrupt echo demo starting...");
+
+    loop {
+        // Check if we have received any data
+        if uart.rx_data_available() {
+            if let Some(byte) = uart.try_read_byte() {
+                // Echo it back
+                uart.write_byte(byte);
+                uart.write_str_blocking(" (received)\r\n");
+            }
+        } else {
+            // No data available, wait a bit before checking again
+            cortex_m::asm::delay(12_000_000); // ~1 second at 12MHz
+        }
+    }
+}
diff --git a/memory.x b/memory.x
new file mode 100644
index 000000000..b47534f18
--- /dev/null
+++ b/memory.x
@@ -0,0 +1,10 @@
+/* Memory layout for MCXA276 - RAM execution with cortex-m-rt */
+MEMORY
+{
+  /* FLASH and RAM overlap for RAM-execution experiments. */
+  FLASH : ORIGIN = 0x20000000, LENGTH = 128K
+  /* RAM overlaps FLASH */
+  RAM : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* Leave symbol and section boundary definitions to cortex-m-rt's link.x. */
diff --git a/ram.ld b/ram.ld
new file mode 100644
index 000000000..816ab6819
--- /dev/null
+++ b/ram.ld
@@ -0,0 +1,109 @@
+/* Simple RAM execution linker script for MCXA276 */
+MEMORY
+{
+  RAM : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* Pull in device default interrupt symbol aliases (e.g., CMC = DefaultHandler) */
+INCLUDE device.x
+
+
+/* Provide core exception weak aliases if not supplied by cortex-m-rt's link.x */
+PROVIDE(NonMaskableInt = DefaultHandler);
+PROVIDE(HardFault = DefaultHandler);
+PROVIDE(MemoryManagement = DefaultHandler);
+PROVIDE(BusFault = DefaultHandler);
+PROVIDE(UsageFault = DefaultHandler);
+PROVIDE(SecureFault = DefaultHandler);
+PROVIDE(SVCall = DefaultHandler);
+PROVIDE(DebugMonitor = DefaultHandler);
+PROVIDE(PendSV = DefaultHandler);
+PROVIDE(SysTick = DefaultHandler);
+
+/* In RAM-run we have no FLASH sidata; copy from sdata */
+__sidata = __sdata;
+
+/* Ensure the PAC interrupt table is kept */
+EXTERN(__INTERRUPTS);
+
+
+/* Pull in defmt's linker script to generate the defmt table that host decoders expect */
+INCLUDE defmt.x
+
+ENTRY(Reset)
+EXTERN(VECTOR_TABLE)
+EXTERN(Reset)
+EXTERN(main)
+
+/* Define _stack_start at end of RAM BEFORE it's used in vector table */
+_stack_start = ORIGIN(RAM) + LENGTH(RAM);
+
+SECTIONS
+{
+  .vector_table ORIGIN(RAM) :
+  {
+    /* Slot 0: Initial stack pointer - use our explicitly set _stack_start */
+    LONG(_stack_start);
+    /* Slot 1: Reset vector - address of Reset function with Thumb bit set */
+    LONG(Reset | 1);
+    /* Cortex-M33 core exceptions (slots 2-14) */
+    KEEP(*(.vector_table.exceptions));
+    /* Peripheral interrupt vectors provided by PAC (slots 16+) */
+    KEEP(*(.vector_table.interrupts));
+  } > RAM
+
+  .text :
+  {
+    KEEP(*(.text.Reset));
+    KEEP(*(.text.main));
+    *(.text .text.*);
+  } > RAM
+
+  /* Keep defmt table and fragments so host decoders can find metadata */
+  .defmt :
+  {
+    KEEP(*(.defmt));
+    KEEP(*(.defmt.*));
+  } > RAM
+
+  .rodata :
+  {
+    *(.rodata .rodata.*);
+  } > RAM
+
+  .data :
+  {
+    . = ALIGN(4);
+    __sdata = .;
+    *(.data .data.*);
+    . = ALIGN(4);
+    __edata = .;
+  } > RAM
+
+  /* Ensure RTT control block with "SEGGER RTT" signature is loaded to RAM */
+  .rtt :
+  {
+    KEEP(*(.rtt));
+  } > RAM
+
+  /* Place uninitialized buffers (like defmt-rtt) in RAM; load is fine for RAM-run */
+  .uninit :
+  {
+    *(.uninit .uninit.*);
+  } > RAM
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __sbss = .;
+    *(.bss .bss.*);
+    . = ALIGN(4);
+    __ebss = .;
+  } > RAM
+
+  /* Discard exception unwinding info */
+  /DISCARD/ :
+  {
+    *(.ARM.exidx .ARM.exidx.*);
+  }
+}
diff --git a/run.sh b/run.sh
new file mode 100644
index 000000000..418dc8a24
--- /dev/null
+++ b/run.sh
@@ -0,0 +1,93 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+ELF="${1:-}"
+if [[ -z "${ELF}" ]]; then
+  echo "Usage: $0 <elf_file>"
+  exit 1
+fi
+if [[ ! -f "${ELF}" ]]; then
+  echo "ELF not found: ${ELF}"
+  exit 1
+fi
+
+# Configurable via env
+CHIP="${CHIP:-MCXA276}"
+SPEED="${PROBE_SPEED:-1000}"   # kHz
+# Default to J-Link if PROBE not provided
+PROBE_OPT=(--probe "${PROBE:-1366:0101:000600110607}")
+PORT="${PROBE_RS_GDB_PORT:-1337}"
+
+cleanup() {
+  if [[ -n "${GDB_SERVER_PID:-}" ]]; then kill "${GDB_SERVER_PID}" 2>/dev/null || true; fi
+  [[ -n "${GDB_SCRIPT:-}" ]] && rm -f "${GDB_SCRIPT}" || true
+  [[ -n "${SERVER_LOG:-}" ]] && rm -f "${SERVER_LOG}" || true
+}
+trap cleanup EXIT
+
+if ! command -v probe-rs >/dev/null 2>&1; then
+  echo "probe-rs not found (cargo install probe-rs --features cli)"
+  exit 1
+fi
+if ! command -v gdb-multiarch >/dev/null 2>&1; then
+  echo "gdb-multiarch not found; install it (e.g., sudo apt install gdb-multiarch)."
+  exit 1
+fi
+
+# Start probe-rs GDB server and capture its output to a log (do not hide errors)
+SERVER_LOG=$(mktemp)
+set +e
+probe-rs gdb --chip "${CHIP}" --protocol swd --speed "${SPEED}" --non-interactive "${ELF}" "${PROBE_OPT[@]}" \
+  >"${SERVER_LOG}" 2>&1 &
+GDB_SERVER_PID=$!
+set -e
+
+# Wait for server readiness without touching the TCP port to avoid corrupting the GDB protocol
+ready=""
+for _ in {1..50}; do
+  if grep -q "Firing up GDB stub" "${SERVER_LOG}"; then ready=1; break; fi
+  if grep -q "Connecting to the chip was unsuccessful" "${SERVER_LOG}"; then
+    echo "probe-rs gdb server failed to connect to target. Log:" >&2
+    echo "----- probe-rs gdb log -----" >&2
+    sed -e 's/^/  /' "${SERVER_LOG}" >&2 || true
+    exit 1
+  fi
+  sleep 0.1
+done
+if [[ -z "${ready}" ]]; then
+  echo "probe-rs gdb server did not report readiness. Log:" >&2
+  echo "----- probe-rs gdb log -----" >&2
+  sed -e 's/^/  /' "${SERVER_LOG}" >&2 || true
+  exit 1
+fi
+
+# GDB script: load to RAM and run, no reset
+GDB_SCRIPT=$(mktemp)
+cat >"${GDB_SCRIPT}" <<EOF
+set pagination off
+set confirm off
+set mem inaccessible-by-default off
+
+# Connect and load without reset
+target remote :${PORT}
+monitor halt
+load
+# Set VTOR to point to our RAM vector table at 0x20000000
+# This ensures the CPU uses the correct initial SP and Reset vector
+set *0xE000ED08 = 0x20000000
+# Now read SP and PC from our vector table and set them
+set \$sp = *(unsigned int*)0x20000000
+set \$pc = *(unsigned int*)0x20000004
+# Run target (blocks here until you Ctrl+C, like before)
+continue
+EOF
+
+# Run gdb against the server
+if ! gdb-multiarch -q -batch -x "${GDB_SCRIPT}" "${ELF}"; then
+  echo "GDB failed to load/run. probe-rs gdb server log:" >&2
+  echo "----- probe-rs gdb log -----" >&2
+  sed -e 's/^/  /' "${SERVER_LOG}" >&2 || true
+  exit 1
+fi
+
+echo "Program loaded and started (no reset)"
diff --git a/rust-toolchain.toml b/rust-toolchain.toml
deleted file mode 100644
index 367cc1fc3..000000000
--- a/rust-toolchain.toml
+++ /dev/null
@@ -1,2 +0,0 @@
-[toolchain]
-components = ["rustfmt", "clippy"]
diff --git a/rustfmt.toml b/rustfmt.toml
index 753065179..9eb3c3b4f 100644
--- a/rustfmt.toml
+++ b/rustfmt.toml
@@ -1 +1,3 @@
+group_imports = "StdExternalCrate"
+imports_granularity = "Module"
 max_width = 120
diff --git a/src/adc.rs b/src/adc.rs
new file mode 100644
index 000000000..d456971f7
--- /dev/null
+++ b/src/adc.rs
@@ -0,0 +1,388 @@
+//! ADC driver
+use core::sync::atomic::{AtomicBool, Ordering};
+
+use crate::pac;
+use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres};
+use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts};
+use crate::pac::adc1::cmdl1::{Adch, Ctype, Mode};
+use crate::pac::adc1::ctrl::CalAvgs;
+use crate::pac::adc1::tctrl::{Tcmd, Tpri};
+
+type Regs = pac::adc1::RegisterBlock;
+
+static INTERRUPT_TRIGGERED: AtomicBool = AtomicBool::new(false);
+// Token-based instance pattern like embassy-imxrt
+pub trait Instance {
+    fn ptr() -> *const Regs;
+}
+
+/// Token for ADC1
+pub type Adc1 = crate::peripherals::ADC1;
+impl Instance for crate::peripherals::ADC1 {
+    #[inline(always)]
+    fn ptr() -> *const Regs {
+        pac::Adc1::ptr()
+    }
+}
+
+// Also implement Instance for the Peri wrapper type
+impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::ADC1> {
+    #[inline(always)]
+    fn ptr() -> *const Regs {
+        pac::Adc1::ptr()
+    }
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u8)]
+pub enum TriggerPriorityPolicy {
+    ConvPreemptImmediatelyNotAutoResumed = 0,
+    ConvPreemptSoftlyNotAutoResumed = 1,
+    ConvPreemptImmediatelyAutoRestarted = 4,
+    ConvPreemptSoftlyAutoRestarted = 5,
+    ConvPreemptImmediatelyAutoResumed = 12,
+    ConvPreemptSoftlyAutoResumed = 13,
+    ConvPreemptSubsequentlyNotAutoResumed = 2,
+    ConvPreemptSubsequentlyAutoRestarted = 6,
+    ConvPreemptSubsequentlyAutoResumed = 14,
+    TriggerPriorityExceptionDisabled = 16,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct LpadcConfig {
+    pub enable_in_doze_mode: bool,
+    pub conversion_average_mode: CalAvgs,
+    pub enable_analog_preliminary: bool,
+    pub power_up_delay: u8,
+    pub reference_voltage_source: Refsel,
+    pub power_level_mode: Pwrsel,
+    pub trigger_priority_policy: TriggerPriorityPolicy,
+    pub enable_conv_pause: bool,
+    pub conv_pause_delay: u16,
+    pub fifo_watermark: u8,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct ConvCommandConfig {
+    pub sample_channel_mode: Ctype,
+    pub channel_number: Adch,
+    pub chained_next_command_number: Next,
+    pub enable_auto_channel_increment: bool,
+    pub loop_count: u8,
+    pub hardware_average_mode: Avgs,
+    pub sample_time_mode: Sts,
+    pub hardware_compare_mode: Cmpen,
+    pub hardware_compare_value_high: u32,
+    pub hardware_compare_value_low: u32,
+    pub conversion_resolution_mode: Mode,
+    pub enable_wait_trigger: bool,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct ConvTriggerConfig {
+    pub target_command_id: Tcmd,
+    pub delay_power: u8,
+    pub priority: Tpri,
+    pub enable_hardware_trigger: bool,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct ConvResult {
+    pub command_id_source: u32,
+    pub loop_count_index: u32,
+    pub trigger_id_source: u32,
+    pub conv_value: u16,
+}
+
+pub struct Adc<I: Instance> {
+    _inst: core::marker::PhantomData<I>,
+}
+
+impl<I: Instance> Adc<I> {
+    /// initialize ADC
+    pub fn new(_inst: impl Instance, config: LpadcConfig) -> Self {
+        let adc = unsafe { &*I::ptr() };
+
+        /* Reset the module. */
+        adc.ctrl().modify(|_, w| w.rst().held_in_reset());
+        adc.ctrl().modify(|_, w| w.rst().released_from_reset());
+
+        adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset());
+
+        /* Disable the module before setting configuration. */
+        adc.ctrl().modify(|_, w| w.adcen().disabled());
+
+        /* Configure the module generally. */
+        if config.enable_in_doze_mode {
+            adc.ctrl().modify(|_, w| w.dozen().enabled());
+        } else {
+            adc.ctrl().modify(|_, w| w.dozen().disabled());
+        }
+
+        /* Set calibration average mode. */
+        adc.ctrl()
+            .modify(|_, w| w.cal_avgs().variant(config.conversion_average_mode));
+
+        adc.cfg().write(|w| unsafe {
+            let w = if config.enable_analog_preliminary {
+                w.pwren().pre_enabled()
+            } else {
+                w
+            };
+
+            w.pudly()
+                .bits(config.power_up_delay)
+                .refsel()
+                .variant(config.reference_voltage_source)
+                .pwrsel()
+                .variant(config.power_level_mode)
+                .tprictrl()
+                .variant(match config.trigger_priority_policy {
+                    TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted
+                    | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => Tprictrl::FinishCurrentOnPriority,
+                    TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted
+                    | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tprictrl::FinishSequenceOnPriority,
+                    _ => Tprictrl::AbortCurrentOnPriority,
+                })
+                .tres()
+                .variant(match config.trigger_priority_policy {
+                    TriggerPriorityPolicy::ConvPreemptImmediatelyAutoRestarted
+                    | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted
+                    | TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted
+                    | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tres::Enabled,
+                    _ => Tres::Disabled,
+                })
+                .tcmdres()
+                .variant(match config.trigger_priority_policy {
+                    TriggerPriorityPolicy::ConvPreemptImmediatelyAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed
+                    | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed
+                    | TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => Tcmdres::Enabled,
+                    _ => Tcmdres::Disabled,
+                })
+                .hpt_exdi()
+                .variant(match config.trigger_priority_policy {
+                    TriggerPriorityPolicy::TriggerPriorityExceptionDisabled => HptExdi::Disabled,
+                    _ => HptExdi::Enabled,
+                })
+        });
+
+        if config.enable_conv_pause {
+            adc.pause()
+                .modify(|_, w| unsafe { w.pauseen().enabled().pausedly().bits(config.conv_pause_delay) });
+        } else {
+            adc.pause().write(|w| unsafe { w.bits(0) });
+        }
+
+        adc.fctrl0()
+            .write(|w| unsafe { w.fwmark().bits(config.fifo_watermark) });
+
+        // Enable ADC
+        adc.ctrl().modify(|_, w| w.adcen().enabled());
+
+        Self {
+            _inst: core::marker::PhantomData,
+        }
+    }
+
+    pub fn deinit(&self) {
+        let adc = unsafe { &*I::ptr() };
+        adc.ctrl().modify(|_, w| w.adcen().disabled());
+    }
+
+    pub fn get_default_config() -> LpadcConfig {
+        LpadcConfig {
+            enable_in_doze_mode: true,
+            conversion_average_mode: CalAvgs::NoAverage,
+            enable_analog_preliminary: false,
+            power_up_delay: 0x80,
+            reference_voltage_source: Refsel::Option1,
+            power_level_mode: Pwrsel::Lowest,
+            trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
+            enable_conv_pause: false,
+            conv_pause_delay: 0,
+            fifo_watermark: 0,
+        }
+    }
+
+    pub fn do_offset_calibration(&self) {
+        let adc = unsafe { &*I::ptr() };
+        // Enable calibration mode
+        adc.ctrl()
+            .modify(|_, w| w.calofs().offset_calibration_request_pending());
+
+        // Wait for calibration to complete (polling status register)
+        while adc.stat().read().cal_rdy().is_not_set() {}
+    }
+
+    pub fn get_gain_conv_result(&self, mut gain_adjustment: f32) -> u32 {
+        let mut gcra_array = [0u32; 17];
+        let mut gcalr: u32 = 0;
+
+        for i in (1..=17).rev() {
+            let shift = 16 - (i - 1);
+            let step = 1.0 / (1u32 << shift) as f32;
+            let tmp = (gain_adjustment / step) as u32;
+            gcra_array[i - 1] = tmp;
+            gain_adjustment = gain_adjustment - tmp as f32 * step;
+        }
+
+        for i in (1..=17).rev() {
+            gcalr += gcra_array[i - 1] << (i - 1);
+        }
+        gcalr
+    }
+
+    pub fn do_auto_calibration(&self) {
+        let adc = unsafe { &*I::ptr() };
+        adc.ctrl().modify(|_, w| w.cal_req().calibration_request_pending());
+
+        while adc.gcc0().read().rdy().is_gain_cal_not_valid() {}
+
+        let mut gcca = adc.gcc0().read().gain_cal().bits() as u32;
+        if gcca & (((0xFFFF >> 0) + 1) >> 1) != 0 {
+            gcca |= !0xFFFF;
+        }
+
+        let gcra = 131072.0 / (131072.0 - gcca as f32);
+
+        // Write to GCR0
+        adc.gcr0().write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) });
+
+        adc.gcr0().modify(|_, w| w.rdy().set_bit());
+
+        // Wait for calibration to complete (polling status register)
+        while adc.stat().read().cal_rdy().is_not_set() {}
+    }
+
+    pub fn do_software_trigger(&self, trigger_id_mask: u32) {
+        let adc = unsafe { &*I::ptr() };
+        adc.swtrig().write(|w| unsafe { w.bits(trigger_id_mask) });
+    }
+
+    pub fn get_default_conv_command_config(&self) -> ConvCommandConfig {
+        ConvCommandConfig {
+            sample_channel_mode: Ctype::SingleEndedASideChannel,
+            channel_number: Adch::SelectCh0,
+            chained_next_command_number: Next::NoNextCmdTerminateOnFinish,
+            enable_auto_channel_increment: false,
+            loop_count: 0,
+            hardware_average_mode: Avgs::NoAverage,
+            sample_time_mode: Sts::Sample3p5,
+            hardware_compare_mode: Cmpen::DisabledAlwaysStoreResult,
+            hardware_compare_value_high: 0,
+            hardware_compare_value_low: 0,
+            conversion_resolution_mode: Mode::Data12Bits,
+            enable_wait_trigger: false,
+        }
+    }
+
+    //TBD Need to add cmdlx and cmdhx with x {2..7}
+    pub fn set_conv_command_config(&self, index: u32, config: &ConvCommandConfig) {
+        let adc = unsafe { &*I::ptr() };
+
+        match index {
+            1 => {
+                adc.cmdl1().write(|w| {
+                    w.adch()
+                        .variant(config.channel_number)
+                        .mode()
+                        .variant(config.conversion_resolution_mode)
+                });
+                adc.cmdh1().write(|w| unsafe {
+                    w.next()
+                        .variant(config.chained_next_command_number)
+                        .loop_()
+                        .bits(config.loop_count)
+                        .avgs()
+                        .variant(config.hardware_average_mode)
+                        .sts()
+                        .variant(config.sample_time_mode)
+                        .cmpen()
+                        .variant(config.hardware_compare_mode);
+                    if config.enable_wait_trigger {
+                        w.wait_trig().enabled();
+                    }
+                    if config.enable_auto_channel_increment {
+                        w.lwi().enabled();
+                    }
+                    w
+                });
+            }
+            _ => panic!("Invalid command index: must be between 1 and 7"),
+        }
+    }
+
+    pub fn get_default_conv_trigger_config(&self) -> ConvTriggerConfig {
+        ConvTriggerConfig {
+            target_command_id: Tcmd::NotValid,
+            delay_power: 0,
+            priority: Tpri::HighestPriority,
+            enable_hardware_trigger: false,
+        }
+    }
+
+    pub fn set_conv_trigger_config(&self, trigger_id: usize, config: &ConvTriggerConfig) {
+        let adc = unsafe { &*I::ptr() };
+        let tctrl = &adc.tctrl(trigger_id);
+
+        tctrl.write(|w| unsafe {
+            let w = w.tcmd().variant(config.target_command_id);
+            let w = w.tdly().bits(config.delay_power);
+            w.tpri().variant(config.priority);
+            if config.enable_hardware_trigger {
+                w.hten().enabled()
+            } else {
+                w
+            }
+        });
+    }
+
+    pub fn do_reset_fifo(&self) {
+        let adc = unsafe { &*I::ptr() };
+        adc.ctrl().modify(|_, w| w.rstfifo0().trigger_reset());
+    }
+
+    pub fn enable_interrupt(&self, mask: u32) {
+        let adc = unsafe { &*I::ptr() };
+        adc.ie().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
+        INTERRUPT_TRIGGERED.store(false, Ordering::SeqCst);
+    }
+
+    pub fn is_interrupt_triggered(&self) -> bool {
+        INTERRUPT_TRIGGERED.load(Ordering::Relaxed)
+    }
+}
+
+pub fn get_conv_result() -> Option<ConvResult> {
+    let adc = unsafe { &*pac::Adc1::ptr() };
+    let fifo = adc.resfifo0().read().bits();
+    const VALID_MASK: u32 = 1 << 31;
+    if fifo & VALID_MASK == 0 {
+        return None;
+    }
+
+    Some(ConvResult {
+        command_id_source: (fifo >> 24) & 0x0F,
+        loop_count_index: (fifo >> 20) & 0x0F,
+        trigger_id_source: (fifo >> 16) & 0x0F,
+        conv_value: (fifo & 0xFFFF) as u16,
+    })
+}
+
+pub fn on_interrupt() {
+    if get_conv_result().is_some() {
+        INTERRUPT_TRIGGERED.store(true, Ordering::SeqCst);
+    }
+}
+
+pub struct AdcHandler;
+impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::ADC1> for AdcHandler {
+    unsafe fn on_interrupt() {
+        on_interrupt();
+    }
+}
diff --git a/src/baremetal/mod.rs b/src/baremetal/mod.rs
deleted file mode 100644
index c03b9538b..000000000
--- a/src/baremetal/mod.rs
+++ /dev/null
@@ -1,6 +0,0 @@
-use core::panic::PanicInfo;
-
-#[panic_handler]
-fn panic(_info: &PanicInfo) -> ! {
-    loop {}
-}
diff --git a/src/board.rs b/src/board.rs
new file mode 100644
index 000000000..fa679e82c
--- /dev/null
+++ b/src/board.rs
@@ -0,0 +1,14 @@
+use crate::{clocks, pac, pins};
+
+/// Initialize clocks and pin muxing for UART2 debug console.
+pub unsafe fn init_uart2(p: &pac::Peripherals) {
+    clocks::ensure_frolf_running(p);
+    clocks::enable_uart2_port2(p);
+    pins::configure_uart2_pins_port2();
+    clocks::select_uart2_clock(p);
+}
+
+/// Initialize clocks for the LED GPIO/PORT used by the blink example.
+pub unsafe fn init_led(p: &pac::Peripherals) {
+    clocks::enable_led_port(p);
+}
diff --git a/src/clocks.rs b/src/clocks.rs
new file mode 100644
index 000000000..65a17cef6
--- /dev/null
+++ b/src/clocks.rs
@@ -0,0 +1,134 @@
+//! Clock control helpers (no magic numbers, PAC field access only).
+//! Provides reusable gate abstractions for peripherals used by the examples.
+use crate::pac;
+
+/// Trait describing an AHB clock gate that can be toggled through MRCC.
+pub trait Gate {
+    /// Enable the clock gate.
+    unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock);
+
+    /// Return whether the clock gate is currently enabled.
+    fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool;
+}
+
+/// Enable a clock gate for the given peripheral set.
+#[inline]
+pub unsafe fn enable<G: Gate>(peripherals: &pac::Peripherals) {
+    let mrcc = &peripherals.mrcc0;
+    G::enable(mrcc);
+    while !G::is_enabled(mrcc) {}
+    core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags));
+}
+
+/// Check whether a gate is currently enabled.
+#[inline]
+pub fn is_enabled<G: Gate>(peripherals: &pac::Peripherals) -> bool {
+    G::is_enabled(&peripherals.mrcc0)
+}
+
+macro_rules! impl_cc_gate {
+    ($name:ident, $reg:ident, $field:ident) => {
+        pub struct $name;
+
+        impl Gate for $name {
+            #[inline]
+            unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock) {
+                mrcc.$reg().modify(|_, w| w.$field().enabled());
+            }
+
+            #[inline]
+            fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool {
+                mrcc.$reg().read().$field().is_enabled()
+            }
+        }
+    };
+}
+
+pub mod gate {
+    use super::*;
+
+    impl_cc_gate!(Port2, mrcc_glb_cc1, port2);
+    impl_cc_gate!(Port3, mrcc_glb_cc1, port3);
+    impl_cc_gate!(Ostimer0, mrcc_glb_cc1, ostimer0);
+    impl_cc_gate!(Lpuart2, mrcc_glb_cc0, lpuart2);
+    impl_cc_gate!(Gpio3, mrcc_glb_cc2, gpio3);
+    impl_cc_gate!(Port1, mrcc_glb_cc1, port1);
+    impl_cc_gate!(Adc1, mrcc_glb_cc1, adc1);
+}
+
+/// Convenience helper enabling the PORT2 and LPUART2 gates required for the debug UART.
+pub unsafe fn enable_uart2_port2(peripherals: &pac::Peripherals) {
+    enable::<gate::Port2>(peripherals);
+    enable::<gate::Lpuart2>(peripherals);
+}
+
+/// Convenience helper enabling the PORT3 and GPIO3 gates used by the LED in the examples.
+pub unsafe fn enable_led_port(peripherals: &pac::Peripherals) {
+    enable::<gate::Port3>(peripherals);
+    enable::<gate::Gpio3>(peripherals);
+}
+
+/// Convenience helper enabling the OSTIMER0 clock gate.
+pub unsafe fn enable_ostimer0(peripherals: &pac::Peripherals) {
+    enable::<gate::Ostimer0>(peripherals);
+}
+
+pub unsafe fn select_uart2_clock(peripherals: &pac::Peripherals) {
+    // Use FRO_LF_DIV (already running) MUX=0 DIV=0
+    let mrcc = &peripherals.mrcc0;
+    mrcc.mrcc_lpuart2_clksel().write(|w| w.mux().clkroot_func_0());
+    mrcc.mrcc_lpuart2_clkdiv().write(|w| unsafe { w.bits(0) });
+}
+
+pub unsafe fn ensure_frolf_running(peripherals: &pac::Peripherals) {
+    // Ensure FRO_LF divider clock is running (reset default HALT=1 stops it)
+    let sys = &peripherals.syscon;
+    sys.frolfdiv().modify(|_, w| {
+        // DIV defaults to 0; keep it explicit and clear HALT
+        unsafe { w.div().bits(0) }.halt().run()
+    });
+}
+
+/// Compute the FRO_LF_DIV output frequency currently selected for LPUART2.
+/// Assumes select_uart2_clock() has chosen MUX=0 (FRO_LF_DIV) and DIV is set in SYSCON.FRO_LF_DIV.
+pub unsafe fn uart2_src_hz(peripherals: &pac::Peripherals) -> u32 {
+    // SYSCON.FRO_LF_DIV: DIV field is simple divider: freq_out = 12_000_000 / (DIV+1) for many NXP parts.
+    // On MCXA276 FRO_LF base is 12 MHz; our init keeps DIV=0, so result=12_000_000.
+    // Read it anyway for future generality.
+    let div = peripherals.syscon.frolfdiv().read().div().bits() as u32;
+    let base = 12_000_000u32;
+    base / (div + 1)
+}
+
+/// Enable clock gate and release reset for OSTIMER0.
+/// Select OSTIMER0 clock source = 1 MHz root (working bring-up configuration).
+pub unsafe fn select_ostimer0_clock_1m(peripherals: &pac::Peripherals) {
+    let mrcc = &peripherals.mrcc0;
+    mrcc.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m());
+}
+
+pub unsafe fn init_fro16k(peripherals: &pac::Peripherals) {
+    let vbat = &peripherals.vbat0;
+    // Enable FRO16K oscillator
+    vbat.froctla().modify(|_, w| w.fro_en().set_bit());
+
+    // Lock the control register
+    vbat.frolcka().modify(|_, w| w.lock().set_bit());
+
+    // Enable clock outputs to both VSYS and VDD_CORE domains
+    // Bit 0: clk_16k0 to VSYS domain
+    // Bit 1: clk_16k1 to VDD_CORE domain
+    vbat.froclke().modify(|_, w| unsafe { w.clke().bits(0x3) });
+}
+
+pub unsafe fn enable_adc(peripherals: &pac::Peripherals) {
+    enable::<gate::Port1>(peripherals);
+    enable::<gate::Adc1>(peripherals);
+}
+
+pub unsafe fn select_adc_clock(peripherals: &pac::Peripherals) {
+    // Use FRO_LF_DIV (already running) MUX=0 DIV=0
+    let mrcc = &peripherals.mrcc0;
+    mrcc.mrcc_adc_clksel().write(|w| w.mux().clkroot_func_0());
+    mrcc.mrcc_adc_clkdiv().write(|w| unsafe { w.bits(0) });
+}
diff --git a/src/config.rs b/src/config.rs
new file mode 100644
index 000000000..93aed5a99
--- /dev/null
+++ b/src/config.rs
@@ -0,0 +1,20 @@
+// HAL configuration (minimal), mirroring embassy-imxrt style
+
+use crate::interrupt::Priority;
+
+#[non_exhaustive]
+pub struct Config {
+    pub time_interrupt_priority: Priority,
+    pub rtc_interrupt_priority: Priority,
+    pub adc_interrupt_priority: Priority,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            time_interrupt_priority: Priority::from(0),
+            rtc_interrupt_priority: Priority::from(0),
+            adc_interrupt_priority: Priority::from(0),
+        }
+    }
+}
diff --git a/src/gpio.rs b/src/gpio.rs
new file mode 100644
index 000000000..1e7214b28
--- /dev/null
+++ b/src/gpio.rs
@@ -0,0 +1,244 @@
+//! GPIO driver built around a type-erased `Flex` pin, similar to other Embassy HALs.
+//! The exported `Output`/`Input` drivers own a `Flex` so they no longer depend on the
+//! concrete pin type.
+
+use core::marker::PhantomData;
+
+use crate::{pac, pins as pin_config};
+
+/// Logical level for GPIO pins.
+#[derive(Copy, Clone, Eq, PartialEq, Debug)]
+pub enum Level {
+    Low,
+    High,
+}
+
+pub type Gpio = crate::peripherals::GPIO;
+
+/// Type-erased representation of a GPIO pin.
+#[derive(Copy, Clone)]
+pub struct AnyPin {
+    port: u8,
+    pin: u8,
+    gpio: *const pac::gpio0::RegisterBlock,
+}
+
+impl AnyPin {
+    /// Create an `AnyPin` from raw components.
+    pub fn new(port: u8, pin: u8, gpio: *const pac::gpio0::RegisterBlock) -> Self {
+        Self { port, pin, gpio }
+    }
+
+    #[inline(always)]
+    fn mask(&self) -> u32 {
+        1u32 << self.pin
+    }
+
+    #[inline(always)]
+    fn gpio(&self) -> &'static pac::gpio0::RegisterBlock {
+        unsafe { &*self.gpio }
+    }
+
+    #[inline(always)]
+    pub fn port_index(&self) -> u8 {
+        self.port
+    }
+
+    #[inline(always)]
+    pub fn pin_index(&self) -> u8 {
+        self.pin
+    }
+}
+
+/// Type-level trait implemented by concrete pin ZSTs.
+pub trait PinId {
+    fn port_index() -> u8;
+    fn pin_index() -> u8;
+    fn gpio_ptr() -> *const pac::gpio0::RegisterBlock;
+
+    fn set_mux_gpio() {
+        unsafe { pin_config::set_pin_mux_gpio(Self::port_index(), Self::pin_index()) }
+    }
+
+    fn degrade() -> AnyPin {
+        AnyPin::new(Self::port_index(), Self::pin_index(), Self::gpio_ptr())
+    }
+}
+
+pub mod pins {
+    use super::{pac, AnyPin, PinId};
+
+    macro_rules! define_pin {
+        ($Name:ident, $port:literal, $pin:literal, $GpioBlk:ident) => {
+            pub struct $Name;
+            impl super::PinId for $Name {
+                #[inline(always)]
+                fn port_index() -> u8 {
+                    $port
+                }
+                #[inline(always)]
+                fn pin_index() -> u8 {
+                    $pin
+                }
+                #[inline(always)]
+                fn gpio_ptr() -> *const pac::gpio0::RegisterBlock {
+                    pac::$GpioBlk::ptr()
+                }
+            }
+
+            impl $Name {
+                /// Convenience helper to obtain a type-erased handle to this pin.
+                pub fn degrade() -> AnyPin {
+                    <Self as PinId>::degrade()
+                }
+
+                pub fn set_mux_gpio() {
+                    <Self as PinId>::set_mux_gpio()
+                }
+            }
+        };
+    }
+
+    // Extend this list as more pins are needed.
+    define_pin!(PIO3_18, 3, 18, Gpio3);
+}
+
+/// A flexible pin that can be configured as input or output.
+pub struct Flex<'d> {
+    pin: AnyPin,
+    _marker: PhantomData<&'d mut ()>,
+}
+
+impl<'d> Flex<'d> {
+    pub fn new(pin: AnyPin) -> Self {
+        Self {
+            pin,
+            _marker: PhantomData,
+        }
+    }
+
+    #[inline(always)]
+    fn gpio(&self) -> &'static pac::gpio0::RegisterBlock {
+        self.pin.gpio()
+    }
+
+    #[inline(always)]
+    fn mask(&self) -> u32 {
+        self.pin.mask()
+    }
+
+    pub fn set_as_input(&mut self) {
+        let mask = self.mask();
+        let gpio = self.gpio();
+        gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() & !mask) });
+    }
+
+    pub fn set_as_output(&mut self) {
+        let mask = self.mask();
+        let gpio = self.gpio();
+        gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
+    }
+
+    pub fn set_high(&mut self) {
+        self.gpio().psor().write(|w| unsafe { w.bits(self.mask()) });
+    }
+
+    pub fn set_low(&mut self) {
+        self.gpio().pcor().write(|w| unsafe { w.bits(self.mask()) });
+    }
+
+    pub fn set_level(&mut self, level: Level) {
+        match level {
+            Level::High => self.set_high(),
+            Level::Low => self.set_low(),
+        }
+    }
+
+    pub fn toggle(&mut self) {
+        self.gpio().ptor().write(|w| unsafe { w.bits(self.mask()) });
+    }
+
+    pub fn is_high(&self) -> bool {
+        (self.gpio().pdir().read().bits() & self.mask()) != 0
+    }
+
+    pub fn is_low(&self) -> bool {
+        !self.is_high()
+    }
+}
+
+/// GPIO output driver that owns a `Flex` pin.
+pub struct Output<'d> {
+    flex: Flex<'d>,
+}
+
+impl<'d> Output<'d> {
+    pub fn new(pin: AnyPin, initial: Level) -> Self {
+        let mut flex = Flex::new(pin);
+        flex.set_level(initial);
+        flex.set_as_output();
+        Self { flex }
+    }
+
+    #[inline]
+    pub fn set_high(&mut self) {
+        self.flex.set_high();
+    }
+
+    #[inline]
+    pub fn set_low(&mut self) {
+        self.flex.set_low();
+    }
+
+    #[inline]
+    pub fn set_level(&mut self, level: Level) {
+        self.flex.set_level(level);
+    }
+
+    #[inline]
+    pub fn toggle(&mut self) {
+        self.flex.toggle();
+    }
+
+    #[inline]
+    pub fn is_set_high(&self) -> bool {
+        self.flex.is_high()
+    }
+
+    #[inline]
+    pub fn is_set_low(&self) -> bool {
+        !self.is_set_high()
+    }
+
+    /// Expose the inner `Flex` if callers need to reconfigure the pin.
+    pub fn into_flex(self) -> Flex<'d> {
+        self.flex
+    }
+}
+
+/// GPIO input driver that owns a `Flex` pin.
+pub struct Input<'d> {
+    flex: Flex<'d>,
+}
+
+impl<'d> Input<'d> {
+    pub fn new(pin: AnyPin) -> Self {
+        let mut flex = Flex::new(pin);
+        flex.set_as_input();
+        Self { flex }
+    }
+
+    #[inline]
+    pub fn is_high(&self) -> bool {
+        self.flex.is_high()
+    }
+
+    #[inline]
+    pub fn is_low(&self) -> bool {
+        self.flex.is_low()
+    }
+
+    pub fn into_flex(self) -> Flex<'d> {
+        self.flex
+    }
+}
diff --git a/src/interrupt.rs b/src/interrupt.rs
new file mode 100644
index 000000000..09d7acbef
--- /dev/null
+++ b/src/interrupt.rs
@@ -0,0 +1,349 @@
+//! Minimal interrupt helpers mirroring embassy-imxrt style for OS_EVENT and LPUART2.
+//! Type-level interrupt traits and bindings are provided by the
+//! `embassy_hal_internal::interrupt_mod!` macro via the generated module below.
+
+mod generated {
+    embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1);
+}
+
+use core::sync::atomic::{AtomicU16, AtomicU32, Ordering};
+
+pub use generated::interrupt::{typelevel, Priority};
+
+use crate::pac::Interrupt;
+
+/// Trait for configuring and controlling interrupts.
+///
+/// This trait provides a consistent interface for interrupt management across
+/// different interrupt sources, similar to embassy-imxrt's InterruptExt.
+pub trait InterruptExt {
+    /// Clear any pending interrupt in NVIC.
+    fn unpend(&self);
+
+    /// Set NVIC priority for this interrupt.
+    fn set_priority(&self, priority: Priority);
+
+    /// Enable this interrupt in NVIC.
+    ///
+    /// # Safety
+    /// This function is unsafe because it can enable interrupts that may not be
+    /// properly configured, potentially leading to undefined behavior.
+    unsafe fn enable(&self);
+
+    /// Disable this interrupt in NVIC.
+    ///
+    /// # Safety
+    /// This function is unsafe because disabling interrupts may leave the system
+    /// in an inconsistent state if the interrupt was expected to fire.
+    unsafe fn disable(&self);
+
+    /// Check if the interrupt is pending in NVIC.
+    fn is_pending(&self) -> bool;
+}
+
+#[derive(Clone, Copy, Debug, Default)]
+pub struct DefaultHandlerSnapshot {
+    pub vector: u16,
+    pub count: u32,
+    pub cfsr: u32,
+    pub hfsr: u32,
+    pub stacked_pc: u32,
+    pub stacked_lr: u32,
+    pub stacked_sp: u32,
+}
+
+static LAST_DEFAULT_VECTOR: AtomicU16 = AtomicU16::new(0);
+static LAST_DEFAULT_COUNT: AtomicU32 = AtomicU32::new(0);
+static LAST_DEFAULT_CFSR: AtomicU32 = AtomicU32::new(0);
+static LAST_DEFAULT_HFSR: AtomicU32 = AtomicU32::new(0);
+static LAST_DEFAULT_PC: AtomicU32 = AtomicU32::new(0);
+static LAST_DEFAULT_LR: AtomicU32 = AtomicU32::new(0);
+static LAST_DEFAULT_SP: AtomicU32 = AtomicU32::new(0);
+
+#[inline]
+pub fn default_handler_snapshot() -> DefaultHandlerSnapshot {
+    DefaultHandlerSnapshot {
+        vector: LAST_DEFAULT_VECTOR.load(Ordering::Relaxed),
+        count: LAST_DEFAULT_COUNT.load(Ordering::Relaxed),
+        cfsr: LAST_DEFAULT_CFSR.load(Ordering::Relaxed),
+        hfsr: LAST_DEFAULT_HFSR.load(Ordering::Relaxed),
+        stacked_pc: LAST_DEFAULT_PC.load(Ordering::Relaxed),
+        stacked_lr: LAST_DEFAULT_LR.load(Ordering::Relaxed),
+        stacked_sp: LAST_DEFAULT_SP.load(Ordering::Relaxed),
+    }
+}
+
+#[inline]
+pub fn clear_default_handler_snapshot() {
+    LAST_DEFAULT_VECTOR.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_COUNT.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_CFSR.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_HFSR.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_PC.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_LR.store(0, Ordering::Relaxed);
+    LAST_DEFAULT_SP.store(0, Ordering::Relaxed);
+}
+
+/// OS_EVENT interrupt helper with methods similar to embassy-imxrt's InterruptExt.
+pub struct OsEvent;
+pub const OS_EVENT: OsEvent = OsEvent;
+
+impl InterruptExt for OsEvent {
+    /// Clear any pending OS_EVENT in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::OS_EVENT);
+    }
+
+    /// Set NVIC priority for OS_EVENT.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::OS_EVENT, u8::from(priority));
+        }
+    }
+
+    /// Enable OS_EVENT in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::OS_EVENT);
+    }
+
+    /// Disable OS_EVENT in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::OS_EVENT);
+    }
+
+    /// Check if OS_EVENT is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::OS_EVENT)
+    }
+}
+
+impl OsEvent {
+    /// Configure OS_EVENT interrupt for timer operation.
+    /// This sets up the NVIC priority, enables the interrupt, and ensures global interrupts are enabled.
+    /// Also performs a software event to wake any pending WFE.
+    pub fn configure_for_timer(&self, priority: Priority) {
+        // Configure NVIC
+        self.unpend();
+        self.set_priority(priority);
+        unsafe {
+            self.enable();
+        }
+
+        // Ensure global interrupts are enabled in no-reset scenarios (e.g., cargo run)
+        // Debuggers typically perform a reset which leaves PRIMASK=0; cargo run may not.
+        unsafe {
+            cortex_m::interrupt::enable();
+        }
+
+        // Wake any executor WFE that might be sleeping when we armed the first deadline
+        cortex_m::asm::sev();
+    }
+}
+
+/// LPUART2 interrupt helper with methods similar to embassy-imxrt's InterruptExt.
+pub struct Lpuart2;
+pub const LPUART2: Lpuart2 = Lpuart2;
+
+impl InterruptExt for Lpuart2 {
+    /// Clear any pending LPUART2 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::LPUART2);
+    }
+
+    /// Set NVIC priority for LPUART2.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::LPUART2, u8::from(priority));
+        }
+    }
+
+    /// Enable LPUART2 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::LPUART2);
+    }
+
+    /// Disable LPUART2 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::LPUART2);
+    }
+
+    /// Check if LPUART2 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::LPUART2)
+    }
+}
+
+impl Lpuart2 {
+    /// Configure LPUART2 interrupt for UART operation.
+    /// This sets up the NVIC priority, enables the interrupt, and ensures global interrupts are enabled.
+    pub fn configure_for_uart(&self, priority: Priority) {
+        // Configure NVIC
+        self.unpend();
+        self.set_priority(priority);
+        unsafe {
+            self.enable();
+        }
+
+        // Ensure global interrupts are enabled in no-reset scenarios (e.g., cargo run)
+        // Debuggers typically perform a reset which leaves PRIMASK=0; cargo run may not.
+        unsafe {
+            cortex_m::interrupt::enable();
+        }
+    }
+
+    /// Install LPUART2 handler into the RAM vector table.
+    /// Safety: See `install_irq_handler`.
+    pub unsafe fn install_handler(&self, handler: unsafe extern "C" fn()) {
+        install_irq_handler(Interrupt::LPUART2, handler);
+    }
+}
+
+pub struct Rtc;
+pub const RTC: Rtc = Rtc;
+
+impl InterruptExt for Rtc {
+    /// Clear any pending RTC in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::RTC);
+    }
+
+    /// Set NVIC priority for RTC.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::RTC, u8::from(priority));
+        }
+    }
+
+    /// Enable RTC in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::RTC);
+    }
+
+    /// Disable RTC in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::RTC);
+    }
+
+    /// Check if RTC is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::RTC)
+    }
+}
+
+pub struct Adc;
+pub const ADC1: Adc = Adc;
+
+impl InterruptExt for Adc {
+    /// Clear any pending ADC1 in NVIC.
+    #[inline]
+    fn unpend(&self) {
+        cortex_m::peripheral::NVIC::unpend(Interrupt::ADC1);
+    }
+
+    /// Set NVIC priority for ADC1.
+    #[inline]
+    fn set_priority(&self, priority: Priority) {
+        unsafe {
+            let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
+            nvic.set_priority(Interrupt::ADC1, u8::from(priority));
+        }
+    }
+
+    /// Enable ADC1 in NVIC.
+    #[inline]
+    unsafe fn enable(&self) {
+        cortex_m::peripheral::NVIC::unmask(Interrupt::ADC1);
+    }
+
+    /// Disable ADC1 in NVIC.
+    #[inline]
+    unsafe fn disable(&self) {
+        cortex_m::peripheral::NVIC::mask(Interrupt::ADC1);
+    }
+
+    /// Check if ADC1 is pending in NVIC.
+    #[inline]
+    fn is_pending(&self) -> bool {
+        cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC1)
+    }
+}
+
+/// Set VTOR (Vector Table Offset) to a RAM-based vector table.
+/// Pass a pointer to the first word in the RAM table (stack pointer slot 0).
+/// Safety: Caller must ensure the RAM table is valid and aligned as required by the core.
+pub unsafe fn vtor_set_ram_vector_base(base: *const u32) {
+    core::ptr::write_volatile(0xE000_ED08 as *mut u32, base as u32);
+}
+
+/// Install an interrupt handler into the current VTOR-based vector table.
+/// This writes the function pointer at index 16 + irq number.
+/// Safety: Caller must ensure VTOR points at a writable RAM table and that `handler`
+/// has the correct ABI and lifetime.
+pub unsafe fn install_irq_handler(irq: Interrupt, handler: unsafe extern "C" fn()) {
+    let vtor_base = core::ptr::read_volatile(0xE000_ED08 as *const u32) as *mut u32;
+    let idx = 16 + (irq as isize as usize);
+    core::ptr::write_volatile(vtor_base.add(idx), handler as usize as u32);
+}
+
+impl OsEvent {
+    /// Convenience to install the OS_EVENT handler into the RAM vector table.
+    /// Safety: See `install_irq_handler`.
+    pub unsafe fn install_handler(&self, handler: extern "C" fn()) {
+        install_irq_handler(Interrupt::OS_EVENT, handler);
+    }
+}
+
+/// Install OS_EVENT handler by raw address. Useful to avoid fn pointer type mismatches.
+/// Safety: Caller must ensure the address is a valid `extern "C" fn()` handler.
+pub unsafe fn os_event_install_handler_raw(handler_addr: usize) {
+    let vtor_base = core::ptr::read_volatile(0xE000_ED08 as *const u32) as *mut u32;
+    let idx = 16 + (Interrupt::OS_EVENT as isize as usize);
+    core::ptr::write_volatile(vtor_base.add(idx), handler_addr as u32);
+}
+
+/// Provide a conservative default IRQ handler that avoids wedging the system.
+/// It clears all NVIC pending bits and returns, so spurious or reserved IRQs
+/// don’t trap the core in an infinite WFI loop during bring-up.
+#[no_mangle]
+pub unsafe extern "C" fn DefaultHandler() {
+    let active = core::ptr::read_volatile(0xE000_ED04 as *const u32) & 0x1FF;
+    let cfsr = core::ptr::read_volatile(0xE000_ED28 as *const u32);
+    let hfsr = core::ptr::read_volatile(0xE000_ED2C as *const u32);
+
+    let sp = cortex_m::register::msp::read();
+    let stacked = sp as *const u32;
+    // Stacked registers follow ARMv8-M procedure call standard order
+    let stacked_pc = unsafe { stacked.add(6).read() };
+    let stacked_lr = unsafe { stacked.add(5).read() };
+
+    LAST_DEFAULT_VECTOR.store(active as u16, Ordering::Relaxed);
+    LAST_DEFAULT_CFSR.store(cfsr, Ordering::Relaxed);
+    LAST_DEFAULT_HFSR.store(hfsr, Ordering::Relaxed);
+    LAST_DEFAULT_COUNT.fetch_add(1, Ordering::Relaxed);
+    LAST_DEFAULT_PC.store(stacked_pc, Ordering::Relaxed);
+    LAST_DEFAULT_LR.store(stacked_lr, Ordering::Relaxed);
+    LAST_DEFAULT_SP.store(sp, Ordering::Relaxed);
+
+    // Do nothing here: on some MCUs/TrustZone setups, writing NVIC from a spurious
+    // handler can fault if targeting the Secure bank. Just return.
+    cortex_m::asm::dsb();
+    cortex_m::asm::isb();
+}
diff --git a/src/lib.rs b/src/lib.rs
new file mode 100644
index 000000000..fe27aadba
--- /dev/null
+++ b/src/lib.rs
@@ -0,0 +1,142 @@
+#![no_std]
+
+pub mod clocks; // still provide clock helpers
+pub mod gpio;
+pub mod pins; // pin mux helpers
+pub mod reset; // reset control helpers
+
+pub mod adc;
+pub mod config;
+pub mod interrupt;
+pub mod lpuart;
+pub mod ostimer;
+pub mod rtc;
+pub mod uart;
+
+embassy_hal_internal::peripherals!(LPUART2, OSTIMER0, GPIO, RTC0, ADC1,);
+
+/// Get access to the PAC Peripherals for low-level register access.
+/// This is a lazy-initialized singleton that can be called after init().
+#[allow(static_mut_refs)]
+pub fn pac() -> &'static pac::Peripherals {
+    // SAFETY: We only call this after init(), and the PAC is a singleton.
+    // The embassy peripheral tokens ensure we don't have multiple mutable accesses.
+    unsafe {
+        static mut PAC_INSTANCE: Option<pac::Peripherals> = None;
+        if PAC_INSTANCE.is_none() {
+            PAC_INSTANCE = Some(pac::Peripherals::steal());
+        }
+        PAC_INSTANCE.as_ref().unwrap()
+    }
+}
+
+// Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it.
+
+// Re-export interrupt traits and types
+pub use adc::Adc1 as Adc1Token;
+pub use gpio::pins::*;
+pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output};
+pub use interrupt::InterruptExt;
+#[cfg(feature = "unstable-pac")]
+pub use mcxa_pac as pac;
+#[cfg(not(feature = "unstable-pac"))]
+pub(crate) use mcxa_pac as pac;
+pub use ostimer::Ostimer0 as Ostimer0Token;
+pub use rtc::Rtc0 as Rtc0Token;
+pub use uart::Lpuart2 as Uart2Token;
+
+/// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals.
+/// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling).
+#[allow(unused_variables)]
+pub fn init(cfg: crate::config::Config) -> Peripherals {
+    let peripherals = Peripherals::take();
+    // Apply user-configured priority early; enabling is left to examples/apps
+    crate::interrupt::OS_EVENT.set_priority(cfg.time_interrupt_priority);
+    // Apply user-configured priority early; enabling is left to examples/apps
+    crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority);
+    // Apply user-configured priority early; enabling is left to examples/apps
+    crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority);
+    peripherals
+}
+
+/// Optional hook called by cortex-m-rt before RAM init.
+/// We proactively mask and clear all NVIC IRQs to avoid wedges from stale state
+/// left by soft resets/debug sessions.
+///
+/// NOTE: Manual VTOR setup is required for RAM execution. The cortex-m-rt 'set-vtor'
+/// feature is incompatible with our setup because it expects __vector_table to be
+/// defined differently than how our RAM-based linker script arranges it.
+#[no_mangle]
+pub unsafe extern "C" fn __pre_init() {
+    // Set the VTOR to point to the interrupt vector table in RAM
+    // This is required since code runs from RAM on this MCU
+    crate::interrupt::vtor_set_ram_vector_base(0x2000_0000 as *const u32);
+
+    // Mask and clear pending for all NVIC lines (0..127) to avoid stale state across runs.
+    let nvic = &*cortex_m::peripheral::NVIC::PTR;
+    for i in 0..4 {
+        // 4 words x 32 = 128 IRQs
+        nvic.icer[i].write(0xFFFF_FFFF);
+        nvic.icpr[i].write(0xFFFF_FFFF);
+    }
+    // Do NOT touch peripheral registers here: clocks may be off and accesses can fault.
+    crate::interrupt::clear_default_handler_snapshot();
+}
+
+/// Internal helper to dispatch a type-level interrupt handler.
+#[inline(always)]
+#[doc(hidden)]
+pub unsafe fn __handle_interrupt<T, H>()
+where
+    T: crate::interrupt::typelevel::Interrupt,
+    H: crate::interrupt::typelevel::Handler<T>,
+{
+    H::on_interrupt();
+}
+
+/// Macro to bind interrupts to handlers, similar to embassy-imxrt.
+///
+/// Example:
+/// - Bind OS_EVENT to the OSTIMER time-driver handler
+///   bind_interrupts!(struct Irqs { OS_EVENT => crate::ostimer::time_driver::OsEventHandler; });
+#[macro_export]
+macro_rules! bind_interrupts {
+    ($(#[$attr:meta])* $vis:vis struct $name:ident {
+        $(
+            $(#[cfg($cond_irq:meta)])?
+            $irq:ident => $(
+                $(#[cfg($cond_handler:meta)])?
+                $handler:ty
+            ),*;
+        )*
+    }) => {
+        #[derive(Copy, Clone)]
+        $(#[$attr])*
+        $vis struct $name;
+
+        $(
+            #[allow(non_snake_case)]
+            #[no_mangle]
+            $(#[cfg($cond_irq)])?
+            unsafe extern "C" fn $irq() {
+                unsafe {
+                    $(
+                        $(#[cfg($cond_handler)])?
+                        <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
+                    )*
+                }
+            }
+
+            $(#[cfg($cond_irq)])?
+            $crate::bind_interrupts!(@inner
+                $(
+                    $(#[cfg($cond_handler)])?
+                    unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
+                )*
+            );
+        )*
+    };
+    (@inner $($t:tt)*) => {
+        $($t)*
+    }
+}
diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs
new file mode 100644
index 000000000..0413fed8e
--- /dev/null
+++ b/src/lpuart/buffered.rs
@@ -0,0 +1,675 @@
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::sync::atomic::{AtomicBool, Ordering};
+use core::task::Poll;
+
+use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
+use embassy_hal_internal::Peri;
+use embassy_sync::waitqueue::AtomicWaker;
+
+use super::*;
+use crate::interrupt;
+
+// ============================================================================
+// STATIC STATE MANAGEMENT
+// ============================================================================
+
+/// State for buffered LPUART operations
+pub struct State {
+    rx_waker: AtomicWaker,
+    rx_buf: RingBuffer,
+    tx_waker: AtomicWaker,
+    tx_buf: RingBuffer,
+    tx_done: AtomicBool,
+    initialized: AtomicBool,
+}
+
+impl State {
+    /// Create a new state instance
+    pub const fn new() -> Self {
+        Self {
+            rx_waker: AtomicWaker::new(),
+            rx_buf: RingBuffer::new(),
+            tx_waker: AtomicWaker::new(),
+            tx_buf: RingBuffer::new(),
+            tx_done: AtomicBool::new(true),
+            initialized: AtomicBool::new(false),
+        }
+    }
+}
+// ============================================================================
+// BUFFERED DRIVER STRUCTURES
+// ============================================================================
+
+/// Buffered LPUART driver
+pub struct BufferedLpuart<'a> {
+    tx: BufferedLpuartTx<'a>,
+    rx: BufferedLpuartRx<'a>,
+}
+
+/// Buffered LPUART TX driver
+pub struct BufferedLpuartTx<'a> {
+    info: Info,
+    state: &'static State,
+    _tx_pin: Peri<'a, AnyPin>,
+}
+
+/// Buffered LPUART RX driver
+pub struct BufferedLpuartRx<'a> {
+    info: Info,
+    state: &'static State,
+    _rx_pin: Peri<'a, AnyPin>,
+}
+
+// ============================================================================
+// BUFFERED LPUART IMPLEMENTATION
+// ============================================================================
+
+impl<'a> BufferedLpuart<'a> {
+    /// Create a new buffered LPUART instance
+    pub fn new<T: Instance>(
+        _inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        tx_buffer: &'a mut [u8],
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        // Configure pins
+        tx_pin.as_tx();
+        rx_pin.as_rx();
+
+        // Convert pins to AnyPin
+        let tx_pin: Peri<'a, AnyPin> = tx_pin.into();
+        let rx_pin: Peri<'a, AnyPin> = rx_pin.into();
+
+        let state = T::buffered_state();
+
+        // Initialize the peripheral
+        Self::init::<T>(Some(&tx_pin), Some(&rx_pin), None, None, tx_buffer, rx_buffer, config)?;
+
+        Ok(Self {
+            tx: BufferedLpuartTx {
+                info: T::info(),
+                state,
+                _tx_pin: tx_pin,
+            },
+            rx: BufferedLpuartRx {
+                info: T::info(),
+                state,
+                _rx_pin: rx_pin,
+            },
+        })
+    }
+
+    /// Create a new buffered LPUART with flexible pin configuration
+    pub fn new_with_pins<T: Instance>(
+        _inner: Peri<'a, T>,
+        tx_pin: Option<Peri<'a, impl TxPin<T>>>,
+        rx_pin: Option<Peri<'a, impl RxPin<T>>>,
+        rts_pin: Option<Peri<'a, impl RtsPin<T>>>,
+        cts_pin: Option<Peri<'a, impl CtsPin<T>>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        tx_buffer: &'a mut [u8],
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        // Configure pins if provided
+        let tx_pin = tx_pin.map(|pin| {
+            pin.as_tx();
+            let converted: Peri<'a, AnyPin> = pin.into();
+            converted
+        });
+
+        let rx_pin = rx_pin.map(|pin| {
+            pin.as_rx();
+            let converted: Peri<'a, AnyPin> = pin.into();
+            converted
+        });
+
+        let rts_pin = rts_pin.map(|pin| {
+            pin.as_rts();
+            let converted: Peri<'a, AnyPin> = pin.into();
+            converted
+        });
+
+        let cts_pin = cts_pin.map(|pin| {
+            pin.as_cts();
+            let converted: Peri<'a, AnyPin> = pin.into();
+            converted
+        });
+
+        let state = T::buffered_state();
+
+        // Initialize the peripheral
+        Self::init::<T>(
+            tx_pin.as_ref(),
+            rx_pin.as_ref(),
+            rts_pin.as_ref(),
+            cts_pin.as_ref(),
+            tx_buffer,
+            rx_buffer,
+            config,
+        )?;
+
+        // Create TX and RX instances
+        let (tx, rx) = if let (Some(tx_pin), Some(rx_pin)) = (tx_pin, rx_pin) {
+            (
+                BufferedLpuartTx {
+                    info: T::info(),
+                    state,
+                    _tx_pin: tx_pin,
+                },
+                BufferedLpuartRx {
+                    info: T::info(),
+                    state,
+                    _rx_pin: rx_pin,
+                },
+            )
+        } else {
+            return Err(Error::InvalidArgument);
+        };
+
+        Ok(Self { tx, rx })
+    }
+
+    fn init<T: Instance>(
+        _tx: Option<&Peri<'a, AnyPin>>,
+        _rx: Option<&Peri<'a, AnyPin>>,
+        _rts: Option<&Peri<'a, AnyPin>>,
+        _cts: Option<&Peri<'a, AnyPin>>,
+        tx_buffer: &'a mut [u8],
+        rx_buffer: &'a mut [u8],
+        mut config: Config,
+    ) -> Result<()> {
+        let regs = T::info().regs;
+        let state = T::buffered_state();
+
+        // Check if already initialized
+        if state.initialized.load(Ordering::Relaxed) {
+            return Err(Error::InvalidArgument);
+        }
+
+        // Initialize ring buffers
+        assert!(!tx_buffer.is_empty());
+        unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), tx_buffer.len()) }
+
+        assert!(!rx_buffer.is_empty());
+        unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), rx_buffer.len()) }
+
+        // Mark as initialized
+        state.initialized.store(true, Ordering::Relaxed);
+
+        // Enable TX and RX for buffered operation
+        config.enable_tx = true;
+        config.enable_rx = true;
+
+        // Perform standard initialization
+        perform_software_reset(regs);
+        disable_transceiver(regs);
+        configure_baudrate(regs, config.baudrate_bps, config.clock)?;
+        configure_frame_format(regs, &config);
+        configure_control_settings(regs, &config);
+        configure_fifo(regs, &config);
+        clear_all_status_flags(regs);
+        configure_flow_control(regs, &config);
+        configure_bit_order(regs, config.msb_firs);
+
+        // Enable interrupts for buffered operation
+        cortex_m::interrupt::free(|_| {
+            regs.ctrl().modify(|_, w| {
+                w.rie()
+                    .enabled() // RX interrupt
+                    .orie()
+                    .enabled() // Overrun interrupt
+                    .peie()
+                    .enabled() // Parity error interrupt
+                    .feie()
+                    .enabled() // Framing error interrupt
+                    .neie()
+                    .enabled() // Noise error interrupt
+            });
+        });
+
+        // Enable the transceiver
+        enable_transceiver(regs, config.enable_tx, config.enable_rx);
+
+        // Enable the interrupt
+        // unsafe {
+        //     // TODO: Used the propper interrupt enable method for the specific LPUART instance
+        //     // T::Interrupt::enable();
+        // }
+
+        Ok(())
+    }
+
+    /// Split the buffered LPUART into separate TX and RX parts
+    pub fn split(self) -> (BufferedLpuartTx<'a>, BufferedLpuartRx<'a>) {
+        (self.tx, self.rx)
+    }
+
+    /// Get mutable references to TX and RX parts
+    pub fn split_ref(&mut self) -> (&mut BufferedLpuartTx<'a>, &mut BufferedLpuartRx<'a>) {
+        (&mut self.tx, &mut self.rx)
+    }
+}
+
+// ============================================================================
+// BUFFERED TX IMPLEMENTATION
+// ============================================================================
+
+impl<'a> BufferedLpuartTx<'a> {
+    /// Create a new TX-only buffered LPUART
+    pub fn new<T: Instance>(
+        _inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        tx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+        let tx_pin: Peri<'a, AnyPin> = tx_pin.into();
+
+        let info = T::info();
+        let state = T::buffered_state();
+
+        // Check if already initialized
+        if state.initialized.load(Ordering::Relaxed) {
+            return Err(Error::InvalidArgument);
+        }
+
+        // Initialize TX ring buffer only
+        unsafe {
+            let tx_buf = &state.tx_buf as *const _ as *mut RingBuffer;
+            (*tx_buf).init(tx_buffer.as_mut_ptr(), tx_buffer.len());
+        }
+
+        state.initialized.store(true, Ordering::Relaxed);
+
+        // Initialize with TX only
+        BufferedLpuart::init::<T>(
+            Some(&tx_pin),
+            None,
+            None,
+            None,
+            tx_buffer,
+            &mut [], // Empty RX buffer
+            config,
+        )?;
+
+        Ok(Self {
+            info,
+            state,
+            _tx_pin: tx_pin,
+        })
+    }
+
+    /// Write data asynchronously
+    pub async fn write(&mut self, buf: &[u8]) -> Result<usize> {
+        let mut written = 0;
+
+        for &byte in buf {
+            // Wait for space in the buffer
+            poll_fn(|cx| {
+                self.state.tx_waker.register(cx.waker());
+
+                let mut writer = unsafe { self.state.tx_buf.writer() };
+                if writer.push_one(byte) {
+                    // Enable TX interrupt to start transmission
+                    cortex_m::interrupt::free(|_| {
+                        self.info.regs.ctrl().modify(|_, w| w.tie().enabled());
+                    });
+                    Poll::Ready(Ok(()))
+                } else {
+                    Poll::Pending
+                }
+            })
+            .await?;
+
+            written += 1;
+        }
+
+        Ok(written)
+    }
+
+    /// Flush the TX buffer and wait for transmission to complete
+    pub async fn flush(&mut self) -> Result<()> {
+        // Wait for TX buffer to empty and transmission to complete
+        poll_fn(|cx| {
+            self.state.tx_waker.register(cx.waker());
+
+            let tx_empty = self.state.tx_buf.is_empty();
+            let fifo_empty = self.info.regs.water().read().txcount().bits() == 0;
+            let tc_complete = self.info.regs.stat().read().tc().is_complete();
+
+            if tx_empty && fifo_empty && tc_complete {
+                Poll::Ready(Ok(()))
+            } else {
+                // Enable appropriate interrupt
+                cortex_m::interrupt::free(|_| {
+                    if !tx_empty {
+                        self.info.regs.ctrl().modify(|_, w| w.tie().enabled());
+                    } else {
+                        self.info.regs.ctrl().modify(|_, w| w.tcie().enabled());
+                    }
+                });
+                Poll::Pending
+            }
+        })
+        .await
+    }
+
+    /// Try to write without blocking
+    pub fn try_write(&mut self, buf: &[u8]) -> Result<usize> {
+        let mut writer = unsafe { self.state.tx_buf.writer() };
+        let mut written = 0;
+
+        for &byte in buf {
+            if writer.push_one(byte) {
+                written += 1;
+            } else {
+                break;
+            }
+        }
+
+        if written > 0 {
+            // Enable TX interrupt to start transmission
+            cortex_m::interrupt::free(|_| {
+                self.info.regs.ctrl().modify(|_, w| w.tie().enabled());
+            });
+        }
+
+        Ok(written)
+    }
+}
+
+// ============================================================================
+// BUFFERED RX IMPLEMENTATION
+// ============================================================================
+
+impl<'a> BufferedLpuartRx<'a> {
+    /// Create a new RX-only buffered LPUART
+    pub fn new<T: Instance>(
+        _inner: Peri<'a, T>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
+        rx_buffer: &'a mut [u8],
+        config: Config,
+    ) -> Result<Self> {
+        rx_pin.as_rx();
+        let rx_pin: Peri<'a, AnyPin> = rx_pin.into();
+
+        let info = T::info();
+        let state = T::buffered_state();
+
+        // Check if already initialized
+        if state.initialized.load(Ordering::Relaxed) {
+            return Err(Error::InvalidArgument);
+        }
+
+        // Initialize RX ring buffer only
+        unsafe {
+            let rx_buf = &state.rx_buf as *const _ as *mut RingBuffer;
+            (*rx_buf).init(rx_buffer.as_mut_ptr(), rx_buffer.len());
+        }
+
+        state.initialized.store(true, Ordering::Relaxed);
+
+        // Initialize with RX only
+        BufferedLpuart::init::<T>(
+            None,
+            Some(&rx_pin),
+            None,
+            None,
+            &mut [], // Empty TX buffer
+            rx_buffer,
+            config,
+        )?;
+
+        Ok(Self {
+            info,
+            state,
+            _rx_pin: rx_pin,
+        })
+    }
+
+    /// Read data asynchronously
+    pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize> {
+        if buf.is_empty() {
+            return Ok(0);
+        }
+
+        let mut read = 0;
+
+        // Try to read available data
+        poll_fn(|cx| {
+            self.state.rx_waker.register(cx.waker());
+
+            // Disable RX interrupt while reading from buffer
+            cortex_m::interrupt::free(|_| {
+                self.info.regs.ctrl().modify(|_, w| w.rie().disabled());
+            });
+
+            let mut reader = unsafe { self.state.rx_buf.reader() };
+            let available = reader.pop(|data| {
+                let to_copy = core::cmp::min(data.len(), buf.len() - read);
+                if to_copy > 0 {
+                    buf[read..read + to_copy].copy_from_slice(&data[..to_copy]);
+                    read += to_copy;
+                }
+                to_copy
+            });
+
+            // Re-enable RX interrupt
+            cortex_m::interrupt::free(|_| {
+                self.info.regs.ctrl().modify(|_, w| w.rie().enabled());
+            });
+
+            if read > 0 {
+                Poll::Ready(Ok(read))
+            } else if available == 0 {
+                Poll::Pending
+            } else {
+                Poll::Ready(Ok(0))
+            }
+        })
+        .await
+    }
+
+    /// Try to read without blocking
+    pub fn try_read(&mut self, buf: &mut [u8]) -> Result<usize> {
+        if buf.is_empty() {
+            return Ok(0);
+        }
+
+        // Disable RX interrupt while reading from buffer
+        cortex_m::interrupt::free(|_| {
+            self.info.regs.ctrl().modify(|_, w| w.rie().disabled());
+        });
+
+        let mut reader = unsafe { self.state.rx_buf.reader() };
+        let read = reader.pop(|data| {
+            let to_copy = core::cmp::min(data.len(), buf.len());
+            if to_copy > 0 {
+                buf[..to_copy].copy_from_slice(&data[..to_copy]);
+            }
+            to_copy
+        });
+
+        // Re-enable RX interrupt
+        cortex_m::interrupt::free(|_| {
+            self.info.regs.ctrl().modify(|_, w| w.rie().enabled());
+        });
+
+        Ok(read)
+    }
+}
+
+// ============================================================================
+// INTERRUPT HANDLER
+// ============================================================================
+
+/// Buffered UART interrupt handler
+pub struct BufferedInterruptHandler<T: Instance> {
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> crate::interrupt::typelevel::Handler<T::Interrupt> for BufferedInterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        let regs = T::info().regs;
+        let state = T::buffered_state();
+
+        // Check if this instance is initialized
+        if !state.initialized.load(Ordering::Relaxed) {
+            return;
+        }
+
+        let ctrl = regs.ctrl().read();
+        let stat = regs.stat().read();
+        let has_fifo = regs.param().read().rxfifo().bits() > 0;
+
+        // Handle overrun error
+        if stat.or().is_overrun() {
+            regs.stat().write(|w| w.or().clear_bit_by_one());
+            state.rx_waker.wake();
+            return;
+        }
+
+        // Clear other error flags
+        if stat.pf().is_parity() {
+            regs.stat().write(|w| w.pf().clear_bit_by_one());
+        }
+        if stat.fe().is_error() {
+            regs.stat().write(|w| w.fe().clear_bit_by_one());
+        }
+        if stat.nf().is_noise() {
+            regs.stat().write(|w| w.nf().clear_bit_by_one());
+        }
+
+        // Handle RX data
+        if ctrl.rie().is_enabled() && (has_data(regs) || stat.idle().is_idle()) {
+            let mut pushed_any = false;
+            let mut writer = state.rx_buf.writer();
+
+            if has_fifo {
+                // Read from FIFO
+                while regs.water().read().rxcount().bits() > 0 {
+                    let byte = (regs.data().read().bits() & 0xFF) as u8;
+                    if writer.push_one(byte) {
+                        pushed_any = true;
+                    } else {
+                        // Buffer full, stop reading
+                        break;
+                    }
+                }
+            } else {
+                // Read single byte
+                if regs.stat().read().rdrf().is_rxdata() {
+                    let byte = (regs.data().read().bits() & 0xFF) as u8;
+                    if writer.push_one(byte) {
+                        pushed_any = true;
+                    }
+                }
+            }
+
+            if pushed_any {
+                state.rx_waker.wake();
+            }
+
+            // Clear idle flag if set
+            if stat.idle().is_idle() {
+                regs.stat().write(|w| w.idle().clear_bit_by_one());
+            }
+        }
+
+        // Handle TX data
+        if ctrl.tie().is_enabled() {
+            let mut sent_any = false;
+            let mut reader = state.tx_buf.reader();
+
+            // Send data while TX buffer is ready and we have data
+            while regs.stat().read().tdre().is_no_txdata() {
+                if let Some(byte) = reader.pop_one() {
+                    regs.data().write(|w| w.bits(u32::from(byte)));
+                    sent_any = true;
+                } else {
+                    // No more data to send
+                    break;
+                }
+            }
+
+            if sent_any {
+                state.tx_waker.wake();
+            }
+
+            // If buffer is empty, switch to TC interrupt or disable
+            if state.tx_buf.is_empty() {
+                cortex_m::interrupt::free(|_| {
+                    regs.ctrl().modify(|_, w| w.tie().disabled().tcie().enabled());
+                });
+            }
+        }
+
+        // Handle transmission complete
+        if ctrl.tcie().is_enabled() {
+            if regs.stat().read().tc().is_complete() {
+                state.tx_done.store(true, Ordering::Release);
+                state.tx_waker.wake();
+
+                // Disable TC interrupt
+                cortex_m::interrupt::free(|_| {
+                    regs.ctrl().modify(|_, w| w.tcie().disabled());
+                });
+            }
+        }
+    }
+}
+
+// ============================================================================
+// EMBEDDED-IO ASYNC TRAIT IMPLEMENTATIONS
+// ============================================================================
+
+impl embedded_io_async::ErrorType for BufferedLpuartTx<'_> {
+    type Error = Error;
+}
+
+impl embedded_io_async::ErrorType for BufferedLpuartRx<'_> {
+    type Error = Error;
+}
+
+impl embedded_io_async::ErrorType for BufferedLpuart<'_> {
+    type Error = Error;
+}
+
+impl embedded_io_async::Write for BufferedLpuartTx<'_> {
+    async fn write(&mut self, buf: &[u8]) -> core::result::Result<usize, Self::Error> {
+        self.write(buf).await
+    }
+
+    async fn flush(&mut self) -> core::result::Result<(), Self::Error> {
+        self.flush().await
+    }
+}
+
+impl embedded_io_async::Read for BufferedLpuartRx<'_> {
+    async fn read(&mut self, buf: &mut [u8]) -> core::result::Result<usize, Self::Error> {
+        self.read(buf).await
+    }
+}
+
+impl embedded_io_async::Write for BufferedLpuart<'_> {
+    async fn write(&mut self, buf: &[u8]) -> core::result::Result<usize, Self::Error> {
+        self.tx.write(buf).await
+    }
+
+    async fn flush(&mut self) -> core::result::Result<(), Self::Error> {
+        self.tx.flush().await
+    }
+}
+
+impl embedded_io_async::Read for BufferedLpuart<'_> {
+    async fn read(&mut self, buf: &mut [u8]) -> core::result::Result<usize, Self::Error> {
+        self.rx.read(buf).await
+    }
+}
diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs
new file mode 100644
index 000000000..bed10bdb0
--- /dev/null
+++ b/src/lpuart/mod.rs
@@ -0,0 +1,1201 @@
+use core::marker::PhantomData;
+
+use embassy_hal_internal::{Peri, PeripheralType};
+use paste::paste;
+
+use crate::pac::lpuart0::baud::Sbns as StopBits;
+use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits};
+use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource};
+use crate::pac::lpuart0::stat::Msbf as MsbFirst;
+use crate::{interrupt, pac};
+
+pub mod buffered;
+
+// ============================================================================
+// STUB IMPLEMENTATION
+// ============================================================================
+
+// Stub implementation for LIB (Peripherals), GPIO, DMA and CLOCK until stable API
+// Pin and Clock initialization is currently done at the examples level.
+
+// --- START LIB ---
+
+// Use our own instance of Peripherals, until we align `lib.rs` with the EMBASSY-IMXRT approach
+// Inlined peripherals_definition! to bypass the `Peripherals::take_with_cs()` check
+// SHOULD NOT BE USED IN THE FINAL VERSION
+pub mod lib {
+    // embassy_hal_internal::peripherals!(LPUART2, PIO2_2, PIO2_3)
+
+    embassy_hal_internal::peripherals_definition!(LPUART2, PIO2_2, PIO2_3,);
+    #[doc = r" Struct containing all the peripheral singletons."]
+    #[doc = r""]
+    #[doc = r" To obtain the peripherals, you must initialize the HAL, by calling [`crate::init`]."]
+    #[allow(non_snake_case)]
+    pub struct Peripherals {
+        #[doc = concat!(stringify!(LPUART2)," peripheral")]
+        pub LPUART2: embassy_hal_internal::Peri<'static, peripherals::LPUART2>,
+        #[doc = concat!(stringify!(PIO2_2)," peripheral")]
+        pub PIO2_2: embassy_hal_internal::Peri<'static, peripherals::PIO2_2>,
+        #[doc = concat!(stringify!(PIO2_3)," peripheral")]
+        pub PIO2_3: embassy_hal_internal::Peri<'static, peripherals::PIO2_3>,
+    }
+    impl Peripherals {
+        #[doc = r"Returns all the peripherals *once*"]
+        #[inline]
+        pub(crate) fn take() -> Self {
+            critical_section::with(Self::take_with_cs)
+        }
+        #[doc = r"Returns all the peripherals *once*"]
+        #[inline]
+        pub(crate) fn take_with_cs(_cs: critical_section::CriticalSection) -> Self {
+            #[no_mangle]
+            static mut _EMBASSY_DEVICE_PERIPHERALS2: bool = false; // ALIGN: Temporary fix to use stub Peripherals
+            unsafe {
+                if _EMBASSY_DEVICE_PERIPHERALS2 {
+                    panic!("init called more than once!")
+                }
+                _EMBASSY_DEVICE_PERIPHERALS2 = true;
+                Self::steal()
+            }
+        }
+    }
+    impl Peripherals {
+        #[doc = r" Unsafely create an instance of this peripheral out of thin air."]
+        #[doc = r""]
+        #[doc = r" # Safety"]
+        #[doc = r""]
+        #[doc = r" You must ensure that you're only using one instance of this type at a time."]
+        #[inline]
+        pub unsafe fn steal() -> Self {
+            Self {
+                LPUART2: peripherals::LPUART2::steal(),
+                PIO2_2: peripherals::PIO2_2::steal(),
+                PIO2_3: peripherals::PIO2_3::steal(),
+            }
+        }
+    }
+
+    /// Initialize HAL
+    pub fn init() -> Peripherals {
+        Peripherals::take()
+    }
+}
+
+// --- END LIB ---
+
+// --- START GPIO ---
+
+mod gpio {
+    use embassy_hal_internal::PeripheralType;
+    trait SealedPin {}
+
+    #[allow(private_bounds)]
+    pub trait GpioPin: SealedPin + Sized + PeripheralType + Into<AnyPin> + 'static {
+        /// Type-erase the pin.
+        fn degrade(self) -> AnyPin {
+            todo!()
+        }
+    }
+
+    // Add this macro to implement GpioPin for all pins
+    macro_rules! impl_gpio_pin {
+        ($($pin:ident),*) => {
+            $(
+                impl SealedPin for super::lib::peripherals::$pin {}
+
+                impl GpioPin for super::lib::peripherals::$pin {}
+
+                impl Into<AnyPin> for super::lib::peripherals::$pin {
+                    fn into(self) -> AnyPin {
+                        AnyPin
+                    }
+                }
+            )*
+        };
+    }
+
+    // Implement GpioPin for all pins from lib.rs
+    impl_gpio_pin!(PIO2_2, PIO2_3);
+
+    #[derive(Debug, Clone, Copy)]
+    pub struct AnyPin;
+
+    impl PeripheralType for AnyPin {}
+
+    pub enum Alt {
+        ALT3,
+    }
+}
+
+use gpio::{AnyPin, GpioPin as Pin};
+
+// --- END GPIO ---
+
+// --- START DMA ---
+mod dma {
+    pub struct Channel<'d> {
+        pub(super) _lifetime: core::marker::PhantomData<&'d ()>,
+    }
+}
+
+use dma::Channel;
+
+// --- END DMA ---
+
+// --- START CLOCK ---
+mod clock {
+    #[derive(Debug, Clone, Copy)]
+    pub enum Clock {
+        FroLf, // Low-Frequency Free-Running Oscillator
+    }
+}
+
+use clock::Clock;
+
+// --- END CLOCK ---
+
+// ============================================================================
+// MISC
+// ============================================================================
+
+mod sealed {
+    /// Simply seal a trait to prevent external implementations
+    pub trait Sealed {}
+}
+
+// ============================================================================
+// INSTANCE TRAIT
+// ============================================================================
+
+pub type Regs = &'static crate::pac::lpuart0::RegisterBlock;
+
+pub trait SealedInstance {
+    fn info() -> Info;
+    fn index() -> usize;
+    fn buffered_state() -> &'static buffered::State;
+}
+
+pub struct Info {
+    pub regs: Regs,
+}
+
+/// Trait for LPUART peripheral instances
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + 'static + Send {
+    type Interrupt: interrupt::typelevel::Interrupt;
+}
+
+macro_rules! impl_instance {
+    ($($n:expr),*) => {
+        $(
+            paste!{
+                impl SealedInstance for lib::peripherals::[<LPUART $n>] {
+                    fn info() -> Info {
+                        Info {
+                            regs: unsafe { &*pac::[<Lpuart $n>]::ptr() },
+                        }
+                    }
+
+                    #[inline]
+                    fn index() -> usize {
+                        $n
+                    }
+
+                    fn buffered_state() -> &'static buffered::State {
+                        static BUFFERED_STATE: buffered::State = buffered::State::new();
+                        &BUFFERED_STATE
+                    }
+                }
+
+                impl Instance for lib::peripherals::[<LPUART $n>] {
+                    type Interrupt = crate::interrupt::typelevel::[<LPUART $n>];
+                }
+            }
+        )*
+    };
+}
+
+// impl_instance!(0, 1, 2, 3, 4);
+impl_instance!(2);
+
+// ============================================================================
+// INSTANCE HELPER FUNCTIONS
+// ============================================================================
+
+/// Perform software reset on the LPUART peripheral
+pub fn perform_software_reset(regs: Regs) {
+    // Software reset - set and clear RST bit (Global register)
+    regs.global().write(|w| w.rst().reset());
+    regs.global().write(|w| w.rst().no_effect());
+}
+
+/// Disable both transmitter and receiver
+pub fn disable_transceiver(regs: Regs) {
+    regs.ctrl().modify(|_, w| w.te().disabled().re().disabled());
+}
+
+/// Calculate and configure baudrate settings
+pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock: Clock) -> Result<()> {
+    let clock_freq = get_fc_freq(clock)?;
+    let (osr, sbr) = calculate_baudrate(baudrate_bps, clock_freq)?;
+
+    // Configure BAUD register
+    regs.baud().modify(|_, w| unsafe {
+        // Clear and set OSR
+        w.osr().bits((osr - 1) as u8);
+        // Clear and set SBR
+        w.sbr().bits(sbr);
+        // Set BOTHEDGE if OSR is between 4 and 7
+        if osr > 3 && osr < 8 {
+            w.bothedge().enabled()
+        } else {
+            w.bothedge().disabled()
+        }
+    });
+
+    Ok(())
+}
+
+/// Configure frame format (stop bits, data bits)
+pub fn configure_frame_format(regs: Regs, config: &Config) {
+    // Configure stop bits
+    regs.baud().modify(|_, w| w.sbns().variant(config.stop_bits_count));
+
+    // Clear M10 for now (10-bit mode)
+    regs.baud().modify(|_, w| w.m10().disabled());
+}
+
+/// Configure control settings (parity, data bits, idle config, pin swap)
+pub fn configure_control_settings(regs: Regs, config: &Config) {
+    regs.ctrl().modify(|_, w| {
+        // Parity configuration
+        let mut w = if let Some(parity) = config.parity_mode {
+            w.pe().enabled().pt().variant(parity)
+        } else {
+            w.pe().disabled()
+        };
+
+        // Data bits configuration
+        w = match config.data_bits_count {
+            DataBits::Data8 => {
+                if config.parity_mode.is_some() {
+                    w.m().data9() // 8 data + 1 parity = 9 bits
+                } else {
+                    w.m().data8() // 8 data bits only
+                }
+            }
+            DataBits::Data9 => w.m().data9(),
+        };
+
+        // Idle configuration
+        w = w.idlecfg().variant(config.rx_idle_config);
+        w = w.ilt().variant(config.rx_idle_type);
+
+        // Swap TXD/RXD if configured
+        if config.swap_txd_rxd {
+            w.swap().swap()
+        } else {
+            w.swap().standard()
+        }
+    });
+}
+
+/// Configure FIFO settings and watermarks
+pub fn configure_fifo(regs: Regs, config: &Config) {
+    // Configure WATER register for FIFO watermarks
+    regs.water().write(|w| unsafe {
+        w.rxwater()
+            .bits(config.rx_fifo_watermark as u8)
+            .txwater()
+            .bits(config.tx_fifo_watermark as u8)
+    });
+
+    // Enable TX/RX FIFOs
+    regs.fifo().modify(|_, w| w.txfe().enabled().rxfe().enabled());
+
+    // Flush FIFOs
+    regs.fifo()
+        .modify(|_, w| w.txflush().txfifo_rst().rxflush().rxfifo_rst());
+}
+
+/// Clear all status flags
+pub fn clear_all_status_flags(regs: Regs) {
+    regs.stat().reset();
+}
+
+/// Configure hardware flow control if enabled
+pub fn configure_flow_control(regs: Regs, config: &Config) {
+    if config.enable_rx_rts || config.enable_tx_cts {
+        regs.modir().modify(|_, w| {
+            let mut w = w;
+
+            // Configure TX CTS
+            w = w.txctsc().variant(config.tx_cts_config);
+            w = w.txctssrc().variant(config.tx_cts_source);
+
+            if config.enable_rx_rts {
+                w = w.rxrtse().enabled();
+            } else {
+                w = w.rxrtse().disabled();
+            }
+
+            if config.enable_tx_cts {
+                w = w.txctse().enabled();
+            } else {
+                w = w.txctse().disabled();
+            }
+
+            w
+        });
+    }
+}
+
+/// Configure bit order (MSB first or LSB first)
+pub fn configure_bit_order(regs: Regs, msb_first: MsbFirst) {
+    regs.stat().modify(|_, w| w.msbf().variant(msb_first));
+}
+
+/// Enable transmitter and/or receiver based on configuration
+pub fn enable_transceiver(regs: Regs, enable_tx: bool, enable_rx: bool) {
+    regs.ctrl().modify(|_, w| {
+        let mut w = w;
+        if enable_tx {
+            w = w.te().enabled();
+        }
+        if enable_rx {
+            w = w.re().enabled();
+        }
+        w
+    });
+}
+
+pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)> {
+    let mut baud_diff = baudrate;
+    let mut osr = 0u8;
+    let mut sbr = 0u16;
+
+    // Try OSR values from 4 to 32
+    for osr_temp in 4u8..=32u8 {
+        // Calculate SBR: (srcClock_Hz * 2 / (baudRate * osr) + 1) / 2
+        let sbr_calc = ((src_clock_hz * 2) / (baudrate * osr_temp as u32) + 1) / 2;
+
+        let sbr_temp = if sbr_calc == 0 {
+            1
+        } else if sbr_calc > 0x1FFF {
+            0x1FFF
+        } else {
+            sbr_calc as u16
+        };
+
+        // Calculate actual baud rate
+        let calculated_baud = src_clock_hz / (osr_temp as u32 * sbr_temp as u32);
+
+        let temp_diff = if calculated_baud > baudrate {
+            calculated_baud - baudrate
+        } else {
+            baudrate - calculated_baud
+        };
+
+        if temp_diff <= baud_diff {
+            baud_diff = temp_diff;
+            osr = osr_temp;
+            sbr = sbr_temp;
+        }
+    }
+
+    // Check if baud rate difference is within 3%
+    if baud_diff > (baudrate / 100) * 3 {
+        return Err(Error::UnsupportedBaudrate);
+    }
+
+    Ok((osr, sbr))
+}
+
+pub fn get_fc_freq(clock: Clock) -> Result<u32> {
+    // This is a placeholder - actual implementation would query the clock system
+    // In real implementation, this would get the LPUART clock frequency
+    match clock {
+        Clock::FroLf => Ok(12_000_000), // Low frequency oscillator
+        #[allow(unreachable_patterns)]
+        _ => Err(Error::InvalidArgument),
+    }
+}
+
+/// Wait for all transmit operations to complete
+pub fn wait_for_tx_complete(regs: Regs) {
+    // Wait for TX FIFO to empty
+    while regs.water().read().txcount().bits() != 0 {
+        // Wait for TX FIFO to drain
+    }
+
+    // Wait for last character to shift out (TC = Transmission Complete)
+    while regs.stat().read().tc().is_active() {
+        // Wait for transmission to complete
+    }
+}
+
+pub fn check_and_clear_rx_errors(regs: Regs) -> Result<()> {
+    let stat = regs.stat().read();
+    let mut status = Ok(());
+
+    // Check for overrun first - other error flags are prevented when OR is set
+    if stat.or().is_overrun() {
+        regs.stat().write(|w| w.or().clear_bit_by_one());
+
+        return Err(Error::Overrun);
+    }
+
+    if stat.pf().is_parity() {
+        regs.stat().write(|w| w.pf().clear_bit_by_one());
+        status = Err(Error::Parity);
+    }
+
+    if stat.fe().is_error() {
+        regs.stat().write(|w| w.fe().clear_bit_by_one());
+        status = Err(Error::Framing);
+    }
+
+    if stat.nf().is_noise() {
+        regs.stat().write(|w| w.nf().clear_bit_by_one());
+        status = Err(Error::Noise);
+    }
+
+    status
+}
+
+pub fn has_data(regs: Regs) -> bool {
+    if regs.param().read().rxfifo().bits() > 0 {
+        // FIFO is available - check RXCOUNT in WATER register
+        regs.water().read().rxcount().bits() > 0
+    } else {
+        // No FIFO - check RDRF flag in STAT register
+        regs.stat().read().rdrf().is_rxdata()
+    }
+}
+
+// ============================================================================
+// PIN TRAITS FOR LPUART FUNCTIONALITY
+// ============================================================================
+
+impl<T: Pin> sealed::Sealed for T {}
+
+/// io configuration trait for Lpuart Tx configuration
+pub trait TxPin<T: Instance>: Pin + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Lpuart Tx  usage
+    fn as_tx(&self);
+}
+
+/// io configuration trait for Lpuart Rx configuration
+pub trait RxPin<T: Instance>: Pin + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Lpuart Rx  usage
+    fn as_rx(&self);
+}
+
+/// io configuration trait for Lpuart Cts
+pub trait CtsPin<T: Instance>: Pin + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Lpuart Cts usage
+    fn as_cts(&self);
+}
+
+/// io configuration trait for Lpuart Rts
+pub trait RtsPin<T: Instance>: Pin + sealed::Sealed + PeripheralType {
+    /// convert the pin to appropriate function for Lpuart Rts usage
+    fn as_rts(&self);
+}
+
+macro_rules! impl_pin_trait {
+    ($fcn:ident, $mode:ident, $($pin:ident, $alt:ident),*) => {
+        paste! {
+            $(
+                impl [<$mode:camel Pin>]<lib::peripherals::$fcn> for lib::peripherals::$pin {
+                    fn [<as_ $mode>](&self) {
+                        let _alt = gpio::Alt::$alt;
+                        // todo!("Configure pin for LPUART function")
+                    }
+                }
+            )*
+        }
+    };
+}
+
+// Document identifier: MCXA343/344 Rev. 1DraftB ReleaseCandidate, 2025-07-10 - 6.1 MCX A173, A174 Signal Multiplexing and Pin Assignments
+// impl_pin_trait!(LPUART0, rx, PIO2_0, ALT2, PIO0_2, ALT2, PIO0_20, ALT3);
+// impl_pin_trait!(LPUART0, tx, PIO2_1, ALT2, PIO0_3, ALT2, PIO0_21, ALT3);
+// impl_pin_trait!(LPUART0, rts, PIO2_2, ALT2, PIO0_0, ALT2, PIO0_22, ALT3);
+// impl_pin_trait!(LPUART0, cts, PIO2_3, ALT2, PIO0_1, ALT2, PIO0_23, ALT3);
+impl_pin_trait!(LPUART2, rx, PIO2_3, ALT3);
+impl_pin_trait!(LPUART2, tx, PIO2_2, ALT3);
+
+// ============================================================================
+// ERROR TYPES AND RESULTS
+// ============================================================================
+
+/// LPUART error types
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    /// Read error
+    Read,
+    /// Buffer overflow
+    Overrun,
+    /// Noise error
+    Noise,
+    /// Framing error
+    Framing,
+    /// Parity error
+    Parity,
+    /// Failure
+    Fail,
+    /// Invalid argument
+    InvalidArgument,
+    /// Lpuart baud rate cannot be supported with the given clock
+    UnsupportedBaudrate,
+    /// RX FIFO Empty
+    RxFifoEmpty,
+    /// TX FIFO Full
+    TxFifoFull,
+    /// TX Busy
+    TxBusy,
+}
+
+/// A specialized Result type for LPUART operations
+pub type Result<T> = core::result::Result<T, Error>;
+
+// ============================================================================
+// CONFIGURATION STRUCTURES
+// ============================================================================
+
+/// Lpuart config
+#[derive(Debug, Clone, Copy)]
+pub struct Config {
+    /// Baud rate in bits per second
+    pub baudrate_bps: u32,
+    /// Clock
+    pub clock: Clock,
+    /// Parity configuration
+    pub parity_mode: Option<Parity>,
+    /// Number of data bits
+    pub data_bits_count: DataBits,
+    /// MSB First or LSB First configuration
+    pub msb_firs: MsbFirst,
+    /// Number of stop bits
+    pub stop_bits_count: StopBits,
+    /// TX FIFO watermark
+    pub tx_fifo_watermark: u8,
+    /// RX FIFO watermark
+    pub rx_fifo_watermark: u8,
+    /// RX RTS enable
+    pub enable_rx_rts: bool,
+    /// TX CTS enable
+    pub enable_tx_cts: bool,
+    /// TX CTS source
+    pub tx_cts_source: TxCtsSource,
+    /// TX CTS configure
+    pub tx_cts_config: TxCtsConfig,
+    /// RX IDLE type
+    pub rx_idle_type: IdleType,
+    /// RX IDLE configuration
+    pub rx_idle_config: IdleConfig,
+    /// Enable transmitter
+    pub enable_tx: bool,
+    /// Enable receiver
+    pub enable_rx: bool,
+    /// Swap TXD and RXD pins
+    pub swap_txd_rxd: bool,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            baudrate_bps: 115_200u32,
+            clock: Clock::FroLf,
+            parity_mode: None,
+            data_bits_count: DataBits::Data8,
+            msb_firs: MsbFirst::LsbFirst,
+            stop_bits_count: StopBits::One,
+            tx_fifo_watermark: 0,
+            rx_fifo_watermark: 1,
+            enable_rx_rts: false,
+            enable_tx_cts: false,
+            tx_cts_source: TxCtsSource::Cts,
+            tx_cts_config: TxCtsConfig::Start,
+            rx_idle_type: IdleType::FromStart,
+            rx_idle_config: IdleConfig::Idle1,
+            enable_tx: false,
+            enable_rx: false,
+            swap_txd_rxd: false,
+        }
+    }
+}
+
+/// LPUART status flags
+#[derive(Debug, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct Status {
+    /// Transmit data register empty
+    pub tx_empty: bool,
+    /// Transmission complete
+    pub tx_complete: bool,
+    /// Receive data register full
+    pub rx_full: bool,
+    /// Idle line detected
+    pub idle: bool,
+    /// Receiver overrun
+    pub overrun: bool,
+    /// Noise error
+    pub noise: bool,
+    /// Framing error
+    pub framing: bool,
+    /// Parity error
+    pub parity: bool,
+}
+
+// ============================================================================
+// MODE TRAITS (BLOCKING/ASYNC)
+// ============================================================================
+
+/// Driver move trait.
+#[allow(private_bounds)]
+pub trait Mode: sealed::Sealed {}
+
+/// Blocking mode.
+pub struct Blocking;
+impl sealed::Sealed for Blocking {}
+impl Mode for Blocking {}
+
+/// Async mode.
+pub struct Async;
+impl sealed::Sealed for Async {}
+impl Mode for Async {}
+
+// ============================================================================
+// CORE DRIVER STRUCTURES
+// ============================================================================
+
+/// Lpuart driver.
+pub struct Lpuart<'a, M: Mode> {
+    info: Info,
+    tx: LpuartTx<'a, M>,
+    rx: LpuartRx<'a, M>,
+}
+
+/// Lpuart TX driver.
+pub struct LpuartTx<'a, M: Mode> {
+    info: Info,
+    _tx_pin: Peri<'a, AnyPin>,
+    _tx_dma: Option<Channel<'a>>,
+    mode: PhantomData<(&'a (), M)>,
+}
+
+/// Lpuart Rx driver.
+pub struct LpuartRx<'a, M: Mode> {
+    info: Info,
+    _rx_pin: Peri<'a, AnyPin>,
+    _rx_dma: Option<Channel<'a>>,
+    mode: PhantomData<(&'a (), M)>,
+}
+
+// ============================================================================
+// LPUART CORE IMPLEMENTATION
+// ============================================================================
+
+impl<'a, M: Mode> Lpuart<'a, M> {
+    fn init<T: Instance>(
+        _tx: Option<&Peri<'a, AnyPin>>,
+        _rx: Option<&Peri<'a, AnyPin>>,
+        _rts: Option<&Peri<'a, AnyPin>>,
+        _cts: Option<&Peri<'a, AnyPin>>,
+        config: Config,
+    ) -> Result<()> {
+        let regs = T::info().regs;
+
+        // Perform initialization sequence
+        perform_software_reset(regs);
+        disable_transceiver(regs);
+        configure_baudrate(regs, config.baudrate_bps, config.clock)?;
+        configure_frame_format(regs, &config);
+        configure_control_settings(regs, &config);
+        configure_fifo(regs, &config);
+        clear_all_status_flags(regs);
+        configure_flow_control(regs, &config);
+        configure_bit_order(regs, config.msb_firs);
+        enable_transceiver(regs, config.enable_tx, config.enable_rx);
+
+        Ok(())
+    }
+
+    /// Deinitialize the LPUART peripheral
+    pub fn deinit(&self) -> Result<()> {
+        let regs = self.info.regs;
+
+        // Wait for TX operations to complete
+        wait_for_tx_complete(regs);
+
+        // Clear all status flags
+        clear_all_status_flags(regs);
+
+        // Disable the module - clear all CTRL register bits
+        regs.ctrl().reset();
+
+        Ok(())
+    }
+
+    /// Split the Lpuart into a transmitter and receiver
+    pub fn split(self) -> (LpuartTx<'a, M>, LpuartRx<'a, M>) {
+        (self.tx, self.rx)
+    }
+
+    /// Split the Lpuart into a transmitter and receiver by mutable reference
+    pub fn split_ref(&mut self) -> (&mut LpuartTx<'a, M>, &mut LpuartRx<'a, M>) {
+        (&mut self.tx, &mut self.rx)
+    }
+}
+
+// ============================================================================
+// BLOCKING MODE IMPLEMENTATIONS
+// ============================================================================
+
+impl<'a> Lpuart<'a, Blocking> {
+    /// Create a new blocking LPUART instance with TX and RX pins.
+    pub fn new_blocking<T: Instance>(
+        _inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        // Configure the pins for LPUART usage
+        tx_pin.as_tx();
+        rx_pin.as_rx();
+
+        // Convert pins to AnyPin
+        let tx_pin: Peri<'a, AnyPin> = tx_pin.into();
+        let rx_pin: Peri<'a, AnyPin> = rx_pin.into();
+
+        // Initialize the peripheral
+        Self::init::<T>(Some(&tx_pin), Some(&rx_pin), None, None, config)?;
+
+        Ok(Self {
+            info: T::info(),
+            tx: LpuartTx::new_inner(T::info(), tx_pin, None),
+            rx: LpuartRx::new_inner(T::info(), rx_pin, None),
+        })
+    }
+}
+
+// ----------------------------------------------------------------------------
+// Blocking TX Implementation
+// ----------------------------------------------------------------------------
+
+impl<'a, M: Mode> LpuartTx<'a, M> {
+    fn new_inner(info: Info, tx_pin: Peri<'a, AnyPin>, tx_dma: Option<Channel<'a>>) -> Self {
+        Self {
+            info,
+            _tx_pin: tx_pin,
+            _tx_dma: tx_dma,
+            mode: PhantomData,
+        }
+    }
+}
+
+impl<'a> LpuartTx<'a, Blocking> {
+    /// Create a new blocking LPUART which can only send data.
+    pub fn new_blocking<T: Instance>(
+        _inner: Peri<'a, T>,
+        tx_pin: Peri<'a, impl TxPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        tx_pin.as_tx();
+
+        let tx_pin: Peri<'a, AnyPin> = tx_pin.into();
+
+        Lpuart::<Blocking>::init::<T>(Some(&tx_pin), None, None, None, config)?;
+
+        Ok(Self::new_inner(T::info(), tx_pin, None))
+    }
+
+    fn write_byte_internal(&mut self, byte: u8) -> Result<()> {
+        self.info.regs.data().modify(|_, w| unsafe { w.bits(u32::from(byte)) });
+
+        Ok(())
+    }
+
+    fn blocking_write_byte(&mut self, byte: u8) -> Result<()> {
+        while self.info.regs.stat().read().tdre().is_txdata() {}
+        self.write_byte_internal(byte)
+    }
+
+    fn write_byte(&mut self, byte: u8) -> Result<()> {
+        if self.info.regs.stat().read().tdre().is_txdata() {
+            Err(Error::TxFifoFull)
+        } else {
+            self.write_byte_internal(byte)
+        }
+    }
+
+    /// Write data to LPUART TX blocking execution until all data is sent.
+    pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> {
+        for x in buf {
+            self.blocking_write_byte(*x)?;
+        }
+
+        Ok(())
+    }
+
+    /// Write data to LPUART TX without blocking.
+    pub fn write(&mut self, buf: &[u8]) -> Result<()> {
+        for x in buf {
+            self.write_byte(*x)?;
+        }
+
+        Ok(())
+    }
+
+    /// Flush LPUART TX blocking execution until all data has been transmitted.
+    pub fn blocking_flush(&mut self) -> Result<()> {
+        while self.info.regs.water().read().txcount().bits() != 0 {
+            // Wait for TX FIFO to drain
+        }
+
+        // Wait for last character to shift out
+        while self.info.regs.stat().read().tc().is_active() {
+            // Wait for transmission to complete
+        }
+
+        Ok(())
+    }
+
+    /// Flush LPUART TX.
+    pub fn flush(&mut self) -> Result<()> {
+        // Check if TX FIFO is empty
+        if self.info.regs.water().read().txcount().bits() != 0 {
+            return Err(Error::TxBusy);
+        }
+
+        // Check if transmission is complete
+        if self.info.regs.stat().read().tc().is_active() {
+            return Err(Error::TxBusy);
+        }
+
+        Ok(())
+    }
+}
+
+// ----------------------------------------------------------------------------
+// Blocking RX Implementation
+// ----------------------------------------------------------------------------
+
+impl<'a, M: Mode> LpuartRx<'a, M> {
+    fn new_inner(info: Info, rx_pin: Peri<'a, AnyPin>, rx_dma: Option<Channel<'a>>) -> Self {
+        Self {
+            info,
+            _rx_pin: rx_pin,
+            _rx_dma: rx_dma,
+            mode: PhantomData,
+        }
+    }
+}
+
+impl<'a> LpuartRx<'a, Blocking> {
+    /// Create a new blocking LPUART which can only receive data.
+    pub fn new_blocking<T: Instance>(
+        _inner: Peri<'a, T>,
+        rx_pin: Peri<'a, impl RxPin<T>>,
+        config: Config,
+    ) -> Result<Self> {
+        rx_pin.as_rx();
+
+        let rx_pin: Peri<'a, AnyPin> = rx_pin.into();
+
+        Lpuart::<Blocking>::init::<T>(None, Some(&rx_pin), None, None, config)?;
+
+        Ok(Self::new_inner(T::info(), rx_pin, None))
+    }
+
+    fn read_byte_internal(&mut self) -> Result<u8> {
+        let data = self.info.regs.data().read();
+
+        Ok((data.bits() & 0xFF) as u8)
+    }
+
+    fn read_byte(&mut self) -> Result<u8> {
+        check_and_clear_rx_errors(self.info.regs)?;
+
+        if !has_data(self.info.regs) {
+            return Err(Error::RxFifoEmpty);
+        }
+
+        self.read_byte_internal()
+    }
+
+    fn blocking_read_byte(&mut self) -> Result<u8> {
+        loop {
+            if has_data(self.info.regs) {
+                return self.read_byte_internal();
+            }
+
+            check_and_clear_rx_errors(self.info.regs)?;
+        }
+    }
+
+    /// Read data from LPUART RX without blocking.
+    pub fn read(&mut self, buf: &mut [u8]) -> Result<()> {
+        for byte in buf.iter_mut() {
+            *byte = self.read_byte()?;
+        }
+        Ok(())
+    }
+
+    /// Read data from LPUART RX blocking execution until the buffer is filled.
+    pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> {
+        for byte in buf.iter_mut() {
+            *byte = self.blocking_read_byte()?;
+        }
+        Ok(())
+    }
+}
+
+impl<'a> Lpuart<'a, Blocking> {
+    /// Read data from LPUART RX blocking execution until the buffer is filled
+    pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> {
+        self.rx.blocking_read(buf)
+    }
+
+    /// Read data from LPUART RX without blocking
+    pub fn read(&mut self, buf: &mut [u8]) -> Result<()> {
+        self.rx.read(buf)
+    }
+
+    /// Write data to LPUART TX blocking execution until all data is sent
+    pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> {
+        self.tx.blocking_write(buf)
+    }
+
+    /// Write data to LPUART TX without blocking
+    pub fn write(&mut self, buf: &[u8]) -> Result<()> {
+        self.tx.write(buf)
+    }
+
+    /// Flush LPUART TX blocking execution until all data has been transmitted
+    pub fn blocking_flush(&mut self) -> Result<()> {
+        self.tx.blocking_flush()
+    }
+
+    /// Flush LPUART TX without blocking
+    pub fn flush(&mut self) -> Result<()> {
+        self.tx.flush()
+    }
+}
+
+// ============================================================================
+// ASYNC MODE IMPLEMENTATIONS
+// ============================================================================
+
+// TODO: Implement async mode for LPUART
+
+// ============================================================================
+// EMBEDDED-HAL 0.2 TRAIT IMPLEMENTATIONS
+// ============================================================================
+
+impl embedded_hal_02::serial::Read<u8> for LpuartRx<'_, Blocking> {
+    type Error = Error;
+
+    fn read(&mut self) -> core::result::Result<u8, nb::Error<Self::Error>> {
+        let mut buf = [0; 1];
+        match self.read(&mut buf) {
+            Ok(_) => Ok(buf[0]),
+            Err(Error::RxFifoEmpty) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+}
+
+impl embedded_hal_02::serial::Write<u8> for LpuartTx<'_, Blocking> {
+    type Error = Error;
+
+    fn write(&mut self, word: u8) -> core::result::Result<(), nb::Error<Self::Error>> {
+        match self.write(&[word]) {
+            Ok(_) => Ok(()),
+            Err(Error::TxFifoFull) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+
+    fn flush(&mut self) -> core::result::Result<(), nb::Error<Self::Error>> {
+        match self.flush() {
+            Ok(_) => Ok(()),
+            Err(Error::TxBusy) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+}
+
+impl embedded_hal_02::blocking::serial::Write<u8> for LpuartTx<'_, Blocking> {
+    type Error = Error;
+
+    fn bwrite_all(&mut self, buffer: &[u8]) -> core::result::Result<(), Self::Error> {
+        self.blocking_write(buffer)
+    }
+
+    fn bflush(&mut self) -> core::result::Result<(), Self::Error> {
+        self.blocking_flush()
+    }
+}
+
+impl embedded_hal_02::serial::Read<u8> for Lpuart<'_, Blocking> {
+    type Error = Error;
+
+    fn read(&mut self) -> core::result::Result<u8, nb::Error<Self::Error>> {
+        embedded_hal_02::serial::Read::read(&mut self.rx)
+    }
+}
+
+impl embedded_hal_02::serial::Write<u8> for Lpuart<'_, Blocking> {
+    type Error = Error;
+
+    fn write(&mut self, word: u8) -> core::result::Result<(), nb::Error<Self::Error>> {
+        embedded_hal_02::serial::Write::write(&mut self.tx, word)
+    }
+
+    fn flush(&mut self) -> core::result::Result<(), nb::Error<Self::Error>> {
+        embedded_hal_02::serial::Write::flush(&mut self.tx)
+    }
+}
+
+impl embedded_hal_02::blocking::serial::Write<u8> for Lpuart<'_, Blocking> {
+    type Error = Error;
+
+    fn bwrite_all(&mut self, buffer: &[u8]) -> core::result::Result<(), Self::Error> {
+        self.blocking_write(buffer)
+    }
+
+    fn bflush(&mut self) -> core::result::Result<(), Self::Error> {
+        self.blocking_flush()
+    }
+}
+
+// ============================================================================
+// EMBEDDED-HAL-NB TRAIT IMPLEMENTATIONS
+// ============================================================================
+
+impl embedded_hal_nb::serial::Error for Error {
+    fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
+        match *self {
+            Self::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat,
+            Self::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun,
+            Self::Parity => embedded_hal_nb::serial::ErrorKind::Parity,
+            Self::Noise => embedded_hal_nb::serial::ErrorKind::Noise,
+            _ => embedded_hal_nb::serial::ErrorKind::Other,
+        }
+    }
+}
+
+impl embedded_hal_nb::serial::ErrorType for LpuartRx<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_hal_nb::serial::ErrorType for LpuartTx<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_hal_nb::serial::ErrorType for Lpuart<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_hal_nb::serial::Read for LpuartRx<'_, Blocking> {
+    fn read(&mut self) -> nb::Result<u8, Self::Error> {
+        let mut buf = [0; 1];
+        match self.read(&mut buf) {
+            Ok(_) => Ok(buf[0]),
+            Err(Error::RxFifoEmpty) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+}
+
+impl embedded_hal_nb::serial::Write for LpuartTx<'_, Blocking> {
+    fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
+        match self.write(&[word]) {
+            Ok(_) => Ok(()),
+            Err(Error::TxFifoFull) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+
+    fn flush(&mut self) -> nb::Result<(), Self::Error> {
+        match self.flush() {
+            Ok(_) => Ok(()),
+            Err(Error::TxBusy) => Err(nb::Error::WouldBlock),
+            Err(e) => Err(nb::Error::Other(e)),
+        }
+    }
+}
+
+impl embedded_hal_nb::serial::Read for Lpuart<'_, Blocking> {
+    fn read(&mut self) -> nb::Result<u8, Self::Error> {
+        embedded_hal_nb::serial::Read::read(&mut self.rx)
+    }
+}
+
+impl embedded_hal_nb::serial::Write for Lpuart<'_, Blocking> {
+    fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
+        embedded_hal_nb::serial::Write::write(&mut self.tx, char)
+    }
+
+    fn flush(&mut self) -> nb::Result<(), Self::Error> {
+        embedded_hal_nb::serial::Write::flush(&mut self.tx)
+    }
+}
+
+// ============================================================================
+// EMBEDDED-IO TRAIT IMPLEMENTATIONS
+// ============================================================================
+
+impl embedded_io::Error for Error {
+    fn kind(&self) -> embedded_io::ErrorKind {
+        embedded_io::ErrorKind::Other
+    }
+}
+
+impl embedded_io::ErrorType for LpuartRx<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_io::ErrorType for LpuartTx<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_io::ErrorType for Lpuart<'_, Blocking> {
+    type Error = Error;
+}
+
+impl embedded_io::Read for LpuartRx<'_, Blocking> {
+    fn read(&mut self, buf: &mut [u8]) -> core::result::Result<usize, Self::Error> {
+        self.blocking_read(buf).map(|_| buf.len())
+    }
+}
+
+impl embedded_io::Write for LpuartTx<'_, Blocking> {
+    fn write(&mut self, buf: &[u8]) -> core::result::Result<usize, Self::Error> {
+        self.blocking_write(buf).map(|_| buf.len())
+    }
+
+    fn flush(&mut self) -> core::result::Result<(), Self::Error> {
+        self.blocking_flush()
+    }
+}
+
+impl embedded_io::Read for Lpuart<'_, Blocking> {
+    fn read(&mut self, buf: &mut [u8]) -> core::result::Result<usize, Self::Error> {
+        embedded_io::Read::read(&mut self.rx, buf)
+    }
+}
+
+impl embedded_io::Write for Lpuart<'_, Blocking> {
+    fn write(&mut self, buf: &[u8]) -> core::result::Result<usize, Self::Error> {
+        embedded_io::Write::write(&mut self.tx, buf)
+    }
+
+    fn flush(&mut self) -> core::result::Result<(), Self::Error> {
+        embedded_io::Write::flush(&mut self.tx)
+    }
+}
diff --git a/src/main.rs b/src/main.rs
deleted file mode 100644
index 7111536ff..000000000
--- a/src/main.rs
+++ /dev/null
@@ -1,18 +0,0 @@
-#![cfg_attr(target_os = "none", no_std)]
-#![cfg_attr(target_os = "none", no_main)]
-
-#[cfg(target_os = "none")]
-mod baremetal;
-
-#[cfg(not(target_os = "none"))]
-fn main() {
-    println!("Hello, world!");
-}
-
-#[cfg(test)]
-mod tests {
-    #[test]
-    fn it_works() {
-        assert_eq!(2 + 2, 4);
-    }
-}
diff --git a/src/ostimer.rs b/src/ostimer.rs
new file mode 100644
index 000000000..a4cab6970
--- /dev/null
+++ b/src/ostimer.rs
@@ -0,0 +1,678 @@
+//! # OSTIMER Driver with Robustness Features
+//!
+//! This module provides an async timer driver for the NXP MCXA276 OSTIMER peripheral
+//! with protection against race conditions and timer rollover issues.
+//!
+//! ## Features
+//!
+//! - Async timing with embassy-time integration
+//! - Gray code counter handling (42-bit counter)
+//! - Interrupt-driven wakeups
+//! - Configurable interrupt priority
+//! - **Race condition protection**: Critical sections and atomic operations
+//! - **Timer rollover handling**: Bounds checking and rollover prevention
+//!
+//! ## Clock Frequency Configuration
+//!
+//! The OSTIMER frequency depends on your system's clock configuration. You must provide
+//! the actual frequency when calling `time_driver::init()`.
+//!
+//! ## Race Condition Protection
+//! - Critical sections in interrupt handlers prevent concurrent access
+//! - Atomic register operations with memory barriers
+//! - Proper interrupt flag clearing and validation
+//!
+//! ## Timer Rollover Handling
+//! - Bounds checking prevents scheduling beyond timer capacity
+//! - Immediate wake for timestamps that would cause rollover issues
+#![allow(dead_code)]
+
+use core::sync::atomic::{AtomicBool, Ordering};
+
+use crate::interrupt::InterruptExt;
+use crate::pac;
+
+// PAC defines the shared RegisterBlock under `ostimer0`.
+type Regs = pac::ostimer0::RegisterBlock;
+
+// OSTIMER EVTIMER register layout constants
+/// Total width of the EVTIMER counter in bits (42 bits total)
+const EVTIMER_TOTAL_BITS: u32 = 42;
+/// Width of the low part of EVTIMER (bits 31:0)
+const EVTIMER_LO_BITS: u32 = 32;
+/// Width of the high part of EVTIMER (bits 41:32)
+const EVTIMER_HI_BITS: u32 = 10;
+/// Bit position where high part starts in the combined 64-bit value
+const EVTIMER_HI_SHIFT: u32 = 32;
+
+/// Bit mask for the high part of EVTIMER
+const EVTIMER_HI_MASK: u16 = (1 << EVTIMER_HI_BITS) - 1;
+
+/// Maximum value for MATCH_L register (32-bit)
+const MATCH_L_MAX: u32 = u32::MAX;
+/// Maximum value for MATCH_H register (10-bit)
+const MATCH_H_MAX: u16 = EVTIMER_HI_MASK;
+
+/// Bit mask for extracting the low 32 bits from a 64-bit value
+const LOW_32_BIT_MASK: u64 = u32::MAX as u64;
+
+/// Gray code conversion bit shifts (most significant to least)
+const GRAY_CONVERSION_SHIFTS: [u32; 6] = [32, 16, 8, 4, 2, 1];
+
+/// Maximum timer value before rollover (2^42 - 1 ticks)
+/// Actual rollover time depends on the configured clock frequency
+const TIMER_MAX_VALUE: u64 = (1u64 << EVTIMER_TOTAL_BITS) - 1;
+
+/// Threshold for detecting timer rollover in comparisons (1 second at 1MHz)
+const TIMER_ROLLOVER_THRESHOLD: u64 = 1_000_000;
+
+/// Common default interrupt priority for OSTIMER
+const DEFAULT_INTERRUPT_PRIORITY: u8 = 3;
+
+// Global alarm state for interrupt handling
+static ALARM_ACTIVE: AtomicBool = AtomicBool::new(false);
+static mut ALARM_CALLBACK: Option<fn()> = None;
+static mut ALARM_FLAG: Option<*const AtomicBool> = None;
+static mut ALARM_TARGET_TIME: u64 = 0;
+
+/// Number of tight spin iterations between elapsed time checks while waiting for MATCH writes to return to the idle (0) state.
+const MATCH_WRITE_READY_SPINS: usize = 512;
+/// Maximum time (in OSTIMER ticks) to wait for MATCH registers to become writable (~5 ms at 1 MHz).
+const MATCH_WRITE_READY_TIMEOUT_TICKS: u64 = 5_000;
+/// Short stabilization delay executed after toggling the MRCC reset line to let the OSTIMER bus interface settle.
+const RESET_STABILIZE_SPINS: usize = 512;
+
+pub(super) fn wait_for_match_write_ready(r: &Regs) -> bool {
+    let start = now_ticks_read();
+    let mut spin_budget = 0usize;
+
+    loop {
+        if r.osevent_ctrl().read().match_wr_rdy().bit_is_clear() {
+            return true;
+        }
+
+        cortex_m::asm::nop();
+        spin_budget += 1;
+
+        if spin_budget >= MATCH_WRITE_READY_SPINS {
+            spin_budget = 0;
+
+            let elapsed = now_ticks_read().wrapping_sub(start);
+            if elapsed >= MATCH_WRITE_READY_TIMEOUT_TICKS {
+                return false;
+            }
+        }
+    }
+}
+
+pub(super) fn wait_for_match_write_complete(r: &Regs) -> bool {
+    let start = now_ticks_read();
+    let mut spin_budget = 0usize;
+
+    loop {
+        if r.osevent_ctrl().read().match_wr_rdy().bit_is_clear() {
+            return true;
+        }
+
+        cortex_m::asm::nop();
+        spin_budget += 1;
+
+        if spin_budget >= MATCH_WRITE_READY_SPINS {
+            spin_budget = 0;
+
+            let elapsed = now_ticks_read().wrapping_sub(start);
+            if elapsed >= MATCH_WRITE_READY_TIMEOUT_TICKS {
+                return false;
+            }
+        }
+    }
+}
+
+fn prime_match_registers(r: &Regs) {
+    // Disable the interrupt, clear any pending flag, then wait until the MATCH registers are writable.
+    r.osevent_ctrl()
+        .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit());
+
+    if wait_for_match_write_ready(r) {
+        r.match_l().write(|w| unsafe { w.match_value().bits(MATCH_L_MAX) });
+        r.match_h().write(|w| unsafe { w.match_value().bits(MATCH_H_MAX) });
+        let _ = wait_for_match_write_complete(r);
+    }
+}
+
+/// Single-shot alarm functionality for OSTIMER
+pub struct Alarm<'d> {
+    /// Whether the alarm is currently active
+    active: AtomicBool,
+    /// Callback to execute when alarm expires (optional)
+    callback: Option<fn()>,
+    /// Flag that gets set when alarm expires (optional)
+    flag: Option<&'d AtomicBool>,
+    _phantom: core::marker::PhantomData<&'d mut ()>,
+}
+
+impl<'d> Alarm<'d> {
+    /// Create a new alarm instance
+    pub fn new() -> Self {
+        Self {
+            active: AtomicBool::new(false),
+            callback: None,
+            flag: None,
+            _phantom: core::marker::PhantomData,
+        }
+    }
+
+    /// Set a callback that will be executed when the alarm expires
+    /// Note: Due to interrupt handler constraints, callbacks must be static function pointers
+    pub fn with_callback(mut self, callback: fn()) -> Self {
+        self.callback = Some(callback);
+        self
+    }
+
+    /// Set a flag that will be set to true when the alarm expires
+    pub fn with_flag(mut self, flag: &'d AtomicBool) -> Self {
+        self.flag = Some(flag);
+        self
+    }
+
+    /// Check if the alarm is currently active
+    pub fn is_active(&self) -> bool {
+        self.active.load(Ordering::Acquire)
+    }
+
+    /// Cancel the alarm if it's active
+    pub fn cancel(&self) {
+        self.active.store(false, Ordering::Release);
+    }
+}
+
+/// Configuration for Ostimer::new()
+#[derive(Copy, Clone)]
+pub struct Config {
+    /// Initialize MATCH registers to their max values and mask/clear the interrupt flag.
+    pub init_match_max: bool,
+    /// OSTIMER clock frequency in Hz (must match the actual hardware clock)
+    pub clock_frequency_hz: u64,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            init_match_max: true,
+            // Default to 1MHz - user should override this with actual frequency
+            clock_frequency_hz: 1_000_000,
+        }
+    }
+}
+
+/// OSTIMER peripheral instance
+pub struct Ostimer<'d, I: Instance> {
+    _inst: core::marker::PhantomData<I>,
+    clock_frequency_hz: u64,
+    _phantom: core::marker::PhantomData<&'d mut ()>,
+}
+
+impl<'d, I: Instance> Ostimer<'d, I> {
+    /// Construct OSTIMER handle.
+    /// Requires clocks for the instance to be enabled by the board before calling.
+    /// Does not enable NVIC or INTENA; use time_driver::init() for async operation.
+    pub fn new(_inst: impl Instance, cfg: Config, _p: &'d crate::pac::Peripherals) -> Self {
+        assert!(cfg.clock_frequency_hz > 0, "OSTIMER frequency must be greater than 0");
+
+        if cfg.init_match_max {
+            let r: &Regs = unsafe { &*I::ptr() };
+            // Mask INTENA, clear pending flag, and set MATCH to max so no spurious IRQ fires.
+            prime_match_registers(r);
+        }
+
+        Self {
+            _inst: core::marker::PhantomData,
+            clock_frequency_hz: cfg.clock_frequency_hz,
+            _phantom: core::marker::PhantomData,
+        }
+    }
+
+    /// Get the configured clock frequency in Hz
+    pub fn clock_frequency_hz(&self) -> u64 {
+        self.clock_frequency_hz
+    }
+
+    /// Read the current timer counter value in timer ticks
+    ///
+    /// # Returns
+    /// Current timer counter value as a 64-bit unsigned integer
+    pub fn now(&self) -> u64 {
+        now_ticks_read()
+    }
+
+    /// Reset the timer counter to zero
+    ///
+    /// This performs a hardware reset of the OSTIMER peripheral, which will reset
+    /// the counter to zero and clear any pending interrupts. Note that this will
+    /// affect all timer operations including embassy-time.
+    ///
+    /// # Safety
+    /// This operation will reset the entire OSTIMER peripheral. Any active alarms
+    /// or time_driver operations will be disrupted. Use with caution.
+    pub fn reset(&self, peripherals: &crate::pac::Peripherals) {
+        critical_section::with(|_| {
+            let r: &Regs = unsafe { &*I::ptr() };
+
+            // Mask the peripheral interrupt flag before we toggle the reset line so that
+            // no new NVIC activity races with the reset sequence.
+            r.osevent_ctrl()
+                .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit());
+
+            unsafe {
+                crate::reset::assert::<crate::reset::line::Ostimer0>(peripherals);
+            }
+
+            for _ in 0..RESET_STABILIZE_SPINS {
+                cortex_m::asm::nop();
+            }
+
+            unsafe {
+                crate::reset::release::<crate::reset::line::Ostimer0>(peripherals);
+            }
+
+            while !<crate::reset::line::Ostimer0 as crate::reset::ResetLine>::is_released(&peripherals.mrcc0) {
+                cortex_m::asm::nop();
+            }
+
+            for _ in 0..RESET_STABILIZE_SPINS {
+                cortex_m::asm::nop();
+            }
+
+            // Clear alarm bookkeeping before re-arming MATCH registers.
+            ALARM_ACTIVE.store(false, Ordering::Release);
+            unsafe {
+                ALARM_TARGET_TIME = 0;
+                ALARM_CALLBACK = None;
+                ALARM_FLAG = None;
+            }
+
+            prime_match_registers(r);
+        });
+
+        // Ensure no stale OS_EVENT request remains pending after the reset sequence.
+        crate::interrupt::OS_EVENT.unpend();
+    }
+
+    /// Schedule a single-shot alarm to expire after the specified delay in microseconds
+    ///
+    /// # Parameters
+    /// * `alarm` - The alarm instance to schedule
+    /// * `delay_us` - Delay in microseconds from now
+    ///
+    /// # Returns
+    /// `true` if the alarm was scheduled successfully, `false` if it would exceed timer capacity
+    pub fn schedule_alarm_delay(&self, alarm: &Alarm, delay_us: u64) -> bool {
+        let delay_ticks = (delay_us * self.clock_frequency_hz) / 1_000_000;
+        let target_time = now_ticks_read() + delay_ticks;
+        self.schedule_alarm_at(alarm, target_time)
+    }
+
+    /// Schedule a single-shot alarm to expire at the specified absolute time in timer ticks
+    ///
+    /// # Parameters
+    /// * `alarm` - The alarm instance to schedule
+    /// * `target_ticks` - Absolute time in timer ticks when the alarm should expire
+    ///
+    /// # Returns
+    /// `true` if the alarm was scheduled successfully, `false` if it would exceed timer capacity
+    pub fn schedule_alarm_at(&self, alarm: &Alarm, target_ticks: u64) -> bool {
+        let now = now_ticks_read();
+
+        // Check if target time is in the past
+        if target_ticks <= now {
+            // Execute callback immediately if alarm was supposed to be active
+            if alarm.active.load(Ordering::Acquire) {
+                alarm.active.store(false, Ordering::Release);
+                if let Some(callback) = alarm.callback {
+                    callback();
+                }
+                if let Some(flag) = &alarm.flag {
+                    flag.store(true, Ordering::Release);
+                }
+            }
+            return true;
+        }
+
+        // Check for timer rollover
+        let max_future = now + TIMER_MAX_VALUE;
+        if target_ticks > max_future {
+            return false; // Would exceed timer capacity
+        }
+
+        // Program the timer
+        let r: &Regs = unsafe { &*I::ptr() };
+
+        critical_section::with(|_| {
+            // Disable interrupt and clear flag
+            r.osevent_ctrl()
+                .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit());
+
+            if !wait_for_match_write_ready(r) {
+                prime_match_registers(r);
+
+                if !wait_for_match_write_ready(r) {
+                    alarm.active.store(false, Ordering::Release);
+                    ALARM_ACTIVE.store(false, Ordering::Release);
+                    unsafe {
+                        ALARM_TARGET_TIME = 0;
+                        ALARM_CALLBACK = None;
+                        ALARM_FLAG = None;
+                    }
+                    return false;
+                }
+            }
+
+            // Mark alarm as active now that we know the MATCH registers are writable
+            alarm.active.store(true, Ordering::Release);
+
+            // Set global alarm state for interrupt handler
+            ALARM_ACTIVE.store(true, Ordering::Release);
+            unsafe {
+                ALARM_TARGET_TIME = target_ticks;
+                ALARM_CALLBACK = alarm.callback;
+                ALARM_FLAG = alarm.flag.map(|f| f as *const AtomicBool);
+            }
+
+            // Program MATCH registers (Gray-coded)
+            let gray = bin_to_gray(target_ticks);
+            let l = (gray & LOW_32_BIT_MASK) as u32;
+            let h = (((gray >> EVTIMER_HI_SHIFT) as u16) & EVTIMER_HI_MASK) as u16;
+
+            r.match_l().write(|w| unsafe { w.match_value().bits(l) });
+            r.match_h().write(|w| unsafe { w.match_value().bits(h) });
+
+            if !wait_for_match_write_complete(r) {
+                alarm.active.store(false, Ordering::Release);
+                ALARM_ACTIVE.store(false, Ordering::Release);
+                unsafe {
+                    ALARM_TARGET_TIME = 0;
+                    ALARM_CALLBACK = None;
+                    ALARM_FLAG = None;
+                }
+                return false;
+            }
+
+            let now_after_program = now_ticks_read();
+            let intrflag_set = r.osevent_ctrl().read().ostimer_intrflag().bit_is_set();
+            if now_after_program >= target_ticks && !intrflag_set {
+                alarm.active.store(false, Ordering::Release);
+                ALARM_ACTIVE.store(false, Ordering::Release);
+                unsafe {
+                    ALARM_TARGET_TIME = 0;
+                    ALARM_CALLBACK = None;
+                    ALARM_FLAG = None;
+                }
+                return false;
+            }
+
+            // Enable interrupt
+            r.osevent_ctrl().write(|w| w.ostimer_intena().set_bit());
+
+            true
+        })
+    }
+
+    /// Cancel any active alarm
+    pub fn cancel_alarm(&self, alarm: &Alarm) {
+        critical_section::with(|_| {
+            alarm.cancel();
+
+            // Clear global alarm state
+            ALARM_ACTIVE.store(false, Ordering::Release);
+            unsafe { ALARM_TARGET_TIME = 0 };
+
+            // Reset MATCH registers to maximum values to prevent spurious interrupts
+            let r: &Regs = unsafe { &*I::ptr() };
+            prime_match_registers(r);
+        });
+    }
+
+    /// Check if an alarm has expired (call this from your interrupt handler)
+    /// Returns true if the alarm was active and has now expired
+    pub fn check_alarm_expired(&self, alarm: &Alarm) -> bool {
+        if alarm.active.load(Ordering::Acquire) {
+            alarm.active.store(false, Ordering::Release);
+
+            // Execute callback
+            if let Some(callback) = alarm.callback {
+                callback();
+            }
+
+            // Set flag
+            if let Some(flag) = &alarm.flag {
+                flag.store(true, Ordering::Release);
+            }
+
+            true
+        } else {
+            false
+        }
+    }
+}
+
+/// Read current EVTIMER (Gray-coded) and convert to binary ticks.
+#[inline(always)]
+fn now_ticks_read() -> u64 {
+    let r: &Regs = unsafe { &*pac::Ostimer0::ptr() };
+
+    // Read high then low to minimize incoherent snapshots
+    let hi = (r.evtimerh().read().evtimer_count_value().bits() as u64) & (EVTIMER_HI_MASK as u64);
+    let lo = r.evtimerl().read().evtimer_count_value().bits() as u64;
+
+    // Combine and convert from Gray code to binary
+    let gray = lo | (hi << EVTIMER_HI_SHIFT);
+    gray_to_bin(gray)
+}
+
+// Instance trait like other drivers, providing a PAC pointer for this OSTIMER instance
+pub trait Instance {
+    fn ptr() -> *const Regs;
+}
+
+// Token for OSTIMER0 provided by embassy-hal-internal peripherals macro.
+pub type Ostimer0 = crate::peripherals::OSTIMER0;
+
+impl Instance for crate::peripherals::OSTIMER0 {
+    #[inline(always)]
+    fn ptr() -> *const Regs {
+        pac::Ostimer0::ptr()
+    }
+}
+
+// Also implement Instance for the Peri wrapper type
+impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::OSTIMER0> {
+    #[inline(always)]
+    fn ptr() -> *const Regs {
+        pac::Ostimer0::ptr()
+    }
+}
+
+#[inline(always)]
+fn bin_to_gray(x: u64) -> u64 {
+    x ^ (x >> 1)
+}
+
+#[inline(always)]
+fn gray_to_bin(gray: u64) -> u64 {
+    // More efficient iterative conversion using predefined shifts
+    let mut bin = gray;
+    for &shift in &GRAY_CONVERSION_SHIFTS {
+        bin ^= bin >> shift;
+    }
+    bin
+}
+
+pub mod time_driver {
+    use core::sync::atomic::Ordering;
+    use core::task::Waker;
+
+    use embassy_sync::waitqueue::AtomicWaker;
+    use embassy_time_driver as etd;
+
+    use super::{
+        bin_to_gray, now_ticks_read, Regs, ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME,
+        EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, LOW_32_BIT_MASK,
+    };
+    use crate::pac;
+    pub struct Driver;
+    static TIMER_WAKER: AtomicWaker = AtomicWaker::new();
+
+    impl etd::Driver for Driver {
+        fn now(&self) -> u64 {
+            // Use the hardware counter (frequency configured in init)
+            super::now_ticks_read()
+        }
+
+        fn schedule_wake(&self, timestamp: u64, waker: &Waker) {
+            let now = self.now();
+
+            // If timestamp is in the past or very close to now, wake immediately
+            if timestamp <= now {
+                waker.wake_by_ref();
+                return;
+            }
+
+            // Prevent scheduling too far in the future (beyond timer rollover)
+            // This prevents wraparound issues
+            let max_future = now + super::TIMER_MAX_VALUE;
+            if timestamp > max_future {
+                // For very long timeouts, wake immediately to avoid rollover issues
+                waker.wake_by_ref();
+                return;
+            }
+
+            // Register the waker first so any immediate wake below is observed by the executor.
+            TIMER_WAKER.register(waker);
+
+            let r: &Regs = unsafe { &*pac::Ostimer0::ptr() };
+
+            critical_section::with(|_| {
+                // Mask INTENA and clear flag
+                r.osevent_ctrl()
+                    .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit());
+
+                // Read back to ensure W1C took effect on hardware
+                let _ = r.osevent_ctrl().read().ostimer_intrflag().bit();
+
+                if !super::wait_for_match_write_ready(r) {
+                    super::prime_match_registers(r);
+
+                    if !super::wait_for_match_write_ready(r) {
+                        // If we can't safely program MATCH, wake immediately and leave INTENA masked.
+                        waker.wake_by_ref();
+                        return;
+                    }
+                }
+
+                // Program MATCH (Gray-coded). Write low then high, then fence.
+                let gray = bin_to_gray(timestamp);
+                let l = (gray & LOW_32_BIT_MASK) as u32;
+
+                let h = (((gray >> EVTIMER_HI_SHIFT) as u16) & EVTIMER_HI_MASK) as u16;
+
+                r.match_l().write(|w| unsafe { w.match_value().bits(l) });
+                r.match_h().write(|w| unsafe { w.match_value().bits(h) });
+
+                if !super::wait_for_match_write_complete(r) {
+                    waker.wake_by_ref();
+                    return;
+                }
+
+                let now_after_program = super::now_ticks_read();
+                let intrflag_set = r.osevent_ctrl().read().ostimer_intrflag().bit_is_set();
+                if now_after_program >= timestamp && !intrflag_set {
+                    waker.wake_by_ref();
+                    return;
+                }
+
+                // Enable peripheral interrupt
+                r.osevent_ctrl().write(|w| w.ostimer_intena().set_bit());
+            });
+        }
+    }
+
+    /// Install the global embassy-time driver and configure NVIC priority for OS_EVENT.
+    ///
+    /// # Parameters
+    /// * `priority` - Interrupt priority for the OSTIMER interrupt
+    /// * `frequency_hz` - Actual OSTIMER clock frequency in Hz (stored for future use)
+    ///
+    /// Note: The frequency parameter is currently accepted for API compatibility.
+    /// The embassy_time_driver macro handles driver registration automatically.
+    pub fn init(priority: crate::interrupt::Priority, frequency_hz: u64) {
+        // Mask/clear at peripheral and set default MATCH
+        let r: &Regs = unsafe { &*pac::Ostimer0::ptr() };
+        super::prime_match_registers(r);
+
+        // Configure NVIC for timer operation
+        crate::interrupt::OS_EVENT.configure_for_timer(priority);
+
+        // Note: The embassy_time_driver macro automatically registers the driver
+        // The frequency parameter is accepted for future compatibility
+        let _ = frequency_hz; // Suppress unused parameter warning
+    }
+
+    // Export the global time driver expected by embassy-time
+    embassy_time_driver::time_driver_impl!(static DRIVER: Driver = Driver);
+
+    /// To be called from the OS_EVENT IRQ.
+    pub fn on_interrupt() {
+        let r: &Regs = unsafe { &*pac::Ostimer0::ptr() };
+
+        // Critical section to prevent races with schedule_wake
+        critical_section::with(|_| {
+            // Check if interrupt is actually pending and handle it atomically
+            if r.osevent_ctrl().read().ostimer_intrflag().bit_is_set() {
+                // Clear flag and disable interrupt atomically
+                r.osevent_ctrl().write(|w| {
+                    w.ostimer_intrflag()
+                        .clear_bit_by_one() // Write-1-to-clear using safe helper
+                        .ostimer_intena()
+                        .clear_bit()
+                });
+
+                // Wake the waiting task
+                TIMER_WAKER.wake();
+
+                // Handle alarm callback if active and this interrupt is for the alarm
+                if ALARM_ACTIVE.load(Ordering::SeqCst) {
+                    let current_time = now_ticks_read();
+                    let target_time = unsafe { ALARM_TARGET_TIME };
+
+                    // Check if current time is close to alarm target time (within 1000 ticks for timing variations)
+                    if current_time >= target_time && current_time <= target_time + 1000 {
+                        ALARM_ACTIVE.store(false, Ordering::SeqCst);
+                        unsafe { ALARM_TARGET_TIME = 0 };
+
+                        // Execute callback if set
+                        unsafe {
+                            if let Some(callback) = ALARM_CALLBACK {
+                                callback();
+                            }
+                        }
+
+                        // Set flag if provided
+                        unsafe {
+                            if let Some(flag) = ALARM_FLAG {
+                                (*flag).store(true, Ordering::SeqCst);
+                            }
+                        }
+                    }
+                }
+            }
+        });
+    }
+
+    /// Type-level handler to be used with bind_interrupts! for OS_EVENT.
+    pub struct OsEventHandler;
+    impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::OS_EVENT> for OsEventHandler {
+        unsafe fn on_interrupt() {
+            on_interrupt();
+        }
+    }
+}
diff --git a/src/pins.rs b/src/pins.rs
new file mode 100644
index 000000000..f802568f3
--- /dev/null
+++ b/src/pins.rs
@@ -0,0 +1,123 @@
+//! Pin configuration helpers (separate from peripheral drivers).
+use crate::pac;
+
+pub unsafe fn configure_uart2_pins_port2() {
+    // P2_2 = LPUART2_TX ALT3, P2_3 = LPUART2_RX ALT3 with pull-up, input enable, high drive, slow slew.
+    let port2 = &*pac::Port2::ptr();
+    port2.pcr2().write(|w| {
+        w.ps()
+            .ps1()
+            .pe()
+            .pe1()
+            .sre()
+            .sre1()
+            .dse()
+            .dse1()
+            .mux()
+            .mux11()
+            .ibe()
+            .ibe1()
+    });
+    port2.pcr3().write(|w| {
+        w.ps()
+            .ps1()
+            .pe()
+            .pe1()
+            .sre()
+            .sre1()
+            .dse()
+            .dse1()
+            .mux()
+            .mux11()
+            .ibe()
+            .ibe1()
+    });
+    core::arch::asm!("dsb sy; isb sy");
+}
+
+pub unsafe fn configure_adc_pins() {
+    // P1_10 = ADC1_A8
+    let port1 = &*pac::Port1::ptr();
+    port1.pcr10().write(|w| {
+        w.ps()
+            .ps0()
+            .pe()
+            .pe0()
+            .sre()
+            .sre0()
+            .ode()
+            .ode0()
+            .dse()
+            .dse0()
+            .mux()
+            .mux00()
+            .ibe()
+            .ibe0()
+            .inv()
+            .inv0()
+            .lk()
+            .lk0()
+    });
+    core::arch::asm!("dsb sy; isb sy");
+}
+
+/// Configure a pin for a specific mux alternative.
+///
+/// # Arguments
+/// * `port` - Port number (0-4)
+/// * `pin` - Pin number (varies by port: PORT0=0-7, PORT1=0-19, PORT2=0-26, PORT3=0-31, PORT4=0-7)
+/// * `mux` - Mux alternative (0-15, where 0 = GPIO, 1-15 = other functions)
+pub unsafe fn set_pin_mux(port: u8, pin: u8, mux: u8) {
+    // Validate mux value (0-15)
+    if mux > 15 {
+        panic!("Invalid mux value: {}, must be 0-15", mux);
+    }
+
+    // Validate pin number based on port
+    let max_pin = match port {
+        0 => 7,  // PORT0: pins 0-7
+        1 => 19, // PORT1: pins 0-19
+        2 => 26, // PORT2: pins 0-26
+        3 => 31, // PORT3: pins 0-31
+        4 => 7,  // PORT4: pins 0-7
+        _ => panic!("Unsupported GPIO port: {}", port),
+    };
+
+    if pin > max_pin {
+        panic!("Invalid pin {} for PORT{}, max pin is {}", pin, port, max_pin);
+    }
+
+    // Get the base address for the port
+    let port_base: *mut u32 = match port {
+        0 => pac::Port0::ptr() as *mut u32,
+        1 => pac::Port1::ptr() as *mut u32,
+        2 => pac::Port2::ptr() as *mut u32,
+        3 => pac::Port3::ptr() as *mut u32,
+        4 => pac::Port4::ptr() as *mut u32,
+        _ => panic!("Unsupported GPIO port: {}", port),
+    };
+
+    // PCR registers are 4 bytes apart, starting at offset 0 for PCR0
+    let pcr_addr = port_base.add(pin as usize);
+
+    // Read current PCR value
+    let current_val = pcr_addr.read_volatile();
+
+    // Clear mux bits (bits 8-11) and set new mux value
+    let new_val = (current_val & !(0xF << 8)) | ((mux as u32) << 8);
+
+    // Write back the new value
+    pcr_addr.write_volatile(new_val);
+
+    core::arch::asm!("dsb sy; isb sy");
+}
+
+/// Configure a pin for GPIO mode (ALT0).
+/// This is a convenience function that calls set_pin_mux with mux=0.
+///
+/// # Arguments
+/// * `port` - Port number (0-4)
+/// * `pin` - Pin number (varies by port: PORT0=0-7, PORT1=0-19, PORT2=0-26, PORT3=0-31, PORT4=0-7)
+pub unsafe fn set_pin_mux_gpio(port: u8, pin: u8) {
+    set_pin_mux(port, pin, 0);
+}
diff --git a/src/reset.rs b/src/reset.rs
new file mode 100644
index 000000000..1c131d1cc
--- /dev/null
+++ b/src/reset.rs
@@ -0,0 +1,112 @@
+//! Reset control helpers built on PAC field writers.
+use crate::pac;
+
+/// Trait describing a reset line that can be asserted/deasserted.
+pub trait ResetLine {
+    /// Drive the peripheral out of reset.
+    unsafe fn release(mrcc: &pac::mrcc0::RegisterBlock);
+
+    /// Drive the peripheral into reset.
+    unsafe fn assert(mrcc: &pac::mrcc0::RegisterBlock);
+
+    /// Check whether the peripheral is currently released.
+    fn is_released(mrcc: &pac::mrcc0::RegisterBlock) -> bool;
+}
+
+/// Release a reset line for the given peripheral set.
+#[inline]
+pub unsafe fn release<R: ResetLine>(peripherals: &pac::Peripherals) {
+    R::release(&peripherals.mrcc0);
+}
+
+/// Assert a reset line for the given peripheral set.
+#[inline]
+pub unsafe fn assert<R: ResetLine>(peripherals: &pac::Peripherals) {
+    R::assert(&peripherals.mrcc0);
+}
+
+/// Pulse a reset line (assert then release) with a short delay.
+#[inline]
+pub unsafe fn pulse<R: ResetLine>(peripherals: &pac::Peripherals) {
+    let mrcc = &peripherals.mrcc0;
+    R::assert(mrcc);
+    cortex_m::asm::nop();
+    cortex_m::asm::nop();
+    R::release(mrcc);
+}
+
+macro_rules! impl_reset_line {
+    ($name:ident, $reg:ident, $field:ident) => {
+        pub struct $name;
+
+        impl ResetLine for $name {
+            #[inline]
+            unsafe fn release(mrcc: &pac::mrcc0::RegisterBlock) {
+                mrcc.$reg().modify(|_, w| w.$field().enabled());
+            }
+
+            #[inline]
+            unsafe fn assert(mrcc: &pac::mrcc0::RegisterBlock) {
+                mrcc.$reg().modify(|_, w| w.$field().disabled());
+            }
+
+            #[inline]
+            fn is_released(mrcc: &pac::mrcc0::RegisterBlock) -> bool {
+                mrcc.$reg().read().$field().is_enabled()
+            }
+        }
+    };
+}
+
+pub mod line {
+    use super::*;
+
+    impl_reset_line!(Port2, mrcc_glb_rst1, port2);
+    impl_reset_line!(Port3, mrcc_glb_rst1, port3);
+    impl_reset_line!(Gpio3, mrcc_glb_rst2, gpio3);
+    impl_reset_line!(Lpuart2, mrcc_glb_rst0, lpuart2);
+    impl_reset_line!(Ostimer0, mrcc_glb_rst1, ostimer0);
+    impl_reset_line!(Port1, mrcc_glb_rst1, port1);
+    impl_reset_line!(Adc1, mrcc_glb_rst1, adc1);
+}
+
+#[inline]
+pub unsafe fn release_reset_port2(peripherals: &pac::Peripherals) {
+    release::<line::Port2>(peripherals);
+}
+
+#[inline]
+pub unsafe fn release_reset_port3(peripherals: &pac::Peripherals) {
+    release::<line::Port3>(peripherals);
+}
+
+#[inline]
+pub unsafe fn release_reset_gpio3(peripherals: &pac::Peripherals) {
+    release::<line::Gpio3>(peripherals);
+}
+
+#[inline]
+pub unsafe fn release_reset_lpuart2(peripherals: &pac::Peripherals) {
+    release::<line::Lpuart2>(peripherals);
+}
+
+#[inline]
+pub unsafe fn release_reset_ostimer0(peripherals: &pac::Peripherals) {
+    release::<line::Ostimer0>(peripherals);
+}
+
+/// Convenience shim retained for existing call sites.
+#[inline]
+pub unsafe fn reset_ostimer0(peripherals: &pac::Peripherals) {
+    pulse::<line::Ostimer0>(peripherals);
+}
+
+#[inline]
+pub unsafe fn release_reset_port1(peripherals: &pac::Peripherals) {
+    release::<line::Port1>(peripherals);
+}
+
+#[inline]
+pub unsafe fn release_reset_adc1(peripherals: &pac::Peripherals) {
+    release::<line::Adc1>(peripherals);
+}
diff --git a/src/rtc.rs b/src/rtc.rs
new file mode 100644
index 000000000..d62da1f0a
--- /dev/null
+++ b/src/rtc.rs
@@ -0,0 +1,284 @@
+//! RTC DateTime driver.
+use core::sync::atomic::{AtomicBool, Ordering};
+
+use crate::pac;
+use crate::pac::rtc0::cr::Um;
+
+type Regs = pac::rtc0::RegisterBlock;
+
+static ALARM_TRIGGERED: AtomicBool = AtomicBool::new(false);
+
+// Token-based instance pattern like embassy-imxrt
+pub trait Instance {
+    fn ptr() -> *const Regs;
+}
+
+/// Token for RTC0
+pub type Rtc0 = crate::peripherals::RTC0;
+impl Instance for crate::peripherals::RTC0 {
+    #[inline(always)]
+    fn ptr() -> *const Regs {
+        pac::Rtc0::ptr()
+    }
+}
+
+// Also implement Instance for the Peri wrapper type
+impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::RTC0> {
+    #[inline(always)]
+    fn ptr() -> *const Regs {
+        pac::Rtc0::ptr()
+    }
+}
+
+const DAYS_IN_A_YEAR: u32 = 365;
+const SECONDS_IN_A_DAY: u32 = 86400;
+const SECONDS_IN_A_HOUR: u32 = 3600;
+const SECONDS_IN_A_MINUTE: u32 = 60;
+const YEAR_RANGE_START: u16 = 1970;
+
+#[derive(Debug, Clone, Copy)]
+pub struct RtcDateTime {
+    pub year: u16,
+    pub month: u8,
+    pub day: u8,
+    pub hour: u8,
+    pub minute: u8,
+    pub second: u8,
+}
+#[derive(Copy, Clone)]
+pub struct RtcConfig {
+    #[allow(dead_code)]
+    wakeup_select: bool,
+    update_mode: Um,
+    #[allow(dead_code)]
+    supervisor_access: bool,
+    compensation_interval: u8,
+    compensation_time: u8,
+}
+
+#[derive(Copy, Clone)]
+pub struct RtcInterruptEnable;
+impl RtcInterruptEnable {
+    pub const RTC_TIME_INVALID_INTERRUPT_ENABLE: u32 = 1 << 0;
+    pub const RTC_TIME_OVERFLOW_INTERRUPT_ENABLE: u32 = 1 << 1;
+    pub const RTC_ALARM_INTERRUPT_ENABLE: u32 = 1 << 2;
+    pub const RTC_SECONDS_INTERRUPT_ENABLE: u32 = 1 << 4;
+}
+
+pub fn convert_datetime_to_seconds(datetime: &RtcDateTime) -> u32 {
+    let month_days: [u16; 13] = [0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334];
+
+    let mut seconds = (datetime.year as u32 - 1970) * DAYS_IN_A_YEAR;
+    seconds += (datetime.year as u32 / 4) - (1970 / 4);
+    seconds += month_days[datetime.month as usize] as u32;
+    seconds += datetime.day as u32 - 1;
+
+    if (datetime.year & 3 == 0) && (datetime.month <= 2) {
+        seconds -= 1;
+    }
+
+    seconds = seconds * SECONDS_IN_A_DAY
+        + (datetime.hour as u32 * SECONDS_IN_A_HOUR)
+        + (datetime.minute as u32 * SECONDS_IN_A_MINUTE)
+        + datetime.second as u32;
+
+    seconds
+}
+
+pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime {
+    let mut seconds_remaining = seconds;
+    let mut days = seconds_remaining / SECONDS_IN_A_DAY + 1;
+    seconds_remaining %= SECONDS_IN_A_DAY;
+
+    let hour = (seconds_remaining / SECONDS_IN_A_HOUR) as u8;
+    seconds_remaining %= SECONDS_IN_A_HOUR;
+    let minute = (seconds_remaining / SECONDS_IN_A_MINUTE) as u8;
+    let second = (seconds_remaining % SECONDS_IN_A_MINUTE) as u8;
+
+    let mut year = YEAR_RANGE_START;
+    let mut days_in_year = DAYS_IN_A_YEAR;
+
+    while days > days_in_year {
+        days -= days_in_year;
+        year += 1;
+
+        days_in_year = if year % 4 == 0 {
+            DAYS_IN_A_YEAR + 1
+        } else {
+            DAYS_IN_A_YEAR
+        };
+    }
+
+    let mut days_per_month = [0u8, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31];
+    if year % 4 == 0 {
+        days_per_month[2] = 29;
+    }
+
+    let mut month = 1;
+    for m in 1..=12 {
+        if days <= days_per_month[m] as u32 {
+            month = m;
+            break;
+        } else {
+            days -= days_per_month[m] as u32;
+        }
+    }
+
+    let day = days as u8;
+
+    RtcDateTime {
+        year,
+        month: month as u8,
+        day,
+        hour,
+        minute,
+        second,
+    }
+}
+
+pub fn get_default_config() -> RtcConfig {
+    RtcConfig {
+        wakeup_select: false,
+        update_mode: Um::Um0,
+        supervisor_access: false,
+        compensation_interval: 0,
+        compensation_time: 0,
+    }
+}
+/// Minimal RTC handle for a specific instance I (store the zero-sized token like embassy)
+pub struct Rtc<I: Instance> {
+    _inst: core::marker::PhantomData<I>,
+}
+
+impl<I: Instance> Rtc<I> {
+    /// initialize RTC
+    pub fn new(_inst: impl Instance, config: RtcConfig) -> Self {
+        let rtc = unsafe { &*I::ptr() };
+
+        /* RTC reset */
+        rtc.cr().modify(|_, w| w.swr().set_bit());
+        rtc.cr().modify(|_, w| w.swr().clear_bit());
+        rtc.tsr().write(|w| unsafe { w.bits(1) });
+
+        rtc.cr().modify(|_, w| w.um().variant(config.update_mode));
+
+        rtc.tcr().modify(|_, w| unsafe {
+            w.cir()
+                .bits(config.compensation_interval)
+                .tcr()
+                .bits(config.compensation_time)
+        });
+
+        Self {
+            _inst: core::marker::PhantomData,
+        }
+    }
+
+    pub fn set_datetime(&self, datetime: RtcDateTime) {
+        let rtc = unsafe { &*I::ptr() };
+        let seconds = convert_datetime_to_seconds(&datetime);
+        rtc.tsr().write(|w| unsafe { w.bits(seconds) });
+    }
+
+    pub fn get_datetime(&self) -> RtcDateTime {
+        let rtc = unsafe { &*I::ptr() };
+        let seconds = rtc.tsr().read().bits();
+        convert_seconds_to_datetime(seconds)
+    }
+
+    pub fn set_alarm(&self, alarm: RtcDateTime) {
+        let rtc = unsafe { &*I::ptr() };
+        let seconds = convert_datetime_to_seconds(&alarm);
+
+        rtc.tar().write(|w| unsafe { w.bits(0) });
+        let mut timeout = 10000;
+        while rtc.tar().read().bits() != 0 && timeout > 0 {
+            timeout -= 1;
+        }
+
+        rtc.tar().write(|w| unsafe { w.bits(seconds) });
+
+        let mut timeout = 10000;
+        while rtc.tar().read().bits() != seconds && timeout > 0 {
+            timeout -= 1;
+        }
+    }
+
+    pub fn get_alarm(&self) -> RtcDateTime {
+        let rtc = unsafe { &*I::ptr() };
+        let alarm_seconds = rtc.tar().read().bits();
+        convert_seconds_to_datetime(alarm_seconds)
+    }
+
+    pub fn start(&self) {
+        let rtc = unsafe { &*I::ptr() };
+        rtc.sr().modify(|_, w| w.tce().set_bit());
+    }
+
+    pub fn stop(&self) {
+        let rtc = unsafe { &*I::ptr() };
+        rtc.sr().modify(|_, w| w.tce().clear_bit());
+    }
+
+    pub fn set_interrupt(&self, mask: u32) {
+        let rtc = unsafe { &*I::ptr() };
+
+        if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.tiie().tiie_1());
+        }
+        if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.toie().toie_1());
+        }
+        if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.taie().taie_1());
+        }
+        if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.tsie().tsie_1());
+        }
+
+        ALARM_TRIGGERED.store(false, Ordering::SeqCst);
+    }
+
+    pub fn disable_interrupt(&self, mask: u32) {
+        let rtc = unsafe { &*I::ptr() };
+
+        if (RtcInterruptEnable::RTC_TIME_INVALID_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.tiie().tiie_0());
+        }
+        if (RtcInterruptEnable::RTC_TIME_OVERFLOW_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.toie().toie_0());
+        }
+        if (RtcInterruptEnable::RTC_ALARM_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.taie().taie_0());
+        }
+        if (RtcInterruptEnable::RTC_SECONDS_INTERRUPT_ENABLE & mask) != 0 {
+            rtc.ier().modify(|_, w| w.tsie().tsie_0());
+        }
+    }
+
+    pub fn clear_alarm_flag(&self) {
+        let rtc = unsafe { &*I::ptr() };
+        rtc.ier().modify(|_, w| w.taie().clear_bit());
+    }
+
+    pub fn is_alarm_triggered(&self) -> bool {
+        ALARM_TRIGGERED.load(Ordering::Relaxed)
+    }
+}
+
+pub fn on_interrupt() {
+    let rtc = unsafe { &*pac::Rtc0::ptr() };
+    // Check if this is actually a time alarm interrupt
+    let sr = rtc.sr().read();
+    if sr.taf().bit_is_set() {
+        rtc.ier().modify(|_, w| w.taie().clear_bit());
+        ALARM_TRIGGERED.store(true, Ordering::SeqCst);
+    }
+}
+
+pub struct RtcHandler;
+impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::RTC> for RtcHandler {
+    unsafe fn on_interrupt() {
+        on_interrupt();
+    }
+}
diff --git a/src/uart.rs b/src/uart.rs
new file mode 100644
index 000000000..3209a318d
--- /dev/null
+++ b/src/uart.rs
@@ -0,0 +1,306 @@
+//! Minimal polling UART2 bring-up replicating MCUXpresso hello_world ordering.
+//! WARNING: This is a narrow implementation only for debug console (115200 8N1).
+
+use core::cell::RefCell;
+
+use cortex_m::interrupt::Mutex;
+use embassy_sync::signal::Signal;
+
+use crate::pac;
+
+// svd2rust defines the shared LPUART RegisterBlock under lpuart0; all instances reuse it.
+type Regs = pac::lpuart0::RegisterBlock;
+
+// Token-based instance pattern like embassy-imxrt
+pub trait Instance {
+    fn ptr() -> *const Regs;
+}
+
+/// Token for LPUART2 provided by embassy-hal-internal peripherals macro.
+pub type Lpuart2 = crate::peripherals::LPUART2;
+impl Instance for crate::peripherals::LPUART2 {
+    #[inline(always)]
+    fn ptr() -> *const Regs {
+        pac::Lpuart2::ptr()
+    }
+}
+
+// Also implement Instance for the Peri wrapper type
+impl Instance for embassy_hal_internal::Peri<'_, crate::peripherals::LPUART2> {
+    #[inline(always)]
+    fn ptr() -> *const Regs {
+        pac::Lpuart2::ptr()
+    }
+}
+
+/// UART configuration (explicit src_hz; no hardcoded frequencies)
+#[derive(Copy, Clone)]
+pub struct Config {
+    pub src_hz: u32,
+    pub baud: u32,
+    pub parity: Parity,
+    pub stop_bits: StopBits,
+}
+
+#[derive(Copy, Clone)]
+pub enum Parity {
+    None,
+    Even,
+    Odd,
+}
+#[derive(Copy, Clone)]
+pub enum StopBits {
+    One,
+    Two,
+}
+
+impl Config {
+    pub fn new(src_hz: u32) -> Self {
+        Self {
+            src_hz,
+            baud: 115_200,
+            parity: Parity::None,
+            stop_bits: StopBits::One,
+        }
+    }
+}
+
+/// Compute a valid (OSR, SBR) tuple for given source clock and baud.
+/// Uses a functional fold approach to find the best OSR/SBR combination
+/// with minimal baud rate error.
+fn compute_osr_sbr(src_hz: u32, baud: u32) -> (u8, u16) {
+    let (best_osr, best_sbr, _best_err) = (8u32..=32).fold(
+        (16u8, 4u16, u32::MAX), // (best_osr, best_sbr, best_err)
+        |(best_osr, best_sbr, best_err), osr| {
+            let denom = baud.saturating_mul(osr);
+            if denom == 0 {
+                return (best_osr, best_sbr, best_err);
+            }
+
+            let sbr = (src_hz + denom / 2) / denom; // round
+            if sbr == 0 || sbr > 0x1FFF {
+                return (best_osr, best_sbr, best_err);
+            }
+
+            let actual = src_hz / (osr * sbr);
+            let err = actual.abs_diff(baud);
+
+            // Update best if this is better, or same error but higher OSR
+            if err < best_err || (err == best_err && osr as u8 > best_osr) {
+                (osr as u8, sbr as u16, err)
+            } else {
+                (best_osr, best_sbr, best_err)
+            }
+        },
+    );
+    (best_osr, best_sbr)
+}
+
+/// Minimal UART handle for a specific instance I (store the zero-sized token like embassy)
+pub struct Uart<I: Instance> {
+    _inst: core::marker::PhantomData<I>,
+}
+
+impl<I: Instance> Uart<I> {
+    /// Create and initialize LPUART (reset + config). Clocks and pins must be prepared by the caller.
+    pub fn new(_inst: impl Instance, cfg: Config) -> Self {
+        let l = unsafe { &*I::ptr() };
+        // 1) software reset pulse
+        l.global().write(|w| w.rst().reset());
+        cortex_m::asm::delay(3); // Short delay for reset to take effect
+        l.global().write(|w| w.rst().no_effect());
+        cortex_m::asm::delay(10); // Allow peripheral to stabilize after reset
+                                  // 2) BAUD
+        let (osr, sbr) = compute_osr_sbr(cfg.src_hz, cfg.baud);
+        l.baud().modify(|_, w| {
+            let w = match cfg.stop_bits {
+                StopBits::One => w.sbns().one(),
+                StopBits::Two => w.sbns().two(),
+            };
+            // OSR field encodes (osr-1); use raw bits to avoid a long match on all variants
+            let raw_osr = osr.saturating_sub(1) as u8;
+            unsafe { w.osr().bits(raw_osr).sbr().bits(sbr) }
+        });
+        // 3) CTRL baseline and parity
+        l.ctrl().write(|w| {
+            let w = w.ilt().from_stop().idlecfg().idle_2();
+            let w = match cfg.parity {
+                Parity::None => w.pe().disabled(),
+                Parity::Even => w.pe().enabled().pt().even(),
+                Parity::Odd => w.pe().enabled().pt().odd(),
+            };
+            w.re().enabled().te().enabled().rie().disabled()
+        });
+        // 4) FIFOs and WATER: keep it simple for polling; disable FIFOs and set RX watermark to 0
+        l.fifo().modify(|_, w| {
+            w.txfe()
+                .disabled()
+                .rxfe()
+                .disabled()
+                .txflush()
+                .txfifo_rst()
+                .rxflush()
+                .rxfifo_rst()
+        });
+        l.water()
+            .modify(|_, w| unsafe { w.txwater().bits(0).rxwater().bits(0) });
+        Self {
+            _inst: core::marker::PhantomData,
+        }
+    }
+
+    /// Enable RX interrupts. The caller must ensure an appropriate IRQ handler is installed.
+    pub unsafe fn enable_rx_interrupts(&self) {
+        let l = &*I::ptr();
+        l.ctrl().modify(|_, w| w.rie().enabled());
+    }
+
+    #[inline(never)]
+    pub fn write_byte(&self, b: u8) {
+        let l = unsafe { &*I::ptr() };
+        // Timeout after ~10ms at 12MHz (assuming 115200 baud, should be plenty)
+        const DATA_OFFSET: usize = 0x1C; // DATA register offset inside LPUART block
+        let data_ptr = unsafe { (I::ptr() as *mut u8).add(DATA_OFFSET) };
+        for _ in 0..120000 {
+            if l.water().read().txcount().bits() == 0 {
+                unsafe { core::ptr::write_volatile(data_ptr, b) };
+                return;
+            }
+        }
+        // If timeout, skip the write to avoid hanging
+    }
+
+    #[inline(never)]
+    pub fn write_str_blocking(&self, s: &str) {
+        for &b in s.as_bytes() {
+            if b == b'\n' {
+                self.write_byte(b'\r');
+            }
+            self.write_byte(b);
+        }
+    }
+    pub fn read_byte_blocking(&self) -> u8 {
+        let l = unsafe { &*I::ptr() };
+        while !l.stat().read().rdrf().is_rxdata() {}
+        (l.data().read().bits() & 0xFF) as u8
+    }
+}
+
+// Simple ring buffer for UART RX data
+const RX_BUFFER_SIZE: usize = 256;
+pub struct RingBuffer {
+    buffer: [u8; RX_BUFFER_SIZE],
+    read_idx: usize,
+    write_idx: usize,
+    count: usize,
+}
+
+impl RingBuffer {
+    pub const fn new() -> Self {
+        Self {
+            buffer: [0; RX_BUFFER_SIZE],
+            read_idx: 0,
+            write_idx: 0,
+            count: 0,
+        }
+    }
+
+    pub fn push(&mut self, data: u8) -> bool {
+        if self.count >= RX_BUFFER_SIZE {
+            return false; // Buffer full
+        }
+        self.buffer[self.write_idx] = data;
+        self.write_idx = (self.write_idx + 1) % RX_BUFFER_SIZE;
+        self.count += 1;
+        true
+    }
+
+    pub fn pop(&mut self) -> Option<u8> {
+        if self.count == 0 {
+            return None;
+        }
+        let data = self.buffer[self.read_idx];
+        self.read_idx = (self.read_idx + 1) % RX_BUFFER_SIZE;
+        self.count -= 1;
+        Some(data)
+    }
+
+    pub fn is_empty(&self) -> bool {
+        self.count == 0
+    }
+
+    pub fn len(&self) -> usize {
+        self.count
+    }
+}
+
+// Global RX buffer shared between interrupt handler and UART instance
+static RX_BUFFER: Mutex<RefCell<RingBuffer>> = Mutex::new(RefCell::new(RingBuffer::new()));
+static RX_SIGNAL: Signal<embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex, ()> = Signal::new();
+
+// Debug counter for interrupt handler calls
+static mut INTERRUPT_COUNT: u32 = 0;
+
+impl<I: Instance> Uart<I> {
+    /// Read a byte asynchronously using interrupts
+    pub async fn read_byte_async(&self) -> u8 {
+        loop {
+            // Check if we have data in the buffer
+            let byte = cortex_m::interrupt::free(|cs| {
+                let mut buffer = RX_BUFFER.borrow(cs).borrow_mut();
+                buffer.pop()
+            });
+
+            if let Some(byte) = byte {
+                return byte;
+            }
+
+            // Wait for the interrupt signal
+            RX_SIGNAL.wait().await;
+        }
+    }
+
+    /// Check if there's data available in the RX buffer
+    pub fn rx_data_available(&self) -> bool {
+        cortex_m::interrupt::free(|cs| {
+            let buffer = RX_BUFFER.borrow(cs).borrow();
+            !buffer.is_empty()
+        })
+    }
+
+    /// Try to read a byte from RX buffer (non-blocking)
+    pub fn try_read_byte(&self) -> Option<u8> {
+        cortex_m::interrupt::free(|cs| {
+            let mut buffer = RX_BUFFER.borrow(cs).borrow_mut();
+            buffer.pop()
+        })
+    }
+}
+
+/// Type-level handler for LPUART2 interrupts, compatible with bind_interrupts!.
+pub struct UartInterruptHandler;
+
+impl crate::interrupt::typelevel::Handler<crate::interrupt::typelevel::LPUART2> for UartInterruptHandler {
+    unsafe fn on_interrupt() {
+        INTERRUPT_COUNT += 1;
+
+        let lpuart = &*pac::Lpuart2::ptr();
+
+        // Check if we have RX data
+        if lpuart.stat().read().rdrf().is_rxdata() {
+            // Read the data byte
+            let data = (lpuart.data().read().bits() & 0xFF) as u8;
+
+            // Store in ring buffer
+            cortex_m::interrupt::free(|cs| {
+                let mut buffer = RX_BUFFER.borrow(cs).borrow_mut();
+                if buffer.push(data) {
+                    // Data added successfully, signal waiting tasks
+                    RX_SIGNAL.signal(());
+                }
+            });
+        }
+        // Always clear any error flags that might cause spurious interrupts
+        let _ = lpuart.stat().read();
+    }
+}
diff --git a/supply-chain/README.md b/supply-chain/README.md
index d43d50485..12f8777b0 100644
--- a/supply-chain/README.md
+++ b/supply-chain/README.md
@@ -1,83 +1,149 @@
-# Working with cargo vet
-
-## Introduction
-
-`cargo vet` is a tool to help ensure that third-party Rust dependencies have been audited by a trusted entity.
-It matches all dependencies against a set of audits conducted by the authors of the project or entities they trust.  
-To learn more, visit [mozilla/cargo-vet](https://github.com/mozilla/cargo-vet)
-
----
-
-## Adding a new dependency
-
-When updating or adding a new dependency, we need to ensure it's audited before being merged into main.  
-For our repositories, we have designated experts who are responsible for vetting any new dependencies being added to their repository.  
-_It is the shared responsibility of the developer creating the PR and the auditors to conduct a successful audit._  
-Follow the process below to ensure compliance:
-
-### For Developers
-1. **Respond to `cargo vet` failures**:
-  - If your PR fails the `cargo vet` step, the cargo-vet workflow will add a comment to the PR with a template questionnaire
-  - Copy the questionnaire, fill it out and paste it as a new comment on the PR. This greatly helps the auditors get some context of the changes requiring the new dependencies
-
-2. **Engage with auditors**:
-  - Respond to any questions that the auditors might have regarding the need of any new dependencies
-
-3. **Rebase and verify**:
-  - At their discretion, auditors will check in their audits into either [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) or into the same repository
-  - Once the new audits have been merged, rebase your branch on main and verify it passes `cargo vet`
-    ```bash
-    git fetch upstream
-    git rebase upstream/main
-    cargo vet
-    ```
-
-4. **Update PR**:
-  - If the audits were checked into rust-crate-audits, they will show up in _imports.lock_ on running `cargo vet`. In this case add the updated _imports.lock_ to your PR
-  - If the audits were checked into the same repository, they will be present in _audits.toml_ after rebase and you can simply force push to your PR after rebase
-    ```bash
-    git push -f
-    ```
-
-5. **Check PR status**:
-  - The existing PR comment from the previous failure will be updated with a success message once the check passes
-
-### For Auditors
-
-1. **Review the questionnaire**:
-  - Check the filled questionnaire on the PR once the developer responds to the `cargo vet` failure
-  - Respond to the developer comment in case more information is needed
-
-2. **Audit new dependencies**:
-  - Inspect the `cargo vet` failures using your preferred method
-    - Use [gh pr checkout](https://cli.github.com/manual/gh_pr_checkout) to checkout the PR and run `cargo vet --locked`
-    - Use [Github Pull Requests for Visual Studio Code](https://marketplace.visualstudio.com/items?itemName=GitHub.vscode-pull-request-github) to checkout the PR and run `cargo vet --locked`
-    - For more suggestions: [Checking out pull requests locally](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/checking-out-pull-requests-locally)
-
-3. **Follow `cargo vet` recommendations**:
-  - Follow the recommendations of the `cargo vet` command output, either `cargo vet diff` for version update or `cargo vet inspect` for new dependencies
-
-4. **Record audits**:
-  - Use `cargo vet certify` to add new audits to _audits.toml_
-  - Verify all dependencies pass using `cargo vet`
-
-5. **Decide audit location**:
-  - **Shared audits**: New audits should ideally be shared across ODP repositories to reduce the overhead of multiple audits for the same dependencies. To facilitate this, it's recommended to cut and paste the new audits and submit as a separate PR to the _audits.toml_ in [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits)
-  - If due to business reasons, the audits are not to be shared across repositories, copy the updated _audits.toml_ to a new branch off main in the same repository and submit the PR to update the audits
-
-6. **Communicate successful audit**:
-  - Communicate to the PR developer via a PR comment so they can update the PR and get `cargo vet` to pass
-
----
-
-## Tips for using `cargo vet`:
-
-- **Update _imports.lock_**:
-  - Import trusted third party audits to reduce the number of new audits to be performed. Running `cargo vet` without `--locked` fetches new imports and updates _imports.lock_ with any audits that are helpful for our project.
-
-- **Add exemptions**:
-  - If an audit cannot be performed for some dependency due to time sensitivity or business justified reasons, use `cargo vet add-exemption <PACKAGE> <VERSION>` to add the dependency to exemptions in _config.toml_
-  - To add all remaining audits to exemptions at once, use `cargo vet regenerate exemptions`
-
-- **Prune unnecessary entries**:
+# Working with cargo vet

+

+## Introduction

+

+`cargo vet` is a tool to help ensure that third-party Rust dependencies have been audited by a trusted entity.

+It matches all dependencies against a set of audits conducted by the authors of the project or entities they trust.  

+To learn more, visit [mozilla/cargo-vet](https://github.com/mozilla/cargo-vet)

+

+---

+

+## Adding a new dependency

+

+When updating or adding a new dependency, we need to ensure it's audited before being merged into main.  

+For our repositories, we have designated experts who are responsible for vetting any new dependencies being added to their repository.  

+_It is the shared responsibility of the developer creating the PR and the auditors to conduct a successful audit._  

+Follow the process below to ensure compliance:

+

+### For Developers

+1. **Respond to `cargo vet` failures**:

+  - If your PR fails the `cargo vet` step, the cargo-vet workflow will add a comment to the PR with a template questionnaire

+  - Copy the questionnaire, fill it out and paste it as a new comment on the PR. This greatly helps the auditors get some context of the changes requiring the new dependencies

+

+2. **Engage with auditors**:

+  - Respond to any questions that the auditors might have regarding the need of any new dependencies

+

+3. **Rebase and verify**:

+  - At their discretion, auditors will check in their audits into either [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits) or into the same repository

+  - Once the new audits have been merged, rebase your branch on main and verify it passes `cargo vet`

+    ```bash

+    git fetch upstream

+    git rebase upstream/main

+    cargo vet

+    ```

+

+4. **Update PR**:

+  - If the audits were checked into rust-crate-audits, they will show up in _imports.lock_ on running `cargo vet`. In this case add the updated _imports.lock_ to your PR

+  - If the audits were checked into the same repository, they will be present in _audits.toml_ after rebase and you can simply force push to your PR after rebase

+    ```bash

+    git push -f

+    ```

+

+5. **Check PR status**:

+  - The existing PR comment from the previous failure will be updated with a success message once the check passes

+

+### For Auditors

+

+1. **Review the questionnaire**:

+  - Check the filled questionnaire on the PR once the developer responds to the `cargo vet` failure

+  - Respond to the developer comment in case more information is needed

+

+2. **Audit new dependencies**:

+  - Inspect the `cargo vet` failures using your preferred method

+    - Use [gh pr checkout](https://cli.github.com/manual/gh_pr_checkout) to checkout the PR and run `cargo vet --locked`

+    - Use [Github Pull Requests for Visual Studio Code](https://marketplace.visualstudio.com/items?itemName=GitHub.vscode-pull-request-github) to checkout the PR and run `cargo vet --locked`

+    - For more suggestions: [Checking out pull requests locally](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/checking-out-pull-requests-locally)

+

+3. **Follow `cargo vet` recommendations**:

+  - Follow the recommendations of the `cargo vet` command output, either `cargo vet diff` for version update or `cargo vet inspect` for new dependencies

+

+4. **Record audits**:

+  - Use `cargo vet certify` to add new audits to _audits.toml_

+  - Verify all dependencies pass using `cargo vet`

+

+5. **Decide audit location**:

+  - **Shared audits**: New audits should ideally be shared across ODP repositories to reduce the overhead of multiple audits for the same dependencies. To facilitate this, it's recommended to cut and paste the new audits and submit as a separate PR to the _audits.toml_ in [rust-crate-audits](https://github.com/OpenDevicePartnership/rust-crate-audits)

+  - If due to business reasons, the audits are not to be shared across repositories, copy the updated _audits.toml_ to a new branch off main in the same repository and submit the PR to update the audits

+

+6. **Communicate successful audit**:

+  - Communicate to the PR developer via a PR comment so they can update the PR and get `cargo vet` to pass

+

+---

+

+## Audit criteria

+`cargo vet` comes pre-equipped with two built-in criteria but supports adding new criteria to suit our needs.  

+As defined [here](https://mozilla.github.io/cargo-vet/built-in-criteria.html), the default criteria are:

+

+- **safe-to-run**  

+  This crate can be compiled, run, and tested on a local workstation or in

+  controlled automation without surprising consequences, such as:

+  * Reading or writing data from sensitive or unrelated parts of the filesystem.

+  * Installing software or reconfiguring the device.

+  * Connecting to untrusted network endpoints.

+  * Misuse of system resources (e.g. cryptocurrency mining).

+

+- **safe-to-deploy**  

+  This crate will not introduce a serious security vulnerability to production

+  software exposed to untrusted input.

+  

+  Auditors are not required to perform a full logic review of the entire crate.

+  Rather, they must review enough to fully reason about the behavior of all unsafe

+  blocks and usage of powerful imports. For any reasonable usage of the crate in

+  real-world software, an attacker must not be able to manipulate the runtime

+  behavior of these sections in an exploitable or surprising way.

+  

+  Ideally, all unsafe code is fully sound, and ambient capabilities (e.g.

+  filesystem access) are hardened against manipulation and consistent with the

+  advertised behavior of the crate. However, some discretion is permitted. In such

+  cases, the nature of the discretion should be recorded in the `notes` field of

+  the audit record.

+  

+  For crates which generate deployed code (e.g. build dependencies or procedural

+  macros), reasonable usage of the crate should output code which meets the above

+  criteria.

+

+  **Note: `safe-to-deploy` implies `safe-to-run`**

+

+---

+

+## Conducting an audit

+

+When performing an audit for a new or updated dependency, auditors may consider the following criteria to ensure the safety, reliability, and suitability of the crate for use in our projects:

+

+- **Security**:  

+  - Review the crate for known vulnerabilities or security advisories.

+  - Check for unsafe code usage and ensure it is justified and well-documented.

+  - Evaluate the crate’s history of security issues and responsiveness to reported problems.

+

+- **Maintenance and Activity**:  

+  - Assess the frequency of updates and the responsiveness of maintainers to issues and pull requests.

+  - Prefer crates that are actively maintained and have a healthy contributor base.

+

+- **License Compliance**:  

+  - Verify that the crate’s license is compatible with our project’s licensing requirements.

+

+- **Community Trust and Adoption**:  

+  - Consider the crate’s adoption in the wider Rust ecosystem.

+  - Prefer crates that are widely used and trusted by the community.

+

+- **Functionality and Suitability**:  

+  - Confirm that the crate provides the required functionality without unnecessary features or bloat.

+  - Evaluate whether the crate’s API is stable and unlikely to introduce breaking changes unexpectedly.

+

+- **Audit Trail**:  

+  - Record the audit decision, including any concerns, mitigations, or recommendations for future updates.

+  - If exemptions are granted, document the justification and any follow-up actions required.

+

+---

+

+## Tips for using `cargo vet`:

+

+- **Update _imports.lock_**:

+  - Import trusted third party audits to reduce the number of new audits to be performed. Running `cargo vet` without `--locked` fetches new imports and updates _imports.lock_ with any audits that are helpful for our project.

+

+- **Add exemptions**:

+  - If an audit cannot be performed for some dependency due to time sensitivity or business justified reasons, use `cargo vet add-exemption <PACKAGE> <VERSION>` to add the dependency to exemptions in _config.toml_

+  - To add all remaining audits to exemptions at once, use `cargo vet regenerate exemptions`

+

+- **Prune unnecessary entries**:

   - Remove unnecessary exemptions and imports using `cargo vet prune`
\ No newline at end of file
diff --git a/supply-chain/audits.toml b/supply-chain/audits.toml
index 2772ccb21..60ebedf9b 100644
--- a/supply-chain/audits.toml
+++ b/supply-chain/audits.toml
@@ -1,4 +1,128 @@
 
 # cargo-vet audits file
 
-[audits]
+[[audits.autocfg]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.5.0"
+
+[[audits.cfg-if]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.4"
+
+[[audits.darling]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.20.11"
+
+[[audits.darling_core]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.20.11"
+
+[[audits.darling_macro]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.20.11"
+
+[[audits.defmt-rtt]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.0"
+notes = "defmt-rtt is used for all our logging purposes. Version 1.0.0 merely stabilizes what was already available previously."
+
+[[audits.defmt-rtt]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.0 -> 1.1.0"
+
+[[audits.document-features]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.2.12"
+
+[[audits.document-features]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-run"
+version = "0.2.12"
+
+[[audits.embassy-executor]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.9.1"
+
+[[audits.embassy-executor-macros]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.7.0"
+
+[[audits.embassy-executor-timer-queue]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.1.0"
+
+[[audits.embassy-executor-timer-queue]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.1.0"
+
+[[audits.embassy-time-queue-utils]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.3.0"
+
+[[audits.ident_case]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.1"
+
+[[audits.litrs]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.0"
+
+[[audits.panic-probe]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.0"
+
+[[audits.proc-macro2]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.103"
+
+[[audits.quote]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.42"
+
+[[audits.stable_deref_trait]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.2.1"
+
+[[audits.static_cell]]
+who = "jerrysxie <[email protected]>"
+criteria = "safe-to-run"
+delta = "2.1.0 -> 2.1.1"
+
+[[audits.syn]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "2.0.100 -> 2.0.109"
+
+[[audits.thiserror]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "2.0.17"
+
+[[audits.thiserror-impl]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "2.0.17"
+
+[[audits.unicode-ident]]
+who = "Felipe Balbi <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.22"
diff --git a/supply-chain/config.toml b/supply-chain/config.toml
index 55618c2ff..5927b0b61 100644
--- a/supply-chain/config.toml
+++ b/supply-chain/config.toml
@@ -12,3 +12,187 @@ url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.to
 
 [imports.mozilla]
 url = "https://raw.githubusercontent.com/mozilla/supply-chain/main/audits.toml"
+
+[[exemptions.az]]
+version = "1.2.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.bare-metal]]
+version = "0.2.5"
+criteria = "safe-to-deploy"
+
+[[exemptions.bitfield]]
+version = "0.13.2"
+criteria = "safe-to-deploy"
+
+[[exemptions.bitfield]]
+version = "0.15.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.chrono]]
+version = "0.4.40"
+criteria = "safe-to-deploy"
+
+[[exemptions.cortex-m]]
+version = "0.7.7"
+criteria = "safe-to-deploy"
+
+[[exemptions.cortex-m-rt]]
+version = "0.7.5"
+criteria = "safe-to-deploy"
+
+[[exemptions.cortex-m-rt-macros]]
+version = "0.7.5"
+criteria = "safe-to-deploy"
+
+[[exemptions.critical-section]]
+version = "1.2.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.defmt]]
+version = "1.0.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.defmt-macros]]
+version = "1.0.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.defmt-parser]]
+version = "1.0.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.embassy-embedded-hal]]
+version = "0.5.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.embassy-futures]]
+version = "0.1.2"
+criteria = "safe-to-deploy"
+
+[[exemptions.embassy-hal-internal]]
+version = "0.3.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.embassy-sync]]
+version = "0.7.2"
+criteria = "safe-to-deploy"
+
+[[exemptions.embassy-time]]
+version = "0.5.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.embassy-time-driver]]
+version = "0.2.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.embedded-hal]]
+version = "0.2.7"
+criteria = "safe-to-deploy"
+
+[[exemptions.embedded-hal]]
+version = "1.0.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.embedded-hal-async]]
+version = "1.0.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.embedded-hal-nb]]
+version = "1.0.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.embedded-io]]
+version = "0.6.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.embedded-io-async]]
+version = "0.6.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.embedded-storage]]
+version = "0.3.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.embedded-storage-async]]
+version = "0.4.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.fixed]]
+version = "1.29.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.futures-core]]
+version = "0.3.31"
+criteria = "safe-to-deploy"
+
+[[exemptions.futures-sink]]
+version = "0.3.31"
+criteria = "safe-to-deploy"
+
+[[exemptions.hash32]]
+version = "0.3.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.heapless]]
+version = "0.8.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.itertools]]
+version = "0.11.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.log]]
+version = "0.4.27"
+criteria = "safe-to-deploy"
+
+[[exemptions.mimxrt600-fcb]]
+version = "0.2.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.paste]]
+version = "1.0.15"
+criteria = "safe-to-deploy"
+
+[[exemptions.portable-atomic]]
+version = "1.11.0"
+criteria = "safe-to-run"
+
+[[exemptions.proc-macro-error-attr2]]
+version = "2.0.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.proc-macro-error2]]
+version = "2.0.1"
+criteria = "safe-to-deploy"
+
+[[exemptions.rustc_version]]
+version = "0.2.3"
+criteria = "safe-to-deploy"
+
+[[exemptions.semver]]
+version = "0.9.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.semver-parser]]
+version = "0.7.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.static_cell]]
+version = "2.1.0"
+criteria = "safe-to-run"
+
+[[exemptions.syn]]
+version = "2.0.100"
+criteria = "safe-to-deploy"
+
+[[exemptions.typenum]]
+version = "1.18.0"
+criteria = "safe-to-deploy"
+
+[[exemptions.vcell]]
+version = "0.1.3"
+criteria = "safe-to-deploy"
+
+[[exemptions.volatile-register]]
+version = "0.2.2"
+criteria = "safe-to-deploy"
diff --git a/supply-chain/imports.lock b/supply-chain/imports.lock
index 219dba4ee..3f541e59f 100644
--- a/supply-chain/imports.lock
+++ b/supply-chain/imports.lock
@@ -3,6 +3,470 @@
 
 [audits.OpenDevicePartnership.audits]
 
-[audits.google.audits]
+[[audits.google.audits.autocfg]]
+who = "Manish Goregaokar <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.4.0"
+notes = "Contains no unsafe"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
 
-[audits.mozilla.audits]
+[[audits.google.audits.bitflags]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.3.2"
+notes = """
+Security review of earlier versions of the crate can be found at
+(Google-internal, sorry): go/image-crate-chromium-security-review
+
+The crate exposes a function marked as `unsafe`, but doesn't use any
+`unsafe` blocks (except for tests of the single `unsafe` function).  I
+think this justifies marking this crate as `ub-risk-1`.
+
+Additional review comments can be found at https://crrev.com/c/4723145/31
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.bytemuck]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.16.3"
+notes = """
+Review notes from the original audit (of 1.14.3) may be found in
+https://crrev.com/c/5362675.  Note that this audit has initially missed UB risk
+that was fixed in 1.16.2 - see https://github.com/Lokathor/bytemuck/pull/258.
+Because of this, the original audit has been edited to certify version `1.16.3`
+instead (see also https://crrev.com/c/5771867).
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.bytemuck]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.16.3 -> 1.17.1"
+notes = "Unsafe review comments can be found in https://crrev.com/c/5813463"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.bytemuck]]
+who = "Adrian Taylor <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.17.1 -> 1.18.0"
+notes = "No code changes - just altering feature flag arrangements"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.bytemuck]]
+who = "Adrian Taylor <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.18.0 -> 1.19.0"
+notes = "No code changes - just comment changes and adding the track_caller attribute."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.bytemuck]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.19.0 -> 1.20.0"
+notes = "`unsafe` review can be found at https://crrev.com/c/6096767"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.bytemuck]]
+who = "Adrian Taylor <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.20.0 -> 1.21.0"
+notes = "Unsafe review at https://chromium-review.googlesource.com/c/chromium/src/+/6111154/"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.bytemuck]]
+who = "Daniel Cheng <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.21.0 -> 1.22.0"
+notes = """
+This adds new instances of unsafe, but the uses are justified:
+- BoxBytes is essentially a Box<[u8], which is Send + Sync, so also marking BoxBytes as Send + Sync is justified.
+- core::num::Saturating<T> meets the criteria for Zeroable + Pod, so marking it as such is justified.
+
+See https://crrev.com/c/6321863 for more audit notes.
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.byteorder]]
+who = "danakj <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.5.0"
+notes = "Unsafe review in https://crrev.com/c/5838022"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.cfg-if]]
+who = "George Burgess IV <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.0"
+aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT"
+
+[[audits.google.audits.either]]
+who = "Manish Goregaokar <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.13.0"
+notes = "Unsafe code pertaining to wrapping Pin APIs. Mostly passes invariants down."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.either]]
+who = "Daniel Cheng <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.13.0 -> 1.14.0"
+notes = """
+Inheriting ub-risk-1 from the baseline review of 1.13.0. While the delta has some diffs in unsafe code, they are either:
+- migrating code to use helper macros
+- migrating match patterns to take advantage of default bindings mode from RFC 2005
+Either way, the result is code that does exactly the same thing and does not change the risk of UB.
+
+See https://crrev.com/c/6323164 for more audit details.
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.either]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.14.0 -> 1.15.0"
+notes = "The delta in `lib.rs` only tweaks doc comments and `#[cfg(feature = \"std\")]`."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.nb]]
+who = "George Burgess IV <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.0"
+aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT"
+
+[[audits.google.audits.nb]]
+who = "George Burgess IV <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.0 -> 0.1.3"
+aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT"
+
+[[audits.google.audits.nb]]
+who = "George Burgess IV <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.0 -> 1.1.0"
+aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT"
+
+[[audits.google.audits.num-traits]]
+who = "Manish Goregaokar <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.2.19"
+notes = "Contains a single line of float-to-int unsafe with decent safety comments"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.78"
+notes = """
+Grepped for \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits
+(except for a benign \"fs\" hit in a doc comment)
+
+Notes from the `unsafe` review can be found in https://crrev.com/c/5385745.
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Adrian Taylor <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.78 -> 1.0.79"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Adrian Taylor <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.79 -> 1.0.80"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Dustin J. Mitchell <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.80 -> 1.0.81"
+notes = "Comment changes only"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "danakj <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.81 -> 1.0.82"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Dustin J. Mitchell <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.82 -> 1.0.83"
+notes = "Substantive change is replacing String with Box<str>, saving memory."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.83 -> 1.0.84"
+notes = "Only doc comment changes in `src/lib.rs`."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "[email protected]"
+criteria = "safe-to-deploy"
+delta = "1.0.84 -> 1.0.85"
+notes = "Test-only changes."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.85 -> 1.0.86"
+notes = """
+Comment-only changes in `build.rs`.
+Reordering of `Cargo.toml` entries.
+Just bumping up the version number in `lib.rs`.
+Config-related changes in `test_size.rs`.
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "danakj <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.86 -> 1.0.87"
+notes = "No new unsafe interactions."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Liza Burakova <[email protected]"
+criteria = "safe-to-deploy"
+delta = "1.0.87 -> 1.0.89"
+notes = """
+Biggest change is adding error handling in build.rs.
+Some config related changes in wrapper.rs.
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.89 -> 1.0.92"
+notes = """
+I looked at the delta and the previous discussion at
+https://chromium-review.googlesource.com/c/chromium/src/+/5385745/3#message-a8e2813129fa3779dab15acede408ee26d67b7f3
+and the changes look okay to me (including the `unsafe fn from_str_unchecked`
+changes in `wrapper.rs`).
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.92 -> 1.0.93"
+notes = "No `unsafe`-related changes."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.proc-macro2]]
+who = "Daniel Cheng <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.93 -> 1.0.94"
+notes = "Minor doc changes and clippy lint adjustments+fixes."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.quote]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.35"
+notes = """
+Grepped for \"unsafe\", \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits
+(except for benign \"net\" hit in tests and \"fs\" hit in README.md)
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.quote]]
+who = "Adrian Taylor <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.35 -> 1.0.36"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.quote]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.36 -> 1.0.37"
+notes = """
+The delta just 1) inlines/expands `impl ToTokens` that used to be handled via
+`primitive!` macro and 2) adds `impl ToTokens` for `CStr` and `CString`.
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.quote]]
+who = "Dustin J. Mitchell <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.37 -> 1.0.38"
+notes = "Still no unsafe"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.quote]]
+who = "Daniel Cheng <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.38 -> 1.0.39"
+notes = "Only minor changes for clippy lints and documentation."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.quote]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.39 -> 1.0.40"
+notes = """
+The delta is just a simplification of how `tokens.extend(...)` call is made.
+Still no `unsafe` anywhere.
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.rand_core]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.6.4"
+notes = """
+For more detailed unsafe review notes please see https://crrev.com/c/6362797
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.stable_deref_trait]]
+who = "Manish Goregaokar <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.2.0"
+notes = "Purely a trait, crates using this should be carefully vetted since self-referential stuff can be super tricky around various unsafe rust edges."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.strsim]]
+who = "[email protected]"
+criteria = "safe-to-deploy"
+version = "0.10.0"
+notes = """
+Reviewed in https://crrev.com/c/5171063
+
+Previously reviewed during security review and the audit is grandparented in.
+"""
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.unicode-ident]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.12"
+notes = '''
+I grepped for \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits.
+
+All two functions from the public API of this crate use `unsafe` to avoid bound
+checks for an array access.  Cross-module analysis shows that the offsets can
+be statically proven to be within array bounds.  More details can be found in
+the unsafe review CL at https://crrev.com/c/5350386.
+
+This crate has been added to Chromium in https://crrev.com/c/3891618.
+'''
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.unicode-ident]]
+who = "Dustin J. Mitchell <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.12 -> 1.0.13"
+notes = "Lots of table updates, and tables are assumed correct with unsafe `.get_unchecked()`, so ub-risk-2 is appropriate"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.unicode-ident]]
+who = "Lukasz Anforowicz <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.13 -> 1.0.14"
+notes = "Minimal delta in `.rs` files: new test assertions + doc changes."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.unicode-ident]]
+who = "Adrian Taylor <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.14 -> 1.0.15"
+notes = "No changes relevant to any of these criteria."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.unicode-ident]]
+who = "Liza Burakova <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.15 -> 1.0.16"
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.unicode-ident]]
+who = "Daniel Cheng <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.0.16 -> 1.0.18"
+notes = "Only minor comment and documentation updates."
+aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT"
+
+[[audits.google.audits.void]]
+who = "George Burgess IV <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.2"
+aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT"
+
+[[audits.mozilla.audits.crunchy]]
+who = "Erich Gubler <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.2.3"
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
+
+[[audits.mozilla.audits.document-features]]
+who = "Erich Gubler <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.2.8"
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
+
+[[audits.mozilla.audits.document-features]]
+who = "Erich Gubler <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "0.2.8 -> 0.2.9"
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
+
+[[audits.mozilla.audits.document-features]]
+who = "Erich Gubler <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "0.2.9 -> 0.2.10"
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
+
+[[audits.mozilla.audits.document-features]]
+who = "Teodor Tanasoaia <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "0.2.10 -> 0.2.11"
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
+
+[[audits.mozilla.audits.fnv]]
+who = "Bobby Holley <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.0.7"
+notes = "Simple hasher implementation with no unsafe code."
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
+
+[[audits.mozilla.audits.half]]
+who = "John M. Schanck <[email protected]>"
+criteria = "safe-to-deploy"
+version = "1.8.2"
+notes = """
+This crate contains unsafe code for bitwise casts to/from binary16 floating-point
+format. I've reviewed these and found no issues. There are no uses of ambient
+capabilities.
+"""
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
+
+[[audits.mozilla.audits.half]]
+who = "Erich Gubler <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.8.2 -> 1.8.3"
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
+
+[[audits.mozilla.audits.half]]
+who = "Erich Gubler <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "1.8.3 -> 2.5.0"
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
+
+[[audits.mozilla.audits.litrs]]
+who = "Erich Gubler <[email protected]>"
+criteria = "safe-to-deploy"
+version = "0.4.1"
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
+
+[[audits.mozilla.audits.strsim]]
+who = "Ben Dean-Kawamura <[email protected]>"
+criteria = "safe-to-deploy"
+delta = "0.10.0 -> 0.11.1"
+aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml"
diff --git a/tools/run_and_attach_rtt.sh b/tools/run_and_attach_rtt.sh
new file mode 100644
index 000000000..13041d06b
--- /dev/null
+++ b/tools/run_and_attach_rtt.sh
@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+ELF="${1:-target/thumbv8m.main-none-eabihf/debug/examples/hello}"
+PROBE_ID="${2:-1fc9:0143:H3AYDQVQMTROB}"
+CHIP="${3:-MCXA276}"
+SPEED="${4:-1000}"
+
+# 1) Flash & run using the existing run.sh (probe is in use only during this step)
+./run.sh "$ELF"
+
+# 2) Give target a short moment to boot and set up RTT CB in RAM
+sleep 0.5
+
+# 3) Attach RTT/defmt using probe-rs (no flashing)
+exec probe-rs attach \
+  --chip "$CHIP" \
+  --probe "$PROBE_ID" \
+  --protocol swd \
+  --speed "$SPEED" \
+  "$ELF" \
+  --rtt-scan-memory \
+  --log-format oneline
+
diff --git a/tools/run_jlink_noblock.sh b/tools/run_jlink_noblock.sh
new file mode 100644
index 000000000..3ea1f2b4b
--- /dev/null
+++ b/tools/run_jlink_noblock.sh
@@ -0,0 +1,76 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+ELF="${1:-}"
+PROBE_ID="${2:-1366:0101:000600110607}" # default to your J-Link
+CHIP="${3:-MCXA276}"
+SPEED="${4:-1000}"
+PORT="${PROBE_RS_GDB_PORT:-1337}"
+
+if [[ -z "${ELF}" || ! -f "${ELF}" ]]; then
+  echo "Usage: $0 <elf> [probe-id] [chip] [speed-khz]" >&2
+  exit 1
+fi
+
+if ! command -v probe-rs >/dev/null 2>&1; then
+  echo "probe-rs not found (cargo install probe-rs --features cli)" >&2
+  exit 1
+fi
+if ! command -v gdb-multiarch >/dev/null 2>&1; then
+  echo "gdb-multiarch not found; install it (e.g., sudo apt install gdb-multiarch)." >&2
+  exit 1
+fi
+
+# Start probe-rs GDB server
+SERVER_LOG=$(mktemp)
+probe-rs gdb --chip "${CHIP}" --protocol swd --speed "${SPEED}" --non-interactive "${ELF}" --probe "${PROBE_ID}" \
+  >"${SERVER_LOG}" 2>&1 &
+GDB_SERVER_PID=$!
+
+# Wait for readiness
+for _ in {1..50}; do
+  if grep -q "Firing up GDB stub" "${SERVER_LOG}"; then break; fi
+  if grep -q "Connecting to the chip was unsuccessful" "${SERVER_LOG}"; then
+    echo "probe-rs gdb server failed. Log:" >&2
+    sed -e 's/^/  /' "${SERVER_LOG}" >&2 || true
+    kill "${GDB_SERVER_PID}" 2>/dev/null || true
+    exit 1
+  fi
+  sleep 0.1
+done
+
+# GDB script: load, resume, detach
+GDB_SCRIPT=$(mktemp)
+cat >"${GDB_SCRIPT}" <<EOF
+set pagination off
+set confirm off
+set mem inaccessible-by-default off
+
+target remote :${PORT}
+monitor halt
+load
+set language c
+# Start clean from Reset vector in RAM
+set {int}0xE000ED08 = 0x20000000
+set \$xpsr = 0x01000000
+set \$sp = 0x20020000
+set \$pc = Reset
+monitor resume
+detach
+quit
+EOF
+
+# Run GDB to program and resume target, then exit (probe released)
+if ! gdb-multiarch -q -x "${GDB_SCRIPT}" "${ELF}"; then
+  echo "GDB failed; server log:" >&2
+  sed -e 's/^/  /' "${SERVER_LOG}" >&2 || true
+  kill "${GDB_SERVER_PID}" 2>/dev/null || true
+  exit 1
+fi
+
+# Stop server now that we've detached
+kill "${GDB_SERVER_PID}" 2>/dev/null || true
+rm -f "${GDB_SCRIPT}" "${SERVER_LOG}" || true
+
+echo "Flashed, resumed, and detached (probe free)."
+