diff options
| author | ROMemories <[email protected]> | 2025-05-21 11:36:55 +0200 |
|---|---|---|
| committer | ROMemories <[email protected]> | 2025-05-21 14:19:24 +0200 |
| commit | 576241fe2a455fff58527d9a593583fdab2d51bb (patch) | |
| tree | a66c39687fa7d5cf7198ffeb0c505154d7d3d410 | |
| parent | da86052586b38768bdc2f709fda299ab06260cdb (diff) | |
feat(stm32-wba): provide a `const` constructor on `rcc::Config`
| -rw-r--r-- | embassy-stm32/src/rcc/wba.rs | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs index 1fee648d4..98d2dcf0e 100644 --- a/embassy-stm32/src/rcc/wba.rs +++ b/embassy-stm32/src/rcc/wba.rs | |||
| @@ -37,9 +37,9 @@ pub struct Config { | |||
| 37 | pub mux: super::mux::ClockMux, | 37 | pub mux: super::mux::ClockMux, |
| 38 | } | 38 | } |
| 39 | 39 | ||
| 40 | impl Default for Config { | 40 | impl Config { |
| 41 | #[inline] | 41 | #[inline] |
| 42 | fn default() -> Config { | 42 | pub const fn new() -> Self { |
| 43 | Config { | 43 | Config { |
| 44 | hse: None, | 44 | hse: None, |
| 45 | hsi: true, | 45 | hsi: true, |
| @@ -48,13 +48,20 @@ impl Default for Config { | |||
| 48 | apb1_pre: APBPrescaler::DIV1, | 48 | apb1_pre: APBPrescaler::DIV1, |
| 49 | apb2_pre: APBPrescaler::DIV1, | 49 | apb2_pre: APBPrescaler::DIV1, |
| 50 | apb7_pre: APBPrescaler::DIV1, | 50 | apb7_pre: APBPrescaler::DIV1, |
| 51 | ls: Default::default(), | 51 | ls: crate::rcc::LsConfig::new(), |
| 52 | voltage_scale: VoltageScale::RANGE2, | 52 | voltage_scale: VoltageScale::RANGE2, |
| 53 | mux: Default::default(), | 53 | mux: super::mux::ClockMux::default(), |
| 54 | } | 54 | } |
| 55 | } | 55 | } |
| 56 | } | 56 | } |
| 57 | 57 | ||
| 58 | impl Default for Config { | ||
| 59 | #[inline] | ||
| 60 | fn default() -> Config { | ||
| 61 | Self::new() | ||
| 62 | } | ||
| 63 | } | ||
| 64 | |||
| 58 | fn hsi_enable() { | 65 | fn hsi_enable() { |
| 59 | RCC.cr().modify(|w| w.set_hsion(true)); | 66 | RCC.cr().modify(|w| w.set_hsion(true)); |
| 60 | while !RCC.cr().read().hsirdy() {} | 67 | while !RCC.cr().read().hsirdy() {} |
