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+++ b/docs/modules/ROOT/pages/faq.adoc
@@ -4,6 +4,87 @@ These are a list of unsorted, commonly asked questions and answers.
 
 Please feel free to add items to link:https://github.com/embassy-rs/embassy/edit/main/docs/modules/ROOT/pages/faq.adoc[this page], especially if someone in the chat answered a question for you!
 
+== How do I even start?
+
+There are many ways to configure embassy and it's components for your exact application. The link:https://github.com/embassy-rs/embassy/tree/main/examples[examples] directory for each chipset demonstrate how your project structure should look. Let's break it down:
+
+The toplevel file structure of your project should look like this:
+[source,plain]
+----
+{} = Maybe
+
+my-project
+|- .cargo
+|  |- config.toml
+|- src
+|  |- main.rs
+|- build.rs
+|- Cargo.toml
+|- {memory.x}
+|- rust-toolchain.toml
+----
+
+=== .cargo/config.toml
+
+This directory/file describes what platform you're on, and configures link:https://github.com/probe-rs/probe-rs[probe-rs] to deploy to your device.
+
+Here is a minimal example:
+
+[source,toml]
+----
+[target.thumbv6m-none-eabi] # <-change for your platform
+runner = 'probe-rs run --chip STM32F031K6Tx' # <- change for your chip
+
+[build]
+target = "thumbv6m-none-eabi" # <-change for your platform
+
+[env]
+DEFMT_LOG = "trace" # <- can change to info, warn, or error
+----
+
+=== build.rs
+
+This is the build script for your project. It links defmt (what is defmt?) and the `memory.x` file if need be. This file is pretty specific for each chipset, just copy and paste from the corresponding link:https://github.com/embassy-rs/embassy/tree/main/examples[example].
+
+=== Cargo.toml
+
+This is your manifest file, where you can configure all of the embassy components to use the features you need.
+
+TODO: someone should exhaustively describe every feature for every component!
+
+=== memory.x
+
+This file outlines the flash/ram usage of your program. It is especially useful when using link:https://github.com/embassy-rs/nrf-softdevice[nrf-softdevice] on an nRF5x.
+
+Here is an example for using S140 with an nRF52840:
+
+[source,x]
+----
+MEMORY
+{
+  /* NOTE 1 K = 1 KiBi = 1024 bytes */
+  /* These values correspond to the NRF52840 with Softdevices S140 7.0.1 */
+  FLASH : ORIGIN = 0x00027000, LENGTH = 868K
+  RAM : ORIGIN = 0x20020000, LENGTH = 128K
+}
+----
+
+=== rust-toolchain.toml
+
+This file configures the rust version and configuration to use.
+
+A minimal example:
+
+[source,toml]
+----
+[toolchain]
+channel = "nightly-2023-08-19" # <- as of writing, this is the exact rust version embassy uses
+components = [ "rust-src", "rustfmt" ] # <- optionally add "llvm-tools-preview" for some extra features like "cargo size"
+targets = [
+    "thumbv6m-none-eabi" # <-change for your platform
+]
+----
+
 == How to deploy to RP2040 without a debugging probe.
 
 Install link:https://github.com/JoNil/elf2uf2-rs[elf2uf2-rs] for converting the generated elf binary into a uf2 file.
@@ -36,3 +117,47 @@ For Cortex-M targets, consider making sure that ALL of the following features ar
 * `nightly`
 
 For Xtensa ESP32, consider using the executors and `#[main]` macro provided by your appropriate link:https://crates.io/crates/esp-hal-common[HAL crate].
+
+== Why is my binary so big?
+
+The first step to managing your binary size is to set up your link:https://doc.rust-lang.org/cargo/reference/profiles.html[profiles].
+
+[source,toml]
+----
+[profile.release]
+debug = false
+lto = true
+opt-level = "s"
+incremental = true
+----
+
+All of these flags are elaborated on in the Rust Book page linked above.
+
+=== My binary is still big... filled with `std::fmt` stuff!
+
+This means your code is sufficiently complex that `panic!` invocation's formatting requirements could not be optimized out, despite your usage of `panic-halt` or `panic-reset`.
+
+You can remedy this by adding the following to your `.cargo/config.toml`:
+
+[source,toml]
+----
+[unstable]
+build-std = ["core"]
+build-std-features = ["panic_immediate_abort"]
+----
+
+This replaces all panics with a `UDF` (undefined) instruction.
+
+Depending on your chipset, this will exhibit different behavior.
+
+Refer to the spec for your chipset, but for `thumbv6m`, it results in a hardfault. Which can be configured like so:
+
+[source,rust]
+----
+#[exception]
+unsafe fn HardFault(_frame: &ExceptionFrame) -> ! {
+    SCB::sys_reset() // <- you could do something other than reset
+}
+----
+
+Refer to cortex-m's link:https://docs.rs/cortex-m-rt/latest/cortex_m_rt/attr.exception.html[exception handling] for more info.