Merge pull request #2710 from adamgreig/stm32-sai

      STM32: SAI: Fix MCKDIV for SAI v3/v4
  

1 files changed, 143 insertions, 1 deletions

diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index 02f96f8a9..294620031 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -386,6 +386,7 @@ impl OutputDrive {
 /// Master clock divider.
 #[derive(Copy, Clone, PartialEq)]
 #[allow(missing_docs)]
+#[cfg(any(sai_v1, sai_v2))]
 pub enum MasterClockDivider {
     MasterClockDisabled,
     Div1,
@@ -406,8 +407,79 @@ pub enum MasterClockDivider {
     Div30,
 }
 
+/// Master clock divider.
+#[derive(Copy, Clone, PartialEq)]
+#[allow(missing_docs)]
+#[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
+pub enum MasterClockDivider {
+    MasterClockDisabled,
+    Div1,
+    Div2,
+    Div3,
+    Div4,
+    Div5,
+    Div6,
+    Div7,
+    Div8,
+    Div9,
+    Div10,
+    Div11,
+    Div12,
+    Div13,
+    Div14,
+    Div15,
+    Div16,
+    Div17,
+    Div18,
+    Div19,
+    Div20,
+    Div21,
+    Div22,
+    Div23,
+    Div24,
+    Div25,
+    Div26,
+    Div27,
+    Div28,
+    Div29,
+    Div30,
+    Div31,
+    Div32,
+    Div33,
+    Div34,
+    Div35,
+    Div36,
+    Div37,
+    Div38,
+    Div39,
+    Div40,
+    Div41,
+    Div42,
+    Div43,
+    Div44,
+    Div45,
+    Div46,
+    Div47,
+    Div48,
+    Div49,
+    Div50,
+    Div51,
+    Div52,
+    Div53,
+    Div54,
+    Div55,
+    Div56,
+    Div57,
+    Div58,
+    Div59,
+    Div60,
+    Div61,
+    Div62,
+    Div63,
+}
+
 impl MasterClockDivider {
-    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
+    #[cfg(any(sai_v1, sai_v2))]
     const fn mckdiv(&self) -> u8 {
         match self {
             MasterClockDivider::MasterClockDisabled => 0,
@@ -429,6 +501,76 @@ impl MasterClockDivider {
             MasterClockDivider::Div30 => 15,
         }
     }
+
+    #[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
+    const fn mckdiv(&self) -> u8 {
+        match self {
+            MasterClockDivider::MasterClockDisabled => 0,
+            MasterClockDivider::Div1 => 1,
+            MasterClockDivider::Div2 => 2,
+            MasterClockDivider::Div3 => 3,
+            MasterClockDivider::Div4 => 4,
+            MasterClockDivider::Div5 => 5,
+            MasterClockDivider::Div6 => 6,
+            MasterClockDivider::Div7 => 7,
+            MasterClockDivider::Div8 => 8,
+            MasterClockDivider::Div9 => 9,
+            MasterClockDivider::Div10 => 10,
+            MasterClockDivider::Div11 => 11,
+            MasterClockDivider::Div12 => 12,
+            MasterClockDivider::Div13 => 13,
+            MasterClockDivider::Div14 => 14,
+            MasterClockDivider::Div15 => 15,
+            MasterClockDivider::Div16 => 16,
+            MasterClockDivider::Div17 => 17,
+            MasterClockDivider::Div18 => 18,
+            MasterClockDivider::Div19 => 19,
+            MasterClockDivider::Div20 => 20,
+            MasterClockDivider::Div21 => 21,
+            MasterClockDivider::Div22 => 22,
+            MasterClockDivider::Div23 => 23,
+            MasterClockDivider::Div24 => 24,
+            MasterClockDivider::Div25 => 25,
+            MasterClockDivider::Div26 => 26,
+            MasterClockDivider::Div27 => 27,
+            MasterClockDivider::Div28 => 28,
+            MasterClockDivider::Div29 => 29,
+            MasterClockDivider::Div30 => 30,
+            MasterClockDivider::Div31 => 31,
+            MasterClockDivider::Div32 => 32,
+            MasterClockDivider::Div33 => 33,
+            MasterClockDivider::Div34 => 34,
+            MasterClockDivider::Div35 => 35,
+            MasterClockDivider::Div36 => 36,
+            MasterClockDivider::Div37 => 37,
+            MasterClockDivider::Div38 => 38,
+            MasterClockDivider::Div39 => 39,
+            MasterClockDivider::Div40 => 40,
+            MasterClockDivider::Div41 => 41,
+            MasterClockDivider::Div42 => 42,
+            MasterClockDivider::Div43 => 43,
+            MasterClockDivider::Div44 => 44,
+            MasterClockDivider::Div45 => 45,
+            MasterClockDivider::Div46 => 46,
+            MasterClockDivider::Div47 => 47,
+            MasterClockDivider::Div48 => 48,
+            MasterClockDivider::Div49 => 49,
+            MasterClockDivider::Div50 => 50,
+            MasterClockDivider::Div51 => 51,
+            MasterClockDivider::Div52 => 52,
+            MasterClockDivider::Div53 => 53,
+            MasterClockDivider::Div54 => 54,
+            MasterClockDivider::Div55 => 55,
+            MasterClockDivider::Div56 => 56,
+            MasterClockDivider::Div57 => 57,
+            MasterClockDivider::Div58 => 58,
+            MasterClockDivider::Div59 => 59,
+            MasterClockDivider::Div60 => 60,
+            MasterClockDivider::Div61 => 61,
+            MasterClockDivider::Div62 => 62,
+            MasterClockDivider::Div63 => 63,
+        }
+    }
 }
 
 /// [`SAI`] configuration.