diff options
| author | pennae <[email protected]> | 2023-05-13 19:07:36 +0200 |
|---|---|---|
| committer | pennae <[email protected]> | 2023-05-17 19:28:51 +0200 |
| commit | 5bbed315131991745efacbaa5c384e11f704923b (patch) | |
| tree | a39ecc19e7202616b4ab4bf45c1e402cec05d6a2 | |
| parent | d3494a4bdf513d5b61210180fa227a9bd99935ca (diff) | |
rp/clocks: provide fbdiv, not vco_freq
solvers usually output fbdiv directly, using vco_freq to get back to
fbdiv is not all that necessary or useful. both vco_freq and fbdiv have
hidden constraints, but vco_freq is a lot less accurate because the
fbdiv value resulting from the division may be off by almost a full
ref_freq's worth of frequency.
also fixes the usb pll config, which ran the pll vco way out of (below)
spec.
| -rw-r--r-- | embassy-rp/src/clocks.rs | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/embassy-rp/src/clocks.rs b/embassy-rp/src/clocks.rs index bfca3f02e..63f70cec4 100644 --- a/embassy-rp/src/clocks.rs +++ b/embassy-rp/src/clocks.rs | |||
| @@ -37,15 +37,15 @@ impl ClockConfig { | |||
| 37 | clock_type: ExternalClock::Crystal, | 37 | clock_type: ExternalClock::Crystal, |
| 38 | sys_pll: Some(PllConfig { | 38 | sys_pll: Some(PllConfig { |
| 39 | refdiv: 1, | 39 | refdiv: 1, |
| 40 | vco_freq: 1500_000_000, | 40 | fbdiv: 125, |
| 41 | post_div1: 6, | 41 | post_div1: 6, |
| 42 | post_div2: 2, | 42 | post_div2: 2, |
| 43 | }), | 43 | }), |
| 44 | usb_pll: Some(PllConfig { | 44 | usb_pll: Some(PllConfig { |
| 45 | refdiv: 1, | 45 | refdiv: 1, |
| 46 | vco_freq: 480_000_000, | 46 | fbdiv: 120, |
| 47 | post_div1: 5, | 47 | post_div1: 6, |
| 48 | post_div2: 2, | 48 | post_div2: 5, |
| 49 | }), | 49 | }), |
| 50 | }), | 50 | }), |
| 51 | ref_clk: RefClkConfig { | 51 | ref_clk: RefClkConfig { |
| @@ -126,7 +126,7 @@ pub struct XoscConfig { | |||
| 126 | 126 | ||
| 127 | pub struct PllConfig { | 127 | pub struct PllConfig { |
| 128 | pub refdiv: u32, | 128 | pub refdiv: u32, |
| 129 | pub vco_freq: u32, | 129 | pub fbdiv: u16, |
| 130 | pub post_div1: u8, | 130 | pub post_div1: u8, |
| 131 | pub post_div2: u8, | 131 | pub post_div2: u8, |
| 132 | } | 132 | } |
| @@ -587,16 +587,15 @@ unsafe fn start_xosc(crystal_hz: u32) { | |||
| 587 | unsafe fn configure_pll(p: pac::pll::Pll, input_freq: u32, config: PllConfig) { | 587 | unsafe fn configure_pll(p: pac::pll::Pll, input_freq: u32, config: PllConfig) { |
| 588 | let ref_freq = input_freq / config.refdiv; | 588 | let ref_freq = input_freq / config.refdiv; |
| 589 | 589 | ||
| 590 | let fbdiv = config.vco_freq / ref_freq; | 590 | assert!(config.fbdiv >= 16 && config.fbdiv <= 320); |
| 591 | assert!(fbdiv >= 16 && fbdiv <= 320); | ||
| 592 | assert!(config.post_div1 >= 1 && config.post_div1 <= 7); | 591 | assert!(config.post_div1 >= 1 && config.post_div1 <= 7); |
| 593 | assert!(config.post_div2 >= 1 && config.post_div2 <= 7); | 592 | assert!(config.post_div2 >= 1 && config.post_div2 <= 7); |
| 594 | assert!(config.post_div2 <= config.post_div1); | 593 | assert!(config.post_div2 <= config.post_div1); |
| 595 | assert!(ref_freq <= (config.vco_freq / 16)); | 594 | assert!(ref_freq >= 5_000_000 && ref_freq <= 800_000_000); |
| 596 | 595 | ||
| 597 | // Load VCO-related dividers before starting VCO | 596 | // Load VCO-related dividers before starting VCO |
| 598 | p.cs().write(|w| w.set_refdiv(config.refdiv as _)); | 597 | p.cs().write(|w| w.set_refdiv(config.refdiv as _)); |
| 599 | p.fbdiv_int().write(|w| w.set_fbdiv_int(fbdiv as _)); | 598 | p.fbdiv_int().write(|w| w.set_fbdiv_int(config.fbdiv)); |
| 600 | 599 | ||
| 601 | // Turn on PLL | 600 | // Turn on PLL |
| 602 | p.pwr().modify(|w| { | 601 | p.pwr().modify(|w| { |
