Merge #1353

1353: Add empty test binary for riscv r=Dirbaio a=royb3

As discussed with `@Dirbaio,` this empty test binary should cause a build to fail when it is not possible to build or link a riscv binary.

Co-authored-by: Roy Buitenhuis <[email protected]>

6 files changed, 90 insertions, 0 deletions

diff --git a/ci.sh b/ci.sh
index f81b34c05..1b3fac8bc 100755
--- a/ci.sh
+++ b/ci.sh
@@ -124,6 +124,7 @@ cargo batch  \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u585ai --out-dir out/tests/iot-stm32u585ai \
     --- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/rpi-pico \
     --- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \
+    --- build --release --manifest-path tests/riscv32/Cargo.toml --target riscv32imac-unknown-none-elf \
     $BUILD_EXTRA
 
 
diff --git a/tests/riscv32/.cargo/config.toml b/tests/riscv32/.cargo/config.toml
new file mode 100644
index 000000000..58299b54e
--- /dev/null
+++ b/tests/riscv32/.cargo/config.toml
@@ -0,0 +1,5 @@
+[target.riscv32imac-unknown-none-elf]
+runner = "true"
+
+[build]
+target = "riscv32imac-unknown-none-elf"
diff --git a/tests/riscv32/Cargo.toml b/tests/riscv32/Cargo.toml
new file mode 100644
index 000000000..885776ae6
--- /dev/null
+++ b/tests/riscv32/Cargo.toml
@@ -0,0 +1,46 @@
+[package]
+edition = "2021"
+name = "embassy-riscv-tests"
+version = "0.1.0"
+license = "MIT OR Apache-2.0"
+
+[dependencies]
+critical-section = { version = "1.1.1", features = ["restore-state-bool"] }
+embassy-sync = { version = "0.1.0", path = "../../embassy-sync" }
+embassy-executor = { version = "0.1.0", path = "../../embassy-executor", features = ["arch-riscv32", "nightly", "executor-thread"] }
+embassy-time = { version = "0.1.0", path = "../../embassy-time" }
+embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
+
+riscv-rt = "0.11"
+riscv = { version = "0.10", features = ["critical-section-single-hart"] }
+
+
+[profile.dev]
+debug = 2
+debug-assertions = true
+opt-level = 's'
+overflow-checks = true
+
+[profile.release]
+codegen-units = 1
+debug = 2
+debug-assertions = false
+incremental = false
+lto = "fat"
+opt-level = 's'
+overflow-checks = false
+
+# do not optimize proc-macro crates = faster builds from scratch
+[profile.dev.build-override]
+codegen-units = 8
+debug = false
+debug-assertions = false
+opt-level = 0
+overflow-checks = false
+
+[profile.release.build-override]
+codegen-units = 8
+debug = false
+debug-assertions = false
+opt-level = 0
+overflow-checks = false
diff --git a/tests/riscv32/build.rs b/tests/riscv32/build.rs
new file mode 100644
index 000000000..e4a26c4a1
--- /dev/null
+++ b/tests/riscv32/build.rs
@@ -0,0 +1,8 @@
+use std::error::Error;
+
+fn main() -> Result<(), Box<dyn Error>> {
+    println!("cargo:rustc-link-arg-bins=-Tmemory.x");
+    println!("cargo:rustc-link-arg-bins=-Tlink.x");
+
+    Ok(())
+}
diff --git a/tests/riscv32/memory.x b/tests/riscv32/memory.x
new file mode 100644
index 000000000..316d577d4
--- /dev/null
+++ b/tests/riscv32/memory.x
@@ -0,0 +1,14 @@
+MEMORY
+{
+  ROM : ORIGIN = 0x80000000, LENGTH = 0x00020000
+  RAM : ORIGIN = 0x84000000, LENGTH = 0x00008000
+}
+
+REGION_ALIAS("REGION_TEXT", ROM);
+REGION_ALIAS("REGION_RODATA", ROM);
+REGION_ALIAS("REGION_DATA", RAM);
+REGION_ALIAS("REGION_BSS", RAM);
+REGION_ALIAS("REGION_HEAP", RAM);
+REGION_ALIAS("REGION_STACK", RAM);
+
+_stack_start = ORIGIN(RAM) + LENGTH(RAM) - 4;
diff --git a/tests/riscv32/src/bin/empty.rs b/tests/riscv32/src/bin/empty.rs
new file mode 100644
index 000000000..1874caec4
--- /dev/null
+++ b/tests/riscv32/src/bin/empty.rs
@@ -0,0 +1,16 @@
+#![no_std]
+#![no_main]
+#![feature(type_alias_impl_trait)]
+
+use embassy_executor::Spawner;
+
+#[panic_handler]
+fn panic(_info: &core::panic::PanicInfo) -> ! {
+    loop {}
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Don't do anything, just make sure it compiles.
+    loop {}
+}