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authorxoviat <[email protected]>2025-11-15 13:58:20 -0600
committerGitHub <[email protected]>2025-11-15 13:58:20 -0600
commit5e0867f5620e0a0e7c93a7f80a20643cb2d87957 (patch)
tree55df837419491b4e7e59ab9d0e37bbca69ddaeb8
parentdd0e6889c791d1d58d86ec9d5951c2232f7bf407 (diff)
Update ADC clock frequency constant usage
-rw-r--r--embassy-stm32/src/adc/v2.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 75b1e485b..341b15674 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -58,7 +58,7 @@ fn from_pclk2(freq: Hertz) -> Adcpre {
58 // Datasheet for both F4 and F7 specifies min frequency 0.6 MHz, typ freq. 30 MHz and max 36 MHz. 58 // Datasheet for both F4 and F7 specifies min frequency 0.6 MHz, typ freq. 30 MHz and max 36 MHz.
59 #[cfg(not(stm32f2))] 59 #[cfg(not(stm32f2))]
60 const MAX_FREQUENCY: Hertz = Hertz(36_000_000); 60 const MAX_FREQUENCY: Hertz = Hertz(36_000_000);
61 let raw_div = rcc::raw_prescaler(freq.0, MAX_ADC_CLK_FREQ.0); 61 let raw_div = rcc::raw_prescaler(freq.0, MAX_FREQUENCY.0);
62 match raw_div { 62 match raw_div {
63 0..=1 => Adcpre::DIV2, 63 0..=1 => Adcpre::DIV2,
64 2..=3 => Adcpre::DIV4, 64 2..=3 => Adcpre::DIV4,