stm32 adc v3 read_async

1 files changed, 176 insertions, 16 deletions

diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 398c57a92..559751555 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,8 +1,10 @@
 use cfg_if::cfg_if;
 use embassy_hal_internal::into_ref;
 
-use super::blocking_delay_us;
-use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
+use super::{
+    blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
+};
+use crate::dma::Transfer;
 use crate::{rcc, Peripheral};
 
 /// Default VREF voltage used for sample conversion to millivolts.
@@ -12,7 +14,7 @@ pub const VREF_CALIB_MV: u32 = 3000;
 
 pub struct VrefInt;
 impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> super::SealedAdcChannel<T> for VrefInt {
+impl<T: Instance> SealedAdcChannel<T> for VrefInt {
     fn channel(&self) -> u8 {
         cfg_if! {
             if #[cfg(adc_g0)] {
@@ -31,7 +33,7 @@ impl<T: Instance> super::SealedAdcChannel<T> for VrefInt {
 
 pub struct Temperature;
 impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
+impl<T: Instance> SealedAdcChannel<T> for Temperature {
     fn channel(&self) -> u8 {
         cfg_if! {
             if #[cfg(adc_g0)] {
@@ -50,7 +52,7 @@ impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
 
 pub struct Vbat;
 impl<T: Instance> AdcChannel<T> for Vbat {}
-impl<T: Instance> super::SealedAdcChannel<T> for Vbat {
+impl<T: Instance> SealedAdcChannel<T> for Vbat {
     fn channel(&self) -> u8 {
         cfg_if! {
             if #[cfg(adc_g0)] {
@@ -101,6 +103,7 @@ impl<'d, T: Instance> Adc<'d, T> {
             reg.set_advregen(true);
         });
 
+        // If this is false then each ADC_CHSELR bit enables an input channel.
         #[cfg(any(adc_g0, adc_u0))]
         T::regs().cfgr1().modify(|reg| {
             reg.set_chselrmod(false);
@@ -124,6 +127,28 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
     }
 
+    // Enable ADC only when it is not already running.
+    fn enable(&mut self) {
+        // Make sure bits are off
+        while T::regs().cr().read().addis() {
+            // spin
+        }
+
+        if !T::regs().cr().read().aden() {
+            // Enable ADC
+            T::regs().isr().modify(|reg| {
+                reg.set_adrdy(true);
+            });
+            T::regs().cr().modify(|reg| {
+                reg.set_aden(true);
+            });
+
+            while !T::regs().isr().read().adrdy() {
+                // spin
+            }
+        }
+    }
+
     pub fn enable_vrefint(&self) -> VrefInt {
         #[cfg(not(any(adc_g0, adc_u0)))]
         T::common_regs().ccr().modify(|reg| {
@@ -181,10 +206,17 @@ impl<'d, T: Instance> Adc<'d, T> {
         Vbat {}
     }
 
+    /// Set the ADC sample time.
     pub fn set_sample_time(&mut self, sample_time: SampleTime) {
         self.sample_time = sample_time;
     }
 
+    /// Get the ADC sample time.
+    pub fn sample_time(&self) -> SampleTime {
+        self.sample_time
+    }
+
+    /// Set the ADC resolution.
     pub fn set_resolution(&mut self, resolution: Resolution) {
         #[cfg(not(any(adc_g0, adc_u0)))]
         T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
@@ -220,24 +252,139 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().dr().read().0 as u16
     }
 
+    /// Read an ADC channel.
     pub fn read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        // Make sure bits are off
-        while T::regs().cr().read().addis() {
-            // spin
+        self.read_channel(channel)
+    }
+
+    /// Asynchronously read from sequence of ADC channels.
+    pub async fn read_async(
+        &mut self,
+        rx_dma: &mut impl RxDma<T>,
+        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
+        data: &mut [u16],
+    ) {
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+
+        // Ensure no conversions are ongoing and ADC is enabled.
+        Self::cancel_conversions();
+        self.enable();
+
+        // Set sequence length
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::regs().sqr1().modify(|w| {
+            w.set_l(sequence.len() as u8 - 1);
+        });
+
+        #[cfg(any(adc_g0, adc_u0))]
+        let mut channel_mask = 0;
+
+        // Configure channels and ranks
+        for (_i, (channel, sample_time)) in sequence.enumerate() {
+            Self::configure_channel(channel, sample_time);
+
+            // Each channel is sampled according to sequence
+            #[cfg(not(any(adc_g0, adc_u0)))]
+            match _i {
+                0..=3 => {
+                    T::regs().sqr1().modify(|w| {
+                        w.set_sq(_i, channel.channel());
+                    });
+                }
+                4..=8 => {
+                    T::regs().sqr2().modify(|w| {
+                        w.set_sq(_i - 4, channel.channel());
+                    });
+                }
+                9..=13 => {
+                    T::regs().sqr3().modify(|w| {
+                        w.set_sq(_i - 9, channel.channel());
+                    });
+                }
+                14..=15 => {
+                    T::regs().sqr4().modify(|w| {
+                        w.set_sq(_i - 14, channel.channel());
+                    });
+                }
+                _ => unreachable!(),
+            }
+
+            #[cfg(any(adc_g0, adc_u0))]
+            {
+                channel_mask |= 1 << channel.channel();
+            }
         }
 
-        // Enable ADC
+        // On G0 and U0 enabled channels are sampled from 0 to last channel.
+        // It is possible to add up to 8 sequences if CHSELRMOD = 1.
+        // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
+        #[cfg(any(adc_g0, adc_u0))]
+        T::regs().chselr().modify(|reg| {
+            reg.set_chsel(channel_mask);
+        });
+
+        // Set continuous mode with oneshot dma.
+        // Clear overrun flag before starting transfer.
         T::regs().isr().modify(|reg| {
-            reg.set_adrdy(true);
+            reg.set_ovr(true);
+        });
+
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::regs().cfgr().modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            // Oneshot mode
+            reg.set_dmacfg(false);
+            reg.set_dmaen(true);
         });
+        #[cfg(any(adc_g0, adc_u0))]
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            // Oneshot mode
+            reg.set_dmacfg(false);
+            reg.set_dmaen(true);
+        });
+
+        let request = rx_dma.request();
+        let transfer = unsafe {
+            Transfer::new_read(
+                rx_dma,
+                request,
+                T::regs().dr().as_ptr() as *mut u16,
+                data,
+                Default::default(),
+            )
+        };
+
+        // Start conversion
         T::regs().cr().modify(|reg| {
-            reg.set_aden(true);
+            reg.set_adstart(true);
         });
 
-        while !T::regs().isr().read().adrdy() {
-            // spin
-        }
+        // Wait for conversion sequence to finish.
+        transfer.await;
 
+        // Ensure conversions are finished.
+        Self::cancel_conversions();
+
+        // Reset configuration.
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::regs().cfgr().modify(|reg| {
+            reg.set_cont(false);
+        });
+        #[cfg(any(adc_g0, adc_u0))]
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_cont(false);
+        });
+    }
+
+    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
         // RM0492, RM0481, etc.
         // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
         #[cfg(adc_h5)]
@@ -246,7 +393,12 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
 
         // Configure channel
-        Self::set_channel_sample_time(channel.channel(), self.sample_time);
+        Self::set_channel_sample_time(channel.channel(), sample_time);
+    }
+
+    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+        self.enable();
+        Self::configure_channel(channel, self.sample_time);
 
         // Select channel
         #[cfg(not(any(adc_g0, adc_u0)))]
@@ -262,7 +414,6 @@ impl<'d, T: Instance> Adc<'d, T> {
         // STM32G4: Section 2.7.3
         #[cfg(any(rcc_l4, rcc_g4))]
         let _ = self.convert();
-
         let val = self.convert();
 
         T::regs().cr().modify(|reg| reg.set_addis(true));
@@ -294,4 +445,13 @@ impl<'d, T: Instance> Adc<'d, T> {
             }
         }
     }
+
+    fn cancel_conversions() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(true);
+            });
+            while T::regs().cr().read().adstart() {}
+        }
+    }
 }