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authorPatrick Oppenlander <[email protected]>2023-02-06 09:44:13 +1100
committerPatrick Oppenlander <[email protected]>2023-02-06 09:44:15 +1100
commit64ebb9b7fee1fec62eacc1064a7458a6e6b07048 (patch)
tree6020b7adeb42cf5e261f53f94b386d79496a0688
parent9af25c3396423036d0092a5f32f2d09b05a4e910 (diff)
stm32/usart: implement stop_bits configuration
-rw-r--r--embassy-stm32/src/usart/mod.rs9
1 files changed, 8 insertions, 1 deletions
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 20f4eedeb..b18b646ba 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -770,7 +770,14 @@ fn configure(r: Regs, config: &Config, pclk_freq: Hertz, multiplier: u32, enable
770 770
771 unsafe { 771 unsafe {
772 r.brr().write_value(regs::Brr(div)); 772 r.brr().write_value(regs::Brr(div));
773 r.cr2().write(|_w| {}); 773 r.cr2().write(|w| {
774 w.set_stop(match config.stop_bits {
775 StopBits::STOP0P5 => vals::Stop::STOP0P5,
776 StopBits::STOP1 => vals::Stop::STOP1,
777 StopBits::STOP1P5 => vals::Stop::STOP1P5,
778 StopBits::STOP2 => vals::Stop::STOP2,
779 });
780 });
774 r.cr1().write(|w| { 781 r.cr1().write(|w| {
775 // enable uart 782 // enable uart
776 w.set_ue(true); 783 w.set_ue(true);