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authorDario Nieuwenhuis <[email protected]>2025-01-02 23:02:51 +0000
committerGitHub <[email protected]>2025-01-02 23:02:51 +0000
commit6824567307cb7c92833437988992d05cb7febcd2 (patch)
tree1a3d2f9ffd7327a7fe957fe46a8159f4e1425181
parentcefdbfab2f1efb0797f661a9d8cc0aa686fe881a (diff)
parentd36876042410b056d39dbb08a5d3125c103ea170 (diff)
Merge pull request #3711 from chanterheld/feature/flash_stm32g0_dualbank
embassy-stm32 support g0 second flash bank
-rw-r--r--embassy-stm32/Cargo.toml4
-rw-r--r--embassy-stm32/src/flash/g.rs19
-rw-r--r--embassy-stm32/src/flash/mod.rs6
3 files changed, 22 insertions, 7 deletions
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index f35271016..da5e18b44 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -73,7 +73,7 @@ rand_core = "0.6.3"
73sdio-host = "0.5.0" 73sdio-host = "0.5.0"
74critical-section = "1.1" 74critical-section = "1.1"
75#stm32-metapac = { version = "15" } 75#stm32-metapac = { version = "15" }
76stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-392e41259ffc5ffbfd79169ee80451114fb367fe" } 76stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d87131cfec93a6dbd21422ac36d43ce9562aab7f" }
77 77
78vcell = "0.1.3" 78vcell = "0.1.3"
79nb = "1.0.0" 79nb = "1.0.0"
@@ -102,7 +102,7 @@ proc-macro2 = "1.0.36"
102quote = "1.0.15" 102quote = "1.0.15"
103 103
104#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]} 104#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
105stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-392e41259ffc5ffbfd79169ee80451114fb367fe", default-features = false, features = ["metadata"] } 105stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d87131cfec93a6dbd21422ac36d43ce9562aab7f", default-features = false, features = ["metadata"] }
106 106
107[features] 107[features]
108default = ["rt"] 108default = ["rt"]
diff --git a/embassy-stm32/src/flash/g.rs b/embassy-stm32/src/flash/g.rs
index 01a0c603f..83663743c 100644
--- a/embassy-stm32/src/flash/g.rs
+++ b/embassy-stm32/src/flash/g.rs
@@ -20,7 +20,7 @@ pub(crate) unsafe fn lock() {
20} 20}
21pub(crate) unsafe fn unlock() { 21pub(crate) unsafe fn unlock() {
22 // Wait, while the memory interface is busy. 22 // Wait, while the memory interface is busy.
23 while pac::FLASH.sr().read().bsy() {} 23 wait_busy();
24 24
25 // Unlock flash 25 // Unlock flash
26 if pac::FLASH.cr().read().lock() { 26 if pac::FLASH.cr().read().lock() {
@@ -53,12 +53,17 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
53 53
54pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> { 54pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
55 let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32; 55 let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
56 while pac::FLASH.sr().read().bsy() {} 56 wait_busy();
57 clear_all_err(); 57 clear_all_err();
58 58
59 interrupt::free(|_| { 59 interrupt::free(|_| {
60 pac::FLASH.cr().modify(|w| { 60 pac::FLASH.cr().modify(|w| {
61 w.set_per(true); 61 w.set_per(true);
62 #[cfg(any(flash_g0x0, flash_g0x1, flash_g4c3))]
63 w.set_bker(sector.bank == crate::flash::FlashBank::Bank2);
64 #[cfg(flash_g0x0)]
65 w.set_pnb(idx as u16);
66 #[cfg(not(flash_g0x0))]
62 w.set_pnb(idx as u8); 67 w.set_pnb(idx as u8);
63 w.set_strt(true); 68 w.set_strt(true);
64 }); 69 });
@@ -94,3 +99,13 @@ pub(crate) unsafe fn clear_all_err() {
94 // This clears all "write 1 to clear" bits. 99 // This clears all "write 1 to clear" bits.
95 pac::FLASH.sr().modify(|_| {}); 100 pac::FLASH.sr().modify(|_| {});
96} 101}
102
103#[cfg(any(flash_g0x0, flash_g0x1))]
104fn wait_busy() {
105 while pac::FLASH.sr().read().bsy() | pac::FLASH.sr().read().bsy2() {}
106}
107
108#[cfg(not(any(flash_g0x0, flash_g0x1)))]
109fn wait_busy() {
110 while pac::FLASH.sr().read().bsy() {}
111}
diff --git a/embassy-stm32/src/flash/mod.rs b/embassy-stm32/src/flash/mod.rs
index 88fe6a291..aef1f1482 100644
--- a/embassy-stm32/src/flash/mod.rs
+++ b/embassy-stm32/src/flash/mod.rs
@@ -97,7 +97,7 @@ pub enum FlashBank {
97#[cfg_attr(flash_f2, path = "f2.rs")] 97#[cfg_attr(flash_f2, path = "f2.rs")]
98#[cfg_attr(flash_f4, path = "f4.rs")] 98#[cfg_attr(flash_f4, path = "f4.rs")]
99#[cfg_attr(flash_f7, path = "f7.rs")] 99#[cfg_attr(flash_f7, path = "f7.rs")]
100#[cfg_attr(any(flash_g0, flash_g4c2, flash_g4c3, flash_g4c4), path = "g.rs")] 100#[cfg_attr(any(flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4), path = "g.rs")]
101#[cfg_attr(flash_h7, path = "h7.rs")] 101#[cfg_attr(flash_h7, path = "h7.rs")]
102#[cfg_attr(flash_h7ab, path = "h7.rs")] 102#[cfg_attr(flash_h7ab, path = "h7.rs")]
103#[cfg_attr(flash_u5, path = "u5.rs")] 103#[cfg_attr(flash_u5, path = "u5.rs")]
@@ -107,8 +107,8 @@ pub enum FlashBank {
107#[cfg_attr( 107#[cfg_attr(
108 not(any( 108 not(any(
109 flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb, flash_f0, flash_f1, flash_f2, flash_f3, flash_f4, 109 flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb, flash_f0, flash_f1, flash_f2, flash_f3, flash_f4,
110 flash_f7, flash_g0, flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5, flash_h50, flash_u0, 110 flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5,
111 flash_h5, 111 flash_h50, flash_u0, flash_h5,
112 )), 112 )),
113 path = "other.rs" 113 path = "other.rs"
114)] 114)]