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authorGrant Miller <[email protected]>2022-03-14 14:55:05 -0500
committerGrant Miller <[email protected]>2022-03-14 15:56:08 -0500
commit683c11f3997bc550d5ed716ee6e3059af4a8051c (patch)
treebc9adf334c90bb776309f9c9b5a648cfa3374a7c
parent3ae0923d453d4f7f38326d136aa00246ae63c53d (diff)
Call `set_word_size` before disabling SPE
-rw-r--r--embassy-stm32/src/spi/v1.rs6
-rw-r--r--embassy-stm32/src/spi/v2.rs6
2 files changed, 6 insertions, 6 deletions
diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs
index 5dd4dc2db..33cf9c50e 100644
--- a/embassy-stm32/src/spi/v1.rs
+++ b/embassy-stm32/src/spi/v1.rs
@@ -10,12 +10,12 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
10 where 10 where
11 Tx: TxDma<T>, 11 Tx: TxDma<T>,
12 { 12 {
13 self.set_word_size(WordSize::EightBit);
13 unsafe { 14 unsafe {
14 T::regs().cr1().modify(|w| { 15 T::regs().cr1().modify(|w| {
15 w.set_spe(false); 16 w.set_spe(false);
16 }); 17 });
17 } 18 }
18 self.set_word_size(WordSize::EightBit);
19 19
20 let tx_request = self.txdma.request(); 20 let tx_request = self.txdma.request();
21 let tx_dst = T::regs().tx_ptr(); 21 let tx_dst = T::regs().tx_ptr();
@@ -43,6 +43,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
43 Tx: TxDma<T>, 43 Tx: TxDma<T>,
44 Rx: RxDma<T>, 44 Rx: RxDma<T>,
45 { 45 {
46 self.set_word_size(WordSize::EightBit);
46 unsafe { 47 unsafe {
47 T::regs().cr1().modify(|w| { 48 T::regs().cr1().modify(|w| {
48 w.set_spe(false); 49 w.set_spe(false);
@@ -51,7 +52,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
51 reg.set_rxdmaen(true); 52 reg.set_rxdmaen(true);
52 }); 53 });
53 } 54 }
54 self.set_word_size(WordSize::EightBit);
55 55
56 let (_, clock_byte_count) = slice_ptr_parts_mut(read); 56 let (_, clock_byte_count) = slice_ptr_parts_mut(read);
57 57
@@ -100,6 +100,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
100 let (_, tx_len) = slice_ptr_parts(write); 100 let (_, tx_len) = slice_ptr_parts(write);
101 assert_eq!(rx_len, tx_len); 101 assert_eq!(rx_len, tx_len);
102 102
103 self.set_word_size(WordSize::EightBit);
103 unsafe { 104 unsafe {
104 T::regs().cr1().modify(|w| { 105 T::regs().cr1().modify(|w| {
105 w.set_spe(false); 106 w.set_spe(false);
@@ -108,7 +109,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
108 reg.set_rxdmaen(true); 109 reg.set_rxdmaen(true);
109 }); 110 });
110 } 111 }
111 self.set_word_size(WordSize::EightBit);
112 112
113 let rx_request = self.rxdma.request(); 113 let rx_request = self.rxdma.request();
114 let rx_src = T::regs().rx_ptr(); 114 let rx_src = T::regs().rx_ptr();
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index 3820fcac1..7ffc52be8 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -10,6 +10,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
10 where 10 where
11 Tx: TxDma<T>, 11 Tx: TxDma<T>,
12 { 12 {
13 self.set_word_size(WordSize::EightBit);
13 unsafe { 14 unsafe {
14 T::regs().cr1().modify(|w| { 15 T::regs().cr1().modify(|w| {
15 w.set_spe(false); 16 w.set_spe(false);
@@ -20,7 +21,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
20 let _ = T::regs().dr().read(); 21 let _ = T::regs().dr().read();
21 } 22 }
22 } 23 }
23 self.set_word_size(WordSize::EightBit);
24 24
25 let tx_request = self.txdma.request(); 25 let tx_request = self.txdma.request();
26 let tx_dst = T::regs().tx_ptr(); 26 let tx_dst = T::regs().tx_ptr();
@@ -48,6 +48,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
48 Tx: TxDma<T>, 48 Tx: TxDma<T>,
49 Rx: RxDma<T>, 49 Rx: RxDma<T>,
50 { 50 {
51 self.set_word_size(WordSize::EightBit);
51 unsafe { 52 unsafe {
52 T::regs().cr1().modify(|w| { 53 T::regs().cr1().modify(|w| {
53 w.set_spe(false); 54 w.set_spe(false);
@@ -56,7 +57,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
56 reg.set_rxdmaen(true); 57 reg.set_rxdmaen(true);
57 }); 58 });
58 } 59 }
59 self.set_word_size(WordSize::EightBit);
60 60
61 let (_, clock_byte_count) = slice_ptr_parts_mut(read); 61 let (_, clock_byte_count) = slice_ptr_parts_mut(read);
62 62
@@ -105,6 +105,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
105 let (_, tx_len) = slice_ptr_parts(write); 105 let (_, tx_len) = slice_ptr_parts(write);
106 assert_eq!(rx_len, tx_len); 106 assert_eq!(rx_len, tx_len);
107 107
108 self.set_word_size(WordSize::EightBit);
108 unsafe { 109 unsafe {
109 T::regs().cr1().modify(|w| { 110 T::regs().cr1().modify(|w| {
110 w.set_spe(false); 111 w.set_spe(false);
@@ -118,7 +119,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
118 let _ = T::regs().dr().read(); 119 let _ = T::regs().dr().read();
119 } 120 }
120 } 121 }
121 self.set_word_size(WordSize::EightBit);
122 122
123 let rx_request = self.rxdma.request(); 123 let rx_request = self.rxdma.request();
124 let rx_src = T::regs().rx_ptr(); 124 let rx_src = T::regs().rx_ptr();