diff options
| author | Riley Williams <[email protected]> | 2023-10-17 19:30:53 -0400 |
|---|---|---|
| committer | Riley Williams <[email protected]> | 2023-10-17 19:30:53 -0400 |
| commit | 6906cc9c2532fd690f4f43a0d97ea58f887e673b (patch) | |
| tree | 034aa76b99307216ffbcdf2bfaf0288002a123bb | |
| parent | cb211f88d3e225a2200a8a08d2265f48b7b472db (diff) | |
remove trailing spaces
| -rw-r--r-- | embassy-rp/src/pwm.rs | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/embassy-rp/src/pwm.rs b/embassy-rp/src/pwm.rs index 15655d24e..516b8254b 100644 --- a/embassy-rp/src/pwm.rs +++ b/embassy-rp/src/pwm.rs | |||
| @@ -33,15 +33,15 @@ pub struct Config { | |||
| 33 | /// A higher value will result in a slower output frequency. | 33 | /// A higher value will result in a slower output frequency. |
| 34 | pub divider: fixed::FixedU16<fixed::types::extra::U4>, | 34 | pub divider: fixed::FixedU16<fixed::types::extra::U4>, |
| 35 | /// The output on channel A goes high when `compare_a` is higher than the | 35 | /// The output on channel A goes high when `compare_a` is higher than the |
| 36 | /// counter. A compare of 0 will produce an always low output, while a | 36 | /// counter. A compare of 0 will produce an always low output, while a |
| 37 | /// compare of `top + 1` will produce an always high output. | 37 | /// compare of `top + 1` will produce an always high output. |
| 38 | pub compare_a: u16, | 38 | pub compare_a: u16, |
| 39 | /// The output on channel B goes high when `compare_b` is higher than the | 39 | /// The output on channel B goes high when `compare_b` is higher than the |
| 40 | /// counter. A compare of 0 will produce an always low output, while a | 40 | /// counter. A compare of 0 will produce an always low output, while a |
| 41 | /// compare of `top + 1` will produce an always high output. | 41 | /// compare of `top + 1` will produce an always high output. |
| 42 | pub compare_b: u16, | 42 | pub compare_b: u16, |
| 43 | /// The point at which the counter wraps, representing the maximum possible | 43 | /// The point at which the counter wraps, representing the maximum possible |
| 44 | /// period. The counter will either wrap to 0 or reverse depending on the | 44 | /// period. The counter will either wrap to 0 or reverse depending on the |
| 45 | /// setting of `phase_correct`. | 45 | /// setting of `phase_correct`. |
| 46 | pub top: u16, | 46 | pub top: u16, |
| 47 | } | 47 | } |
| @@ -196,8 +196,8 @@ impl<'d, T: Channel> Pwm<'d, T> { | |||
| 196 | }); | 196 | }); |
| 197 | } | 197 | } |
| 198 | 198 | ||
| 199 | /// Advances a slice’s output phase by one count while it is running | 199 | /// Advances a slice’s output phase by one count while it is running |
| 200 | /// by inserting a pulse into the clock enable. The counter | 200 | /// by inserting a pulse into the clock enable. The counter |
| 201 | /// will not count faster than once per cycle. | 201 | /// will not count faster than once per cycle. |
| 202 | #[inline] | 202 | #[inline] |
| 203 | pub fn phase_advance(&mut self) { | 203 | pub fn phase_advance(&mut self) { |
| @@ -206,7 +206,7 @@ impl<'d, T: Channel> Pwm<'d, T> { | |||
| 206 | while p.csr().read().ph_adv() {} | 206 | while p.csr().read().ph_adv() {} |
| 207 | } | 207 | } |
| 208 | 208 | ||
| 209 | /// Retards a slice’s output phase by one count while it is running | 209 | /// Retards a slice’s output phase by one count while it is running |
| 210 | /// by deleting a pulse from the clock enable. The counter will not | 210 | /// by deleting a pulse from the clock enable. The counter will not |
| 211 | /// count backward when clock enable is permenantly low. | 211 | /// count backward when clock enable is permenantly low. |
| 212 | #[inline] | 212 | #[inline] |
