eth-v2: Fix setting the registers for the descriptors

Also, the interrupts are set to 1 to clear, the manual could have helped
with that one...

2 files changed, 17 insertions, 12 deletions

diff --git a/embassy-stm32/src/eth/v2/descriptors.rs b/embassy-stm32/src/eth/v2/descriptors.rs
index 0c0046704..4ce90d1b5 100644
--- a/embassy-stm32/src/eth/v2/descriptors.rs
+++ b/embassy-stm32/src/eth/v2/descriptors.rs
@@ -102,10 +102,10 @@ impl<const N: usize> TDesRing<N> {
             let dma = ETH.ethernet_dma();
 
             dma.dmactx_dlar()
-                .write(|w| w.set_tdesla(&self.td as *const _ as u32));
+                .write(|w| w.0 = &self.td as *const _ as u32);
             dma.dmactx_rlr().write(|w| w.set_tdrl((N as u16) - 1));
             dma.dmactx_dtpr()
-                .write(|w| w.set_tdt(&self.td[0] as *const _ as u32));
+                .write(|w| w.0 = &self.td[0] as *const _ as u32);
         }
     }
 
@@ -148,7 +148,7 @@ impl<const N: usize> TDesRing<N> {
         unsafe {
             ETH.ethernet_dma()
                 .dmactx_dtpr()
-                .write(|w| w.set_tdt(&self.td[x] as *const _ as u32));
+                .write(|w| w.0 = &self.td[x] as *const _ as u32);
         }
         self.tdidx = x;
         Ok(())
@@ -279,8 +279,7 @@ impl<const N: usize> RDesRing<N> {
         unsafe {
             let dma = ETH.ethernet_dma();
 
-            dma.dmacrx_dlar()
-                .write(|w| w.set_rdesla(self.rd.as_ptr() as u32));
+            dma.dmacrx_dlar().write(|w| w.0 = self.rd.as_ptr() as u32);
             dma.dmacrx_rlr().write(|w| w.set_rdrl((N as u16) - 1));
 
             // We manage to allocate all buffers, set the index to the last one, that means
@@ -290,7 +289,7 @@ impl<const N: usize> RDesRing<N> {
             let tail_ptr = &self.rd[last_index] as *const _ as u32;
             fence(Ordering::Release);
 
-            dma.dmacrx_dtpr().write(|w| w.set_rdt(tail_ptr));
+            dma.dmacrx_dtpr().write(|w| w.0 = tail_ptr);
         }
     }
 
@@ -340,7 +339,7 @@ impl<const N: usize> RDesRing<N> {
                 unsafe {
                     ETH.ethernet_dma()
                         .dmacrx_dtpr()
-                        .write(|w| w.set_rdt(&self.rd[self.tail_idx] as *const _ as u32));
+                        .write(|w| w.0 = &self.rd[self.tail_idx] as *const _ as u32);
                 }
 
                 self.tail_idx = (self.tail_idx + 1) % N;
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index 4c68294bc..ce5f25ebd 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -116,9 +116,13 @@ impl<'d, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, P, TX, RX> {
             mtl.mtltx_qomr().modify(|w| w.set_tsf(true));
 
             // TODO: Address aligned beats plus fixed burst ?
-            dma.dmactx_cr().modify(|w| w.set_txpbl(1)); // 32 ?
+            dma.dmasbmr().modify(|w| {
+                w.set_aal(true);
+                w.set_fb(true);
+            });
+            dma.dmactx_cr().modify(|w| w.set_txpbl(32)); // 32 ?
             dma.dmacrx_cr().modify(|w| {
-                w.set_rxpbl(1); // 32 ?
+                w.set_rxpbl(32); // 32 ?
                 w.set_rbsz(MTU as u16);
             });
         }
@@ -162,7 +166,8 @@ impl<'d, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, P, TX, RX> {
     pub fn init(self: Pin<&mut Self>) {
         // NOTE(unsafe) We won't move this
         let this = unsafe { self.get_unchecked_mut() };
-        let mutex = unsafe { Pin::new_unchecked(&mut this.state) };
+        let mut mutex = unsafe { Pin::new_unchecked(&mut this.state) };
+        mutex.as_mut().register_interrupt();
 
         mutex.with(|s, _| {
             s.desc_ring.init();
@@ -360,8 +365,9 @@ impl<'d, const TX: usize, const RX: usize> PeripheralState for Inner<'d, TX, RX>
             let dma = ETH.ethernet_dma();
 
             dma.dmacsr().modify(|w| {
-                w.set_ti(false);
-                w.set_ri(false);
+                w.set_ti(true);
+                w.set_ri(true);
+                w.set_nis(true);
             });
             // Delay two peripheral's clock
             dma.dmacsr().read();