Update to patched PAC with corrected Div4 (#41)

3 files changed, 16 insertions, 16 deletions

diff --git a/Cargo.lock b/Cargo.lock
index d9f4f08af..eb6c142ef 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -324,7 +324,7 @@ checksum = "11d3d7f243d5c5a8b9bb5d6dd2b1602c0cb0b9db1621bafc7ed66e35ff9fe092"
 [[package]]
 name = "mcxa-pac"
 version = "0.1.0"
-source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#3b36508ab1ac397861bae3431cc95c204f3ca6e9"
+source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#9a857ec9780527679978b42cc60288aeef03baa2"
 dependencies = [
  "cortex-m",
  "cortex-m-rt",
diff --git a/examples/Cargo.lock b/examples/Cargo.lock
index 473ce2b3f..56ae41d48 100644
--- a/examples/Cargo.lock
+++ b/examples/Cargo.lock
@@ -442,7 +442,7 @@ checksum = "11d3d7f243d5c5a8b9bb5d6dd2b1602c0cb0b9db1621bafc7ed66e35ff9fe092"
 [[package]]
 name = "mcxa-pac"
 version = "0.1.0"
-source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#3b36508ab1ac397861bae3431cc95c204f3ca6e9"
+source = "git+https://github.com/OpenDevicePartnership/mcxa-pac#9a857ec9780527679978b42cc60288aeef03baa2"
 dependencies = [
  "cortex-m",
  "cortex-m-rt",
diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs
index 8914f6833..eac3ef8dd 100644
--- a/src/clocks/periph_helpers.rs
+++ b/src/clocks/periph_helpers.rs
@@ -225,8 +225,8 @@ impl SPConfHelper for LpuartConfig {
                 // no ClkrootFunc7, just write manually for now
                 clksel.write(|w| w.bits(0b111));
                 clkdiv.modify(|_r, w| {
-                    w.reset().on();
-                    w.halt().on();
+                    w.reset().asserted();
+                    w.halt().asserted();
                     w
                 });
                 return Ok(0);
@@ -238,18 +238,18 @@ impl SPConfHelper for LpuartConfig {
 
         // Set up clkdiv
         clkdiv.modify(|_r, w| {
-            w.halt().on();
-            w.reset().on();
+            w.halt().asserted();
+            w.reset().asserted();
             unsafe { w.div().bits(self.div.into_bits()) };
             w
         });
         clkdiv.modify(|_r, w| {
-            w.halt().off();
-            w.reset().off();
+            w.halt().deasserted();
+            w.reset().deasserted();
             w
         });
 
-        while clkdiv.read().unstab().is_on() {}
+        while clkdiv.read().unstab().is_unstable() {}
 
         Ok(freq / self.div.into_divisor())
     }
@@ -362,8 +362,8 @@ impl SPConfHelper for AdcConfig {
                     w.mux().bits(0b111)
                 });
                 mrcc0.mrcc_adc_clkdiv().modify(|_r, w| {
-                    w.reset().on();
-                    w.halt().on();
+                    w.reset().asserted();
+                    w.halt().asserted();
                     w
                 });
                 return Ok(0);
@@ -375,18 +375,18 @@ impl SPConfHelper for AdcConfig {
 
         // Set up clkdiv
         mrcc0.mrcc_adc_clkdiv().modify(|_r, w| {
-            w.halt().on();
-            w.reset().on();
+            w.halt().asserted();
+            w.reset().asserted();
             unsafe { w.div().bits(self.div.into_bits()) };
             w
         });
         mrcc0.mrcc_adc_clkdiv().modify(|_r, w| {
-            w.halt().off();
-            w.reset().off();
+            w.halt().deasserted();
+            w.reset().deasserted();
             w
         });
 
-        while mrcc0.mrcc_adc_clkdiv().read().unstab().is_on() {}
+        while mrcc0.mrcc_adc_clkdiv().read().unstab().is_unstable() {}
 
         Ok(freq / self.div.into_divisor())
     }