add docs for PinNumber

2 files changed, 8 insertions, 0 deletions

diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 1813a887b..17c5a9962 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -804,6 +804,11 @@ pub(crate) trait SealedPin {
 /// is needed to hold the total pin number `(ports * number)`.
 #[cfg(not(stm32n6))]
 pub type PinNumber = u8;
+
+/// GPIO pin number type.
+///
+/// Some chips have a total number of ports that exceeds 8, a larger integer
+/// is needed to hold the total pin number `(ports * number)`.
 #[cfg(stm32n6)]
 pub type PinNumber = u16;
 
diff --git a/embassy-stm32/src/rcc/n6.rs b/embassy-stm32/src/rcc/n6.rs
index c9c874e75..866851bbd 100644
--- a/embassy-stm32/src/rcc/n6.rs
+++ b/embassy-stm32/src/rcc/n6.rs
@@ -167,6 +167,7 @@ impl Config {
     }
 }
 
+#[allow(dead_code)]
 struct ClocksOutput {
     cpuclk: Hertz,
     sysclk: Hertz,
@@ -580,6 +581,7 @@ struct PllInput {
 }
 
 #[derive(Clone, Copy, Default)]
+#[allow(dead_code)]
 struct PllOutput {
     divm: Option<Hertz>,
     divn: Option<Hertz>,
@@ -707,6 +709,7 @@ fn init_pll(pll_config: Option<Pll>, pll_index: usize, input: &PllInput) -> PllO
     }
 }
 
+#[allow(dead_code)]
 struct OscOutput {
     hsi: Option<Hertz>,
     hse: Option<Hertz>,