Merge pull request #1565 from JuliDi/main

Implement DMA for DAC on STM32

9 files changed, 757 insertions, 285 deletions

diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 40103d322..fa66da1f6 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -699,6 +699,8 @@ fn main() {
         // SDMMCv1 uses the same channel for both directions, so just implement for RX
         (("sdmmc", "RX"), quote!(crate::sdmmc::SdmmcDma)),
         (("quadspi", "QUADSPI"), quote!(crate::qspi::QuadDma)),
+        (("dac", "CH1"), quote!(crate::dac::DmaCh1)),
+        (("dac", "CH2"), quote!(crate::dac::DmaCh2)),
     ]
     .into();
 
diff --git a/embassy-stm32/src/dac.rs b/embassy-stm32/src/dac.rs
deleted file mode 100644
index 631118877..000000000
--- a/embassy-stm32/src/dac.rs
+++ /dev/null
@@ -1,260 +0,0 @@
-#![macro_use]
-
-use embassy_hal_common::{into_ref, PeripheralRef};
-
-use crate::pac::dac;
-use crate::rcc::RccPeripheral;
-use crate::{peripherals, Peripheral};
-
-#[derive(Debug, Copy, Clone, Eq, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Error {
-    UnconfiguredChannel,
-    InvalidValue,
-}
-
-#[derive(Debug, Copy, Clone, Eq, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Channel {
-    Ch1,
-    Ch2,
-}
-
-impl Channel {
-    fn index(&self) -> usize {
-        match self {
-            Channel::Ch1 => 0,
-            Channel::Ch2 => 1,
-        }
-    }
-}
-
-#[derive(Debug, Copy, Clone, Eq, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Ch1Trigger {
-    Tim6,
-    Tim3,
-    Tim7,
-    Tim15,
-    Tim2,
-    Exti9,
-    Software,
-}
-
-impl Ch1Trigger {
-    fn tsel(&self) -> dac::vals::Tsel1 {
-        match self {
-            Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO,
-            Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO,
-            Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO,
-            Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO,
-            Ch1Trigger::Tim2 => dac::vals::Tsel1::TIM2_TRGO,
-            Ch1Trigger::Exti9 => dac::vals::Tsel1::EXTI9,
-            Ch1Trigger::Software => dac::vals::Tsel1::SOFTWARE,
-        }
-    }
-}
-
-#[derive(Debug, Copy, Clone, Eq, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Ch2Trigger {
-    Tim6,
-    Tim8,
-    Tim7,
-    Tim5,
-    Tim2,
-    Tim4,
-    Exti9,
-    Software,
-}
-
-impl Ch2Trigger {
-    fn tsel(&self) -> dac::vals::Tsel2 {
-        match self {
-            Ch2Trigger::Tim6 => dac::vals::Tsel2::TIM6_TRGO,
-            Ch2Trigger::Tim8 => dac::vals::Tsel2::TIM8_TRGO,
-            Ch2Trigger::Tim7 => dac::vals::Tsel2::TIM7_TRGO,
-            Ch2Trigger::Tim5 => dac::vals::Tsel2::TIM5_TRGO,
-            Ch2Trigger::Tim2 => dac::vals::Tsel2::TIM2_TRGO,
-            Ch2Trigger::Tim4 => dac::vals::Tsel2::TIM4_TRGO,
-            Ch2Trigger::Exti9 => dac::vals::Tsel2::EXTI9,
-            Ch2Trigger::Software => dac::vals::Tsel2::SOFTWARE,
-        }
-    }
-}
-
-#[derive(Debug, Copy, Clone, Eq, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Alignment {
-    Left,
-    Right,
-}
-
-#[derive(Debug, Copy, Clone, Eq, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Value {
-    Bit8(u8),
-    Bit12(u16, Alignment),
-}
-
-pub struct Dac<'d, T: Instance> {
-    channels: u8,
-    _peri: PeripheralRef<'d, T>,
-}
-
-impl<'d, T: Instance> Dac<'d, T> {
-    pub fn new_1ch(peri: impl Peripheral<P = T> + 'd, _ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd) -> Self {
-        into_ref!(peri);
-        Self::new_inner(peri, 1)
-    }
-
-    pub fn new_2ch(
-        peri: impl Peripheral<P = T> + 'd,
-        _ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
-        _ch2: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
-    ) -> Self {
-        into_ref!(peri);
-        Self::new_inner(peri, 2)
-    }
-
-    fn new_inner(peri: PeripheralRef<'d, T>, channels: u8) -> Self {
-        T::enable();
-        T::reset();
-
-        T::regs().cr().modify(|reg| {
-            for ch in 0..channels {
-                reg.set_en(ch as usize, true);
-            }
-        });
-
-        Self { channels, _peri: peri }
-    }
-
-    /// Check the channel is configured
-    fn check_channel_exists(&self, ch: Channel) -> Result<(), Error> {
-        if ch == Channel::Ch2 && self.channels < 2 {
-            Err(Error::UnconfiguredChannel)
-        } else {
-            Ok(())
-        }
-    }
-
-    fn set_channel_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
-        self.check_channel_exists(ch)?;
-        T::regs().cr().modify(|reg| {
-            reg.set_en(ch.index(), on);
-        });
-        Ok(())
-    }
-
-    pub fn enable_channel(&mut self, ch: Channel) -> Result<(), Error> {
-        self.set_channel_enable(ch, true)
-    }
-
-    pub fn disable_channel(&mut self, ch: Channel) -> Result<(), Error> {
-        self.set_channel_enable(ch, false)
-    }
-
-    pub fn select_trigger_ch1(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
-        self.check_channel_exists(Channel::Ch1)?;
-        unwrap!(self.disable_channel(Channel::Ch1));
-        T::regs().cr().modify(|reg| {
-            reg.set_tsel1(trigger.tsel());
-        });
-        Ok(())
-    }
-
-    pub fn select_trigger_ch2(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
-        self.check_channel_exists(Channel::Ch2)?;
-        unwrap!(self.disable_channel(Channel::Ch2));
-        T::regs().cr().modify(|reg| {
-            reg.set_tsel2(trigger.tsel());
-        });
-        Ok(())
-    }
-
-    pub fn trigger(&mut self, ch: Channel) -> Result<(), Error> {
-        self.check_channel_exists(ch)?;
-        T::regs().swtrigr().write(|reg| {
-            reg.set_swtrig(ch.index(), true);
-        });
-        Ok(())
-    }
-
-    pub fn trigger_all(&mut self) {
-        T::regs().swtrigr().write(|reg| {
-            reg.set_swtrig(Channel::Ch1.index(), true);
-            reg.set_swtrig(Channel::Ch2.index(), true);
-        });
-    }
-
-    pub fn set(&mut self, ch: Channel, value: Value) -> Result<(), Error> {
-        self.check_channel_exists(ch)?;
-        match value {
-            Value::Bit8(v) => T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v)),
-            Value::Bit12(v, Alignment::Left) => T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v)),
-            Value::Bit12(v, Alignment::Right) => T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v)),
-        }
-        Ok(())
-    }
-}
-
-pub(crate) mod sealed {
-    pub trait Instance {
-        fn regs() -> &'static crate::pac::dac::Dac;
-    }
-}
-
-pub trait Instance: sealed::Instance + RccPeripheral + 'static {}
-
-pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
-
-foreach_peripheral!(
-    (dac, $inst:ident) => {
-        // H7 uses single bit for both DAC1 and DAC2, this is a hack until a proper fix is implemented
-        #[cfg(rcc_h7)]
-        impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
-            fn frequency() -> crate::time::Hertz {
-                critical_section::with(|_| unsafe {
-                    crate::rcc::get_freqs().apb1
-                })
-            }
-
-            fn reset() {
-                critical_section::with(|_| {
-                    crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true));
-                    crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false));
-                })
-            }
-
-            fn enable() {
-                critical_section::with(|_| {
-                    crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true));
-                })
-            }
-
-            fn disable() {
-                critical_section::with(|_| {
-                    crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(false));
-                })
-            }
-        }
-
-        #[cfg(rcc_h7)]
-        impl crate::rcc::RccPeripheral for peripherals::$inst {}
-
-        impl crate::dac::sealed::Instance for peripherals::$inst {
-            fn regs() -> &'static crate::pac::dac::Dac {
-                &crate::pac::$inst
-            }
-        }
-
-        impl crate::dac::Instance for peripherals::$inst {}
-    };
-);
-
-macro_rules! impl_dac_pin {
-    ($inst:ident, $pin:ident, $ch:expr) => {
-        impl crate::dac::DacPin<peripherals::$inst, $ch> for crate::peripherals::$pin {}
-    };
-}
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
new file mode 100644
index 000000000..1dc13949d
--- /dev/null
+++ b/embassy-stm32/src/dac/mod.rs
@@ -0,0 +1,570 @@
+#![macro_use]
+
+//! Provide access to the STM32 digital-to-analog converter (DAC).
+use core::marker::PhantomData;
+
+use embassy_hal_common::{into_ref, PeripheralRef};
+
+use crate::pac::dac;
+use crate::rcc::RccPeripheral;
+use crate::{peripherals, Peripheral};
+
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Curstom Errors
+pub enum Error {
+    UnconfiguredChannel,
+    InvalidValue,
+}
+
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// DAC Channels
+pub enum Channel {
+    Ch1,
+    Ch2,
+}
+
+impl Channel {
+    const fn index(&self) -> usize {
+        match self {
+            Channel::Ch1 => 0,
+            Channel::Ch2 => 1,
+        }
+    }
+}
+
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Trigger sources for CH1
+pub enum Ch1Trigger {
+    Tim6,
+    Tim3,
+    Tim7,
+    Tim15,
+    Tim2,
+    Exti9,
+    Software,
+}
+
+impl Ch1Trigger {
+    fn tsel(&self) -> dac::vals::Tsel1 {
+        match self {
+            Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO,
+            Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO,
+            Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO,
+            Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO,
+            Ch1Trigger::Tim2 => dac::vals::Tsel1::TIM2_TRGO,
+            Ch1Trigger::Exti9 => dac::vals::Tsel1::EXTI9,
+            Ch1Trigger::Software => dac::vals::Tsel1::SOFTWARE,
+        }
+    }
+}
+
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Trigger sources for CH2
+pub enum Ch2Trigger {
+    Tim6,
+    Tim8,
+    Tim7,
+    Tim5,
+    Tim2,
+    Tim4,
+    Exti9,
+    Software,
+}
+
+impl Ch2Trigger {
+    fn tsel(&self) -> dac::vals::Tsel2 {
+        match self {
+            Ch2Trigger::Tim6 => dac::vals::Tsel2::TIM6_TRGO,
+            Ch2Trigger::Tim8 => dac::vals::Tsel2::TIM8_TRGO,
+            Ch2Trigger::Tim7 => dac::vals::Tsel2::TIM7_TRGO,
+            Ch2Trigger::Tim5 => dac::vals::Tsel2::TIM5_TRGO,
+            Ch2Trigger::Tim2 => dac::vals::Tsel2::TIM2_TRGO,
+            Ch2Trigger::Tim4 => dac::vals::Tsel2::TIM4_TRGO,
+            Ch2Trigger::Exti9 => dac::vals::Tsel2::EXTI9,
+            Ch2Trigger::Software => dac::vals::Tsel2::SOFTWARE,
+        }
+    }
+}
+
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Single 8 or 12 bit value that can be output by the DAC
+pub enum Value {
+    // 8 bit value
+    Bit8(u8),
+    // 12 bit value stored in a u16, left-aligned
+    Bit12Left(u16),
+    // 12 bit value stored in a u16, right-aligned
+    Bit12Right(u16),
+}
+
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Array variant of [`Value`]
+pub enum ValueArray<'a> {
+    // 8 bit values
+    Bit8(&'a [u8]),
+    // 12 bit value stored in a u16, left-aligned
+    Bit12Left(&'a [u16]),
+    // 12 bit values stored in a u16, right-aligned
+    Bit12Right(&'a [u16]),
+}
+/// Provide common functions for DAC channels
+pub trait DacChannel<T: Instance, Tx> {
+    const CHANNEL: Channel;
+
+    /// Enable trigger of the given channel
+    fn set_trigger_enable(&mut self, on: bool) -> Result<(), Error> {
+        T::regs().cr().modify(|reg| {
+            reg.set_ten(Self::CHANNEL.index(), on);
+        });
+        Ok(())
+    }
+
+    /// Set mode register of the given channel
+    #[cfg(dac_v2)]
+    fn set_channel_mode(&mut self, val: u8) -> Result<(), Error> {
+        T::regs().mcr().modify(|reg| {
+            reg.set_mode(Self::CHANNEL.index(), val);
+        });
+        Ok(())
+    }
+
+    /// Set enable register of the given channel
+    fn set_channel_enable(&mut self, on: bool) -> Result<(), Error> {
+        T::regs().cr().modify(|reg| {
+            reg.set_en(Self::CHANNEL.index(), on);
+        });
+        Ok(())
+    }
+
+    /// Enable the DAC channel `ch`
+    fn enable_channel(&mut self) -> Result<(), Error> {
+        self.set_channel_enable(true)
+    }
+
+    /// Disable the DAC channel `ch`
+    fn disable_channel(&mut self) -> Result<(), Error> {
+        self.set_channel_enable(false)
+    }
+
+    /// Perform a software trigger on `ch`
+    fn trigger(&mut self) {
+        T::regs().swtrigr().write(|reg| {
+            reg.set_swtrig(Self::CHANNEL.index(), true);
+        });
+    }
+
+    /// Set a value to be output by the DAC on trigger.
+    ///
+    /// The `value` is written to the corresponding "data holding register".
+    fn set(&mut self, value: Value) -> Result<(), Error> {
+        match value {
+            Value::Bit8(v) => T::regs().dhr8r(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
+            Value::Bit12Left(v) => T::regs().dhr12l(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
+            Value::Bit12Right(v) => T::regs().dhr12r(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
+        }
+        Ok(())
+    }
+}
+
+/// Hold two DAC channels
+///
+/// Note: This consumes the DAC `Instance` only once, allowing to get both channels simultaneously.
+///
+/// # Example for obtaining both DAC channels
+///
+/// ```ignore
+/// // DMA channels and pins may need to be changed for your controller
+/// let (dac_ch1, dac_ch2) =
+///     embassy_stm32::dac::Dac::new(p.DAC1, p.DMA1_CH3, p.DMA1_CH4, p.PA4, p.PA5).split();
+/// ```
+pub struct Dac<'d, T: Instance, TxCh1, TxCh2> {
+    ch1: DacCh1<'d, T, TxCh1>,
+    ch2: DacCh2<'d, T, TxCh2>,
+}
+
+/// DAC CH1
+///
+/// Note: This consumes the DAC `Instance`. Use [`Dac::new`] to get both channels simultaneously.
+pub struct DacCh1<'d, T: Instance, Tx> {
+    /// To consume T
+    _peri: PeripheralRef<'d, T>,
+    #[allow(unused)] // For chips whose DMA is not (yet) supported
+    dma: PeripheralRef<'d, Tx>,
+}
+
+/// DAC CH2
+///
+/// Note: This consumes the DAC `Instance`. Use [`Dac::new`] to get both channels simultaneously.
+pub struct DacCh2<'d, T: Instance, Tx> {
+    /// Instead of PeripheralRef to consume T
+    phantom: PhantomData<&'d mut T>,
+    #[allow(unused)] // For chips whose DMA is not (yet) supported
+    dma: PeripheralRef<'d, Tx>,
+}
+
+impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
+    /// Obtain DAC CH1
+    pub fn new(
+        peri: impl Peripheral<P = T> + 'd,
+        dma: impl Peripheral<P = Tx> + 'd,
+        _pin: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
+    ) -> Self {
+        into_ref!(peri, dma);
+        T::enable();
+        T::reset();
+
+        let mut dac = Self { _peri: peri, dma };
+
+        // Configure each activated channel. All results can be `unwrap`ed since they
+        // will only error if the channel is not configured (i.e. ch1, ch2 are false)
+        #[cfg(dac_v2)]
+        dac.set_channel_mode(0).unwrap();
+        dac.enable_channel().unwrap();
+        dac.set_trigger_enable(true).unwrap();
+
+        dac
+    }
+
+    /// Select a new trigger for this channel
+    ///
+    /// **Important**: This disables the channel!
+    pub fn select_trigger(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
+        unwrap!(self.disable_channel());
+        T::regs().cr().modify(|reg| {
+            reg.set_tsel1(trigger.tsel());
+        });
+        Ok(())
+    }
+
+    /// Write `data` to the DAC CH1 via DMA.
+    ///
+    /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
+    /// This will configure a circular DMA transfer that periodically outputs the `data`.
+    /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
+    ///
+    /// **Important:** Channel 1 has to be configured for the DAC instance!
+    #[cfg(all(bdma, not(dma)))] // It currently only works with BDMA-only chips (DMA should theoretically work though)
+    pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+    where
+        Tx: DmaCh1<T>,
+    {
+        let channel = Channel::Ch1.index();
+        debug!("Writing to channel {}", channel);
+
+        // Enable DAC and DMA
+        T::regs().cr().modify(|w| {
+            w.set_en(channel, true);
+            w.set_dmaen(channel, true);
+        });
+
+        let tx_request = self.dma.request();
+        let dma_channel = &self.dma;
+
+        let tx_options = crate::dma::TransferOptions {
+            circular,
+            half_transfer_ir: false,
+            complete_transfer_ir: !circular,
+            ..Default::default()
+        };
+
+        // Initiate the correct type of DMA transfer depending on what data is passed
+        let tx_f = match data {
+            ValueArray::Bit8(buf) => unsafe {
+                crate::dma::Transfer::new_write(
+                    dma_channel,
+                    tx_request,
+                    buf,
+                    T::regs().dhr8r(channel).as_ptr() as *mut u8,
+                    tx_options,
+                )
+            },
+            ValueArray::Bit12Left(buf) => unsafe {
+                crate::dma::Transfer::new_write(
+                    dma_channel,
+                    tx_request,
+                    buf,
+                    T::regs().dhr12l(channel).as_ptr() as *mut u16,
+                    tx_options,
+                )
+            },
+            ValueArray::Bit12Right(buf) => unsafe {
+                crate::dma::Transfer::new_write(
+                    dma_channel,
+                    tx_request,
+                    buf,
+                    T::regs().dhr12r(channel).as_ptr() as *mut u16,
+                    tx_options,
+                )
+            },
+        };
+
+        tx_f.await;
+
+        // finish dma
+        // TODO: Do we need to check any status registers here?
+        T::regs().cr().modify(|w| {
+            // Disable the DAC peripheral
+            w.set_en(channel, false);
+            // Disable the DMA. TODO: Is this necessary?
+            w.set_dmaen(channel, false);
+        });
+
+        Ok(())
+    }
+}
+
+impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
+    /// Obtain DAC CH2
+    pub fn new(
+        _peri: impl Peripheral<P = T> + 'd,
+        dma: impl Peripheral<P = Tx> + 'd,
+        _pin: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
+    ) -> Self {
+        into_ref!(_peri, dma);
+        T::enable();
+        T::reset();
+
+        let mut dac = Self {
+            phantom: PhantomData,
+            dma,
+        };
+
+        // Configure each activated channel. All results can be `unwrap`ed since they
+        // will only error if the channel is not configured (i.e. ch1, ch2 are false)
+        #[cfg(dac_v2)]
+        dac.set_channel_mode(0).unwrap();
+        dac.enable_channel().unwrap();
+        dac.set_trigger_enable(true).unwrap();
+
+        dac
+    }
+
+    /// Select a new trigger for this channel
+    pub fn select_trigger(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
+        unwrap!(self.disable_channel());
+        T::regs().cr().modify(|reg| {
+            reg.set_tsel2(trigger.tsel());
+        });
+        Ok(())
+    }
+
+    /// Write `data` to the DAC CH2 via DMA.
+    ///
+    /// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
+    /// This will configure a circular DMA transfer that periodically outputs the `data`.
+    /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
+    ///
+    /// **Important:** Channel 2 has to be configured for the DAC instance!
+    #[cfg(all(bdma, not(dma)))] // It currently only works with BDMA-only chips (DMA should theoretically work though)
+    pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
+    where
+        Tx: DmaCh2<T>,
+    {
+        let channel = Channel::Ch2.index();
+        debug!("Writing to channel {}", channel);
+
+        // Enable DAC and DMA
+        T::regs().cr().modify(|w| {
+            w.set_en(channel, true);
+            w.set_dmaen(channel, true);
+        });
+
+        let tx_request = self.dma.request();
+        let dma_channel = &self.dma;
+
+        let tx_options = crate::dma::TransferOptions {
+            circular,
+            half_transfer_ir: false,
+            complete_transfer_ir: !circular,
+            ..Default::default()
+        };
+
+        // Initiate the correct type of DMA transfer depending on what data is passed
+        let tx_f = match data {
+            ValueArray::Bit8(buf) => unsafe {
+                crate::dma::Transfer::new_write(
+                    dma_channel,
+                    tx_request,
+                    buf,
+                    T::regs().dhr8r(channel).as_ptr() as *mut u8,
+                    tx_options,
+                )
+            },
+            ValueArray::Bit12Left(buf) => unsafe {
+                crate::dma::Transfer::new_write(
+                    dma_channel,
+                    tx_request,
+                    buf,
+                    T::regs().dhr12l(channel).as_ptr() as *mut u16,
+                    tx_options,
+                )
+            },
+            ValueArray::Bit12Right(buf) => unsafe {
+                crate::dma::Transfer::new_write(
+                    dma_channel,
+                    tx_request,
+                    buf,
+                    T::regs().dhr12r(channel).as_ptr() as *mut u16,
+                    tx_options,
+                )
+            },
+        };
+
+        tx_f.await;
+
+        // finish dma
+        // TODO: Do we need to check any status registers here?
+        T::regs().cr().modify(|w| {
+            // Disable the DAC peripheral
+            w.set_en(channel, false);
+            // Disable the DMA. TODO: Is this necessary?
+            w.set_dmaen(channel, false);
+        });
+
+        Ok(())
+    }
+}
+
+impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
+    /// Create a new DAC instance with both channels.
+    ///
+    /// This is used to obtain two independent channels via `split()` for use e.g. with DMA.
+    pub fn new(
+        peri: impl Peripheral<P = T> + 'd,
+        dma_ch1: impl Peripheral<P = TxCh1> + 'd,
+        dma_ch2: impl Peripheral<P = TxCh2> + 'd,
+        _pin_ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
+        _pin_ch2: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
+    ) -> Self {
+        into_ref!(peri, dma_ch1, dma_ch2);
+        T::enable();
+        T::reset();
+
+        let mut dac_ch1 = DacCh1 {
+            _peri: peri,
+            dma: dma_ch1,
+        };
+
+        let mut dac_ch2 = DacCh2 {
+            phantom: PhantomData,
+            dma: dma_ch2,
+        };
+
+        // Configure each activated channel. All results can be `unwrap`ed since they
+        // will only error if the channel is not configured (i.e. ch1, ch2 are false)
+        #[cfg(dac_v2)]
+        dac_ch1.set_channel_mode(0).unwrap();
+        dac_ch1.enable_channel().unwrap();
+        dac_ch1.set_trigger_enable(true).unwrap();
+
+        #[cfg(dac_v2)]
+        dac_ch2.set_channel_mode(0).unwrap();
+        dac_ch2.enable_channel().unwrap();
+        dac_ch2.set_trigger_enable(true).unwrap();
+
+        Self {
+            ch1: dac_ch1,
+            ch2: dac_ch2,
+        }
+    }
+
+    /// Split the DAC into CH1 and CH2 for independent use.
+    pub fn split(self) -> (DacCh1<'d, T, TxCh1>, DacCh2<'d, T, TxCh2>) {
+        (self.ch1, self.ch2)
+    }
+
+    /// Get mutable reference to CH1
+    pub fn ch1_mut(&mut self) -> &mut DacCh1<'d, T, TxCh1> {
+        &mut self.ch1
+    }
+
+    /// Get mutable reference to CH2
+    pub fn ch2_mut(&mut self) -> &mut DacCh2<'d, T, TxCh2> {
+        &mut self.ch2
+    }
+
+    /// Get reference to CH1
+    pub fn ch1(&mut self) -> &DacCh1<'d, T, TxCh1> {
+        &self.ch1
+    }
+
+    /// Get reference to CH2
+    pub fn ch2(&mut self) -> &DacCh2<'d, T, TxCh2> {
+        &self.ch2
+    }
+}
+
+impl<'d, T: Instance, Tx> DacChannel<T, Tx> for DacCh1<'d, T, Tx> {
+    const CHANNEL: Channel = Channel::Ch1;
+}
+
+impl<'d, T: Instance, Tx> DacChannel<T, Tx> for DacCh2<'d, T, Tx> {
+    const CHANNEL: Channel = Channel::Ch2;
+}
+
+pub(crate) mod sealed {
+    pub trait Instance {
+        fn regs() -> &'static crate::pac::dac::Dac;
+    }
+}
+
+pub trait Instance: sealed::Instance + RccPeripheral + 'static {}
+dma_trait!(DmaCh1, Instance);
+dma_trait!(DmaCh2, Instance);
+
+/// Marks a pin that can be used with the DAC
+pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
+
+foreach_peripheral!(
+    (dac, $inst:ident) => {
+        // H7 uses single bit for both DAC1 and DAC2, this is a hack until a proper fix is implemented
+        #[cfg(rcc_h7)]
+        impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
+            fn frequency() -> crate::time::Hertz {
+                critical_section::with(|_| unsafe { crate::rcc::get_freqs().apb1 })
+            }
+
+            fn reset() {
+                critical_section::with(|_| {
+                    crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true));
+                    crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false));
+                })
+            }
+
+            fn enable() {
+                critical_section::with(|_| {
+                    crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true));
+                })
+            }
+
+            fn disable() {
+                critical_section::with(|_| {
+                    crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(false))
+                })
+            }
+        }
+
+        #[cfg(rcc_h7)]
+        impl crate::rcc::RccPeripheral for peripherals::$inst {}
+
+        impl crate::dac::sealed::Instance for peripherals::$inst {
+            fn regs() -> &'static crate::pac::dac::Dac {
+                &crate::pac::$inst
+            }
+        }
+
+        impl crate::dac::Instance for peripherals::$inst {}
+    };
+);
+
+macro_rules! impl_dac_pin {
+    ($inst:ident, $pin:ident, $ch:expr) => {
+        impl crate::dac::DacPin<peripherals::$inst, $ch> for crate::peripherals::$pin {}
+    };
+}
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index a307c803c..5a87888b7 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -21,11 +21,22 @@ use crate::pac::bdma::{regs, vals};
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[non_exhaustive]
-pub struct TransferOptions {}
+pub struct TransferOptions {
+    /// Enable circular DMA
+    pub circular: bool,
+    /// Enable half transfer interrupt
+    pub half_transfer_ir: bool,
+    /// Enable transfer complete interrupt
+    pub complete_transfer_ir: bool,
+}
 
 impl Default for TransferOptions {
     fn default() -> Self {
-        Self {}
+        Self {
+            circular: false,
+            half_transfer_ir: false,
+            complete_transfer_ir: true,
+        }
     }
 }
 
@@ -253,7 +264,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
         mem_len: usize,
         incr_mem: bool,
         data_size: WordSize,
-        _options: TransferOptions,
+        options: TransferOptions,
     ) -> Self {
         let ch = channel.regs().ch(channel.num());
 
@@ -283,7 +294,15 @@ impl<'a, C: Channel> Transfer<'a, C> {
             }
             w.set_dir(dir.into());
             w.set_teie(true);
-            w.set_tcie(true);
+            w.set_tcie(options.complete_transfer_ir);
+            w.set_htie(options.half_transfer_ir);
+            if options.circular {
+                w.set_circ(vals::Circ::ENABLED);
+                debug!("Setting circular mode");
+            } else {
+                w.set_circ(vals::Circ::DISABLED);
+            }
+            w.set_pl(vals::Pl::VERYHIGH);
             w.set_en(true);
         });
 
@@ -310,8 +329,9 @@ impl<'a, C: Channel> Transfer<'a, C> {
     pub fn is_running(&mut self) -> bool {
         let ch = self.channel.regs().ch(self.channel.num());
         let en = ch.cr().read().en();
+        let circular = ch.cr().read().circ() == vals::Circ::ENABLED;
         let tcif = STATE.complete_count[self.channel.index()].load(Ordering::Acquire) != 0;
-        en && !tcif
+        en && (circular || !tcif)
     }
 
     /// Gets the total remaining transfers for the channel
@@ -477,6 +497,8 @@ impl<'a, C: Channel, W: Word> RingBuffer<'a, C, W> {
         let ch = self.channel.regs().ch(self.channel.num());
 
         // Disable the channel. Keep the IEs enabled so the irqs still fire.
+        // If the channel is enabled and transfer is not completed, we need to perform
+        // two separate write access to the CR register to disable the channel.
         ch.cr().write(|w| {
             w.set_teie(true);
             w.set_htie(true);
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index 80a336a48..698292bff 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -227,7 +227,11 @@ const DMA_TRANSFER_OPTIONS: crate::dma::TransferOptions = crate::dma::TransferOp
     fifo_threshold: Some(crate::dma::FifoThreshold::Full),
 };
 #[cfg(all(sdmmc_v1, not(dma)))]
-const DMA_TRANSFER_OPTIONS: crate::dma::TransferOptions = crate::dma::TransferOptions {};
+const DMA_TRANSFER_OPTIONS: crate::dma::TransferOptions = crate::dma::TransferOptions {
+    circular: false,
+    half_transfer_ir: false,
+    complete_transfer_ir: true,
+};
 
 /// SDMMC configuration
 ///
diff --git a/examples/stm32f4/src/bin/dac.rs b/examples/stm32f4/src/bin/dac.rs
index d97ae7082..3a6216712 100644
--- a/examples/stm32f4/src/bin/dac.rs
+++ b/examples/stm32f4/src/bin/dac.rs
@@ -4,7 +4,8 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::dac::{Channel, Dac, Value};
+use embassy_stm32::dac::{DacCh1, DacChannel, Value};
+use embassy_stm32::dma::NoDma;
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
@@ -12,12 +13,12 @@ async fn main(_spawner: Spawner) -> ! {
     let p = embassy_stm32::init(Default::default());
     info!("Hello World, dude!");
 
-    let mut dac = Dac::new_1ch(p.DAC, p.PA4);
+    let mut dac = DacCh1::new(p.DAC, NoDma, p.PA4);
 
     loop {
         for v in 0..=255 {
-            unwrap!(dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v))));
-            unwrap!(dac.trigger(Channel::Ch1));
+            unwrap!(dac.set(Value::Bit8(to_sine_wave(v))));
+            dac.trigger();
         }
     }
 }
diff --git a/examples/stm32h7/src/bin/dac.rs b/examples/stm32h7/src/bin/dac.rs
index f12716370..586b4154b 100644
--- a/examples/stm32h7/src/bin/dac.rs
+++ b/examples/stm32h7/src/bin/dac.rs
@@ -4,7 +4,8 @@
 
 use cortex_m_rt::entry;
 use defmt::*;
-use embassy_stm32::dac::{Channel, Dac, Value};
+use embassy_stm32::dac::{DacCh1, DacChannel, Value};
+use embassy_stm32::dma::NoDma;
 use embassy_stm32::time::mhz;
 use embassy_stm32::Config;
 use {defmt_rtt as _, panic_probe as _};
@@ -19,12 +20,12 @@ fn main() -> ! {
     config.rcc.pll1.q_ck = Some(mhz(100));
     let p = embassy_stm32::init(config);
 
-    let mut dac = Dac::new_1ch(p.DAC1, p.PA4);
+    let mut dac = DacCh1::new(p.DAC1, NoDma, p.PA4);
 
     loop {
         for v in 0..=255 {
-            unwrap!(dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v))));
-            unwrap!(dac.trigger(Channel::Ch1));
+            unwrap!(dac.set(Value::Bit8(to_sine_wave(v))));
+            dac.trigger();
         }
     }
 }
diff --git a/examples/stm32l4/src/bin/dac.rs b/examples/stm32l4/src/bin/dac.rs
index a36ed5d90..ade43eb35 100644
--- a/examples/stm32l4/src/bin/dac.rs
+++ b/examples/stm32l4/src/bin/dac.rs
@@ -3,26 +3,21 @@
 #![feature(type_alias_impl_trait)]
 
 use defmt::*;
-use embassy_stm32::dac::{Channel, Dac, Value};
-use embassy_stm32::pac;
+use embassy_stm32::dac::{DacCh1, DacChannel, Value};
+use embassy_stm32::dma::NoDma;
 use {defmt_rtt as _, panic_probe as _};
 
 #[cortex_m_rt::entry]
 fn main() -> ! {
-    info!("Hello World!");
-
-    pac::RCC.apb1enr1().modify(|w| {
-        w.set_dac1en(true);
-    });
-
     let p = embassy_stm32::init(Default::default());
+    info!("Hello World!");
 
-    let mut dac = Dac::new_1ch(p.DAC1, p.PA4);
+    let mut dac = DacCh1::new(p.DAC1, NoDma, p.PA4);
 
     loop {
         for v in 0..=255 {
-            unwrap!(dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v))));
-            unwrap!(dac.trigger(Channel::Ch1));
+            unwrap!(dac.set(Value::Bit8(to_sine_wave(v))));
+            dac.trigger();
         }
     }
 }
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs
new file mode 100644
index 000000000..c27cc03e1
--- /dev/null
+++ b/examples/stm32l4/src/bin/dac_dma.rs
@@ -0,0 +1,137 @@
+#![no_std]
+#![no_main]
+#![feature(type_alias_impl_trait)]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::dac::{DacChannel, ValueArray};
+use embassy_stm32::pac::timer::vals::{Mms, Opm};
+use embassy_stm32::peripherals::{TIM6, TIM7};
+use embassy_stm32::rcc::low_level::RccPeripheral;
+use embassy_stm32::time::Hertz;
+use embassy_stm32::timer::low_level::Basic16bitInstance;
+use micromath::F32Ext;
+use {defmt_rtt as _, panic_probe as _};
+
+pub type Dac1Type =
+    embassy_stm32::dac::DacCh1<'static, embassy_stm32::peripherals::DAC1, embassy_stm32::peripherals::DMA1_CH3>;
+
+pub type Dac2Type =
+    embassy_stm32::dac::DacCh2<'static, embassy_stm32::peripherals::DAC1, embassy_stm32::peripherals::DMA1_CH4>;
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) {
+    let config = embassy_stm32::Config::default();
+
+    // Initialize the board and obtain a Peripherals instance
+    let p: embassy_stm32::Peripherals = embassy_stm32::init(config);
+
+    // Obtain two independent channels (p.DAC1 can only be consumed once, though!)
+    let (dac_ch1, dac_ch2) = embassy_stm32::dac::Dac::new(p.DAC1, p.DMA1_CH3, p.DMA1_CH4, p.PA4, p.PA5).split();
+
+    spawner.spawn(dac_task1(dac_ch1)).ok();
+    spawner.spawn(dac_task2(dac_ch2)).ok();
+}
+
+#[embassy_executor::task]
+async fn dac_task1(mut dac: Dac1Type) {
+    let data: &[u8; 256] = &calculate_array::<256>();
+
+    info!("TIM6 frequency is {}", TIM6::frequency());
+    const FREQUENCY: Hertz = Hertz::hz(200);
+
+    // Compute the reload value such that we obtain the FREQUENCY for the sine
+    let reload: u32 = (TIM6::frequency().0 / FREQUENCY.0) / data.len() as u32;
+
+    // Depends on your clock and on the specific chip used, you may need higher or lower values here
+    if reload < 10 {
+        error!("Reload value {} below threshold!", reload);
+    }
+
+    dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap();
+    dac.enable_channel().unwrap();
+
+    TIM6::enable();
+    TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
+    TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
+    TIM6::regs().cr1().modify(|w| {
+        w.set_opm(Opm::DISABLED);
+        w.set_cen(true);
+    });
+
+    debug!(
+        "TIM6 Frequency {}, Target Frequency {}, Reload {}, Reload as u16 {}, Samples {}",
+        TIM6::frequency(),
+        FREQUENCY,
+        reload,
+        reload as u16,
+        data.len()
+    );
+
+    // Loop technically not necessary if DMA circular mode is enabled
+    loop {
+        info!("Loop DAC1");
+        if let Err(e) = dac.write(ValueArray::Bit8(data), true).await {
+            error!("Could not write to dac: {}", e);
+        }
+    }
+}
+
+#[embassy_executor::task]
+async fn dac_task2(mut dac: Dac2Type) {
+    let data: &[u8; 256] = &calculate_array::<256>();
+
+    info!("TIM7 frequency is {}", TIM7::frequency());
+
+    const FREQUENCY: Hertz = Hertz::hz(600);
+    let reload: u32 = (TIM7::frequency().0 / FREQUENCY.0) / data.len() as u32;
+
+    if reload < 10 {
+        error!("Reload value {} below threshold!", reload);
+    }
+
+    TIM7::enable();
+    TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
+    TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
+    TIM7::regs().cr1().modify(|w| {
+        w.set_opm(Opm::DISABLED);
+        w.set_cen(true);
+    });
+
+    dac.select_trigger(embassy_stm32::dac::Ch2Trigger::Tim7).unwrap();
+
+    debug!(
+        "TIM7 Frequency {}, Target Frequency {}, Reload {}, Reload as u16 {}, Samples {}",
+        TIM7::frequency(),
+        FREQUENCY,
+        reload,
+        reload as u16,
+        data.len()
+    );
+
+    if let Err(e) = dac.write(ValueArray::Bit8(data), true).await {
+        error!("Could not write to dac: {}", e);
+    }
+}
+
+fn to_sine_wave(v: u8) -> u8 {
+    if v >= 128 {
+        // top half
+        let r = 3.14 * ((v - 128) as f32 / 128.0);
+        (r.sin() * 128.0 + 127.0) as u8
+    } else {
+        // bottom half
+        let r = 3.14 + 3.14 * (v as f32 / 128.0);
+        (r.sin() * 128.0 + 127.0) as u8
+    }
+}
+
+fn calculate_array<const N: usize>() -> [u8; N] {
+    let mut res = [0; N];
+    let mut i = 0;
+    while i < N {
+        res[i] = to_sine_wave(i as u8);
+        i += 1;
+    }
+    res
+}