diff options
| author | xoviat <[email protected]> | 2023-07-30 10:57:17 -0500 |
|---|---|---|
| committer | xoviat <[email protected]> | 2023-07-30 10:57:17 -0500 |
| commit | 6f30e92c7aecc80d9fdf23e462a5128c07446f2f (patch) | |
| tree | c7905c478754b2884f05c92ed0bace5e617ce4e7 | |
| parent | 087e649bc297676c483f1f2a94a5abf101dea9a2 (diff) | |
stm32/dma: don't write to full ringbuf
| -rw-r--r-- | embassy-stm32/src/dma/ringbuffer.rs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/embassy-stm32/src/dma/ringbuffer.rs b/embassy-stm32/src/dma/ringbuffer.rs index e9d330219..800f19069 100644 --- a/embassy-stm32/src/dma/ringbuffer.rs +++ b/embassy-stm32/src/dma/ringbuffer.rs | |||
| @@ -243,6 +243,8 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { | |||
| 243 | 243 | ||
| 244 | Ok((len, self.cap() - (start - self.end))) | 244 | Ok((len, self.cap() - (start - self.end))) |
| 245 | } | 245 | } |
| 246 | } else if start == self.end && dma.get_complete_count() == 0 { | ||
| 247 | Ok((0, 0)) | ||
| 246 | } else if start <= self.end && self.end + buf.len() < self.cap() { | 248 | } else if start <= self.end && self.end + buf.len() < self.cap() { |
| 247 | // The occupied portion in the ring buffer DOES NOT wrap | 249 | // The occupied portion in the ring buffer DOES NOT wrap |
| 248 | // and copying elements into the buffer WILL NOT cause it to | 250 | // and copying elements into the buffer WILL NOT cause it to |