Update u5.rs

Update comments on p and q divider values to correctly describe what the clock outputs are used for.

1 files changed, 8 insertions, 10 deletions

diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 0321d51f7..ceed46176 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -45,17 +45,15 @@ pub struct PllConfig {
     /// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
     /// MHz. The upper limit may be lower depending on the `Config { voltage_range }`.
     pub n: Plln,
-    /// The divider for the P output.
-    ///
-    /// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
-    /// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
-    /// `Config { voltage_range }`.
+    /// The divider for the P output. 
+    /// 
+    /// The P output is one of several options
+    /// that can be used to feed the SAI/MDF/ADF Clock mux's.
     pub p: Plldiv,
-    /// The divider for the Q output.
-    ///
-    /// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
-    /// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
-    /// `Config { voltage_range }`.
+    /// The divider for the Q output. 
+    /// 
+    /// The Q ouput is one of severals options that can be used to feed the 48MHz clocks
+    /// and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux's.
     pub q: Plldiv,
     /// The divider for the R output.
     ///