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authorDario Nieuwenhuis <[email protected]>2024-02-26 02:58:03 +0100
committerDario Nieuwenhuis <[email protected]>2024-02-26 03:02:58 +0100
commit72c6f9a101141183fb2de46c2fe40aa979330d9c (patch)
treecb7d41fed85ed0aeea1fe6193116210be92e65b2
parenta308b9ac2f752fec61e23cdc4c9826692b1a5651 (diff)
stm32/adc: reexport enums from PAC to avoid boilerplate hell.
Diffstat
-rw-r--r--embassy-stm32/Cargo.toml4
-rw-r--r--embassy-stm32/src/adc/f1.rs18
-rw-r--r--embassy-stm32/src/adc/f3.rs16
-rw-r--r--embassy-stm32/src/adc/f3_v1_1.rs51
-rw-r--r--embassy-stm32/src/adc/mod.rs35
-rw-r--r--embassy-stm32/src/adc/resolution.rs72
-rw-r--r--embassy-stm32/src/adc/sample_time.rs148
-rw-r--r--embassy-stm32/src/adc/v1.rs2
-rw-r--r--embassy-stm32/src/adc/v2.rs2
-rw-r--r--embassy-stm32/src/adc/v3.rs6
-rw-r--r--embassy-stm32/src/adc/v4.rs2
-rw-r--r--examples/stm32f0/src/bin/adc.rs2
-rw-r--r--examples/stm32f334/src/bin/adc.rs2
-rw-r--r--examples/stm32f334/src/bin/opamp.rs2
-rw-r--r--examples/stm32g4/src/bin/adc.rs2
-rw-r--r--examples/stm32h7/src/bin/adc.rs2
-rw-r--r--examples/stm32l0/src/bin/adc.rs2
-rw-r--r--examples/stm32l4/src/bin/adc.rs2
18 files changed, 82 insertions, 288 deletions
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index e0bee6a92..7d21383c3 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -70,7 +70,7 @@ rand_core = "0.6.3"
70sdio-host = "0.5.0" 70sdio-host = "0.5.0"
71critical-section = "1.1" 71critical-section = "1.1"
72#stm32-metapac = { version = "15" } 72#stm32-metapac = { version = "15" }
73stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-88f71cbcd2f048c40bad162c7e7864cc3897eba4" } 73stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7c8b53413499acc3273b706318777a60f932d77a" }
74vcell = "0.1.3" 74vcell = "0.1.3"
75bxcan = "0.7.0" 75bxcan = "0.7.0"
76nb = "1.0.0" 76nb = "1.0.0"
@@ -94,7 +94,7 @@ critical-section = { version = "1.1", features = ["std"] }
94proc-macro2 = "1.0.36" 94proc-macro2 = "1.0.36"
95quote = "1.0.15" 95quote = "1.0.15"
96#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]} 96#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
97stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-88f71cbcd2f048c40bad162c7e7864cc3897eba4", default-features = false, features = ["metadata"]} 97stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7c8b53413499acc3273b706318777a60f932d77a", default-features = false, features = ["metadata"]}
98 98
99 99
100[features] 100[features]
diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index c896d8e3a..b27b99827 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -74,7 +74,7 @@ impl<'d, T: Instance> Adc<'d, T> {
74 74
75 Self { 75 Self {
76 adc, 76 adc,
77 sample_time: Default::default(), 77 sample_time: SampleTime::from_bits(0),
78 } 78 }
79 } 79 }
80 80
@@ -84,14 +84,14 @@ impl<'d, T: Instance> Adc<'d, T> {
84 84
85 pub fn sample_time_for_us(&self, us: u32) -> SampleTime { 85 pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
86 match us * Self::freq().0 / 1_000_000 { 86 match us * Self::freq().0 / 1_000_000 {
87 0..=1 => SampleTime::Cycles1_5, 87 0..=1 => SampleTime::CYCLES1_5,
88 2..=7 => SampleTime::Cycles7_5, 88 2..=7 => SampleTime::CYCLES7_5,
89 8..=13 => SampleTime::Cycles13_5, 89 8..=13 => SampleTime::CYCLES13_5,
90 14..=28 => SampleTime::Cycles28_5, 90 14..=28 => SampleTime::CYCLES28_5,
91 29..=41 => SampleTime::Cycles41_5, 91 29..=41 => SampleTime::CYCLES41_5,
92 42..=55 => SampleTime::Cycles55_5, 92 42..=55 => SampleTime::CYCLES55_5,
93 56..=71 => SampleTime::Cycles71_5, 93 56..=71 => SampleTime::CYCLES71_5,
94 _ => SampleTime::Cycles239_5, 94 _ => SampleTime::CYCLES239_5,
95 } 95 }
96 } 96 }
97 97
diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs
index 6606a2b9c..efade1f64 100644
--- a/embassy-stm32/src/adc/f3.rs
+++ b/embassy-stm32/src/adc/f3.rs
@@ -97,7 +97,7 @@ impl<'d, T: Instance> Adc<'d, T> {
97 97
98 Self { 98 Self {
99 adc, 99 adc,
100 sample_time: Default::default(), 100 sample_time: SampleTime::from_bits(0),
101 } 101 }
102 } 102 }
103 103
@@ -107,13 +107,13 @@ impl<'d, T: Instance> Adc<'d, T> {
107 107
108 pub fn sample_time_for_us(&self, us: u32) -> SampleTime { 108 pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
109 match us * Self::freq().0 / 1_000_000 { 109 match us * Self::freq().0 / 1_000_000 {
110 0..=1 => SampleTime::Cycles1_5, 110 0..=1 => SampleTime::CYCLES1_5,
111 2..=4 => SampleTime::Cycles4_5, 111 2..=4 => SampleTime::CYCLES4_5,
112 5..=7 => SampleTime::Cycles7_5, 112 5..=7 => SampleTime::CYCLES7_5,
113 8..=19 => SampleTime::Cycles19_5, 113 8..=19 => SampleTime::CYCLES19_5,
114 20..=61 => SampleTime::Cycles61_5, 114 20..=61 => SampleTime::CYCLES61_5,
115 62..=181 => SampleTime::Cycles181_5, 115 62..=181 => SampleTime::CYCLES181_5,
116 _ => SampleTime::Cycles601_5, 116 _ => SampleTime::CYCLES601_5,
117 } 117 }
118 } 118 }
119 119
diff --git a/embassy-stm32/src/adc/f3_v1_1.rs b/embassy-stm32/src/adc/f3_v1_1.rs
index 6915a8f1c..f842893fa 100644
--- a/embassy-stm32/src/adc/f3_v1_1.rs
+++ b/embassy-stm32/src/adc/f3_v1_1.rs
@@ -107,12 +107,12 @@ impl Calibration {
107 107
108 /// Returns a calibrated voltage value as in microvolts (uV) 108 /// Returns a calibrated voltage value as in microvolts (uV)
109 pub fn cal_uv(&self, raw: u16, resolution: super::Resolution) -> u32 { 109 pub fn cal_uv(&self, raw: u16, resolution: super::Resolution) -> u32 {
110 (self.vdda_uv() / resolution.to_max_count()) * raw as u32 110 (self.vdda_uv() / super::resolution_to_max_count(resolution)) * raw as u32
111 } 111 }
112 112
113 /// Returns a calibrated voltage value as an f32 113 /// Returns a calibrated voltage value as an f32
114 pub fn cal_f32(&self, raw: u16, resolution: super::Resolution) -> f32 { 114 pub fn cal_f32(&self, raw: u16, resolution: super::Resolution) -> f32 {
115 raw as f32 * self.vdda_f32() / resolution.to_max_count() as f32 115 raw as f32 * self.vdda_f32() / super::resolution_to_max_count(resolution) as f32
116 } 116 }
117} 117}
118 118
@@ -175,12 +175,7 @@ impl<'d, T: Instance> Adc<'d, T> {
175 } 175 }
176 176
177 pub fn resolution(&self) -> Resolution { 177 pub fn resolution(&self) -> Resolution {
178 match T::regs().cr1().read().res() { 178 T::regs().cr1().read().res()
179 crate::pac::adc::vals::Res::TWELVEBIT => Resolution::TwelveBit,
180 crate::pac::adc::vals::Res::TENBIT => Resolution::TenBit,
181 crate::pac::adc::vals::Res::EIGHTBIT => Resolution::EightBit,
182 crate::pac::adc::vals::Res::SIXBIT => Resolution::SixBit,
183 }
184 } 179 }
185 180
186 pub fn enable_vref(&self) -> Vref<T> { 181 pub fn enable_vref(&self) -> Vref<T> {
@@ -359,23 +354,23 @@ impl<'d, T: Instance> Adc<'d, T> {
359 354
360 fn get_res_clks(res: Resolution) -> u32 { 355 fn get_res_clks(res: Resolution) -> u32 {
361 match res { 356 match res {
362 Resolution::TwelveBit => 12, 357 Resolution::BITS12 => 12,
363 Resolution::TenBit => 11, 358 Resolution::BITS10 => 11,
364 Resolution::EightBit => 9, 359 Resolution::BITS8 => 9,
365 Resolution::SixBit => 7, 360 Resolution::BITS6 => 7,
366 } 361 }
367 } 362 }
368 363
369 fn get_sample_time_clks(sample_time: SampleTime) -> u32 { 364 fn get_sample_time_clks(sample_time: SampleTime) -> u32 {
370 match sample_time { 365 match sample_time {
371 SampleTime::Cycles4 => 4, 366 SampleTime::CYCLES4 => 4,
372 SampleTime::Cycles9 => 9, 367 SampleTime::CYCLES9 => 9,
373 SampleTime::Cycles16 => 16, 368 SampleTime::CYCLES16 => 16,
374 SampleTime::Cycles24 => 24, 369 SampleTime::CYCLES24 => 24,
375 SampleTime::Cycles48 => 48, 370 SampleTime::CYCLES48 => 48,
376 SampleTime::Cycles96 => 96, 371 SampleTime::CYCLES96 => 96,
377 SampleTime::Cycles192 => 192, 372 SampleTime::CYCLES192 => 192,
378 SampleTime::Cycles384 => 384, 373 SampleTime::CYCLES384 => 384,
379 } 374 }
380 } 375 }
381 376
@@ -384,14 +379,14 @@ impl<'d, T: Instance> Adc<'d, T> {
384 let us_clks = us * Self::freq().0 / 1_000_000; 379 let us_clks = us * Self::freq().0 / 1_000_000;
385 let clks = us_clks.saturating_sub(res_clks); 380 let clks = us_clks.saturating_sub(res_clks);
386 match clks { 381 match clks {
387 0..=4 => SampleTime::Cycles4, 382 0..=4 => SampleTime::CYCLES4,
388 5..=9 => SampleTime::Cycles9, 383 5..=9 => SampleTime::CYCLES9,
389 10..=16 => SampleTime::Cycles16, 384 10..=16 => SampleTime::CYCLES16,
390 17..=24 => SampleTime::Cycles24, 385 17..=24 => SampleTime::CYCLES24,
391 25..=48 => SampleTime::Cycles48, 386 25..=48 => SampleTime::CYCLES48,
392 49..=96 => SampleTime::Cycles96, 387 49..=96 => SampleTime::CYCLES96,
393 97..=192 => SampleTime::Cycles192, 388 97..=192 => SampleTime::CYCLES192,
394 193.. => SampleTime::Cycles384, 389 193.. => SampleTime::CYCLES384,
395 } 390 }
396 } 391 }
397 392
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index b273c6394..0d0d40549 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -14,18 +14,13 @@
14#[cfg_attr(adc_v4, path = "v4.rs")] 14#[cfg_attr(adc_v4, path = "v4.rs")]
15mod _version; 15mod _version;
16 16
17#[cfg(not(any(adc_f1, adc_f3_v2)))]
18mod resolution;
19mod sample_time;
20
21#[allow(unused)] 17#[allow(unused)]
22#[cfg(not(adc_f3_v2))] 18#[cfg(not(adc_f3_v2))]
23pub use _version::*; 19pub use _version::*;
24#[cfg(not(any(adc_f1, adc_f3, adc_f3_v2)))]
25pub use resolution::Resolution;
26#[cfg(not(adc_f3_v2))]
27pub use sample_time::SampleTime;
28 20
21#[cfg(not(any(adc_f1, adc_f3_v2)))]
22pub use crate::pac::adc::vals::Res as Resolution;
23pub use crate::pac::adc::vals::SampleTime;
29use crate::peripherals; 24use crate::peripherals;
30 25
31/// Analog to Digital driver. 26/// Analog to Digital driver.
@@ -137,3 +132,27 @@ macro_rules! impl_adc_pin {
137 } 132 }
138 }; 133 };
139} 134}
135
136/// Get the maximum reading value for this resolution.
137///
138/// This is `2**n - 1`.
139#[cfg(not(any(adc_f1, adc_f3_v2)))]
140pub const fn resolution_to_max_count(res: Resolution) -> u32 {
141 match res {
142 #[cfg(adc_v4)]
143 Resolution::BITS16 => (1 << 16) - 1,
144 #[cfg(adc_v4)]
145 Resolution::BITS14 => (1 << 14) - 1,
146 #[cfg(adc_v4)]
147 Resolution::BITS14V => (1 << 14) - 1,
148 #[cfg(adc_v4)]
149 Resolution::BITS12V => (1 << 12) - 1,
150 Resolution::BITS12 => (1 << 12) - 1,
151 Resolution::BITS10 => (1 << 10) - 1,
152 Resolution::BITS8 => (1 << 8) - 1,
153 #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
154 Resolution::BITS6 => (1 << 6) - 1,
155 #[allow(unreachable_patterns)]
156 _ => core::unreachable!(),
157 }
158}
diff --git a/embassy-stm32/src/adc/resolution.rs b/embassy-stm32/src/adc/resolution.rs
deleted file mode 100644
index 37788cd77..000000000
--- a/embassy-stm32/src/adc/resolution.rs
+++ /dev/null
@@ -1,72 +0,0 @@
1/// ADC resolution
2#[allow(missing_docs)]
3#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
4#[derive(Clone, Copy, Debug, Eq, PartialEq)]
5#[cfg_attr(feature = "defmt", derive(defmt::Format))]
6pub enum Resolution {
7 TwelveBit,
8 TenBit,
9 EightBit,
10 SixBit,
11}
12
13/// ADC resolution
14#[allow(missing_docs)]
15#[cfg(adc_v4)]
16#[derive(Clone, Copy, Debug, Eq, PartialEq)]
17#[cfg_attr(feature = "defmt", derive(defmt::Format))]
18pub enum Resolution {
19 SixteenBit,
20 FourteenBit,
21 TwelveBit,
22 TenBit,
23 EightBit,
24}
25
26impl Default for Resolution {
27 fn default() -> Self {
28 #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
29 {
30 Self::TwelveBit
31 }
32 #[cfg(adc_v4)]
33 {
34 Self::SixteenBit
35 }
36 }
37}
38
39impl From<Resolution> for crate::pac::adc::vals::Res {
40 fn from(res: Resolution) -> crate::pac::adc::vals::Res {
41 match res {
42 #[cfg(adc_v4)]
43 Resolution::SixteenBit => crate::pac::adc::vals::Res::SIXTEENBIT,
44 #[cfg(adc_v4)]
45 Resolution::FourteenBit => crate::pac::adc::vals::Res::FOURTEENBITV,
46 Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
47 Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
48 Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
49 #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
50 Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
51 }
52 }
53}
54
55impl Resolution {
56 /// Get the maximum reading value for this resolution.
57 ///
58 /// This is `2**n - 1`.
59 pub const fn to_max_count(&self) -> u32 {
60 match self {
61 #[cfg(adc_v4)]
62 Resolution::SixteenBit => (1 << 16) - 1,
63 #[cfg(adc_v4)]
64 Resolution::FourteenBit => (1 << 14) - 1,
65 Resolution::TwelveBit => (1 << 12) - 1,
66 Resolution::TenBit => (1 << 10) - 1,
67 Resolution::EightBit => (1 << 8) - 1,
68 #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
69 Resolution::SixBit => (1 << 6) - 1,
70 }
71 }
72}
diff --git a/embassy-stm32/src/adc/sample_time.rs b/embassy-stm32/src/adc/sample_time.rs
deleted file mode 100644
index 19bc22938..000000000
--- a/embassy-stm32/src/adc/sample_time.rs
+++ /dev/null
@@ -1,148 +0,0 @@
1#[cfg(not(adc_f3_v2))]
2macro_rules! impl_sample_time {
3 ($default_doc:expr, $default:ident, ($(($doc:expr, $variant:ident, $pac_variant:ident)),*)) => {
4 #[doc = concat!("ADC sample time\n\nThe default setting is ", $default_doc, " ADC clock cycles.")]
5 #[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd)]
6 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
7 pub enum SampleTime {
8 $(
9 #[doc = concat!($doc, " ADC clock cycles.")]
10 $variant,
11 )*
12 }
13
14 impl From<SampleTime> for crate::pac::adc::vals::SampleTime {
15 fn from(sample_time: SampleTime) -> crate::pac::adc::vals::SampleTime {
16 match sample_time {
17 $(SampleTime::$variant => crate::pac::adc::vals::SampleTime::$pac_variant),*
18 }
19 }
20 }
21
22 impl From<crate::pac::adc::vals::SampleTime> for SampleTime {
23 fn from(sample_time: crate::pac::adc::vals::SampleTime) -> SampleTime {
24 match sample_time {
25 $(crate::pac::adc::vals::SampleTime::$pac_variant => SampleTime::$variant),*
26 }
27 }
28 }
29
30 impl Default for SampleTime {
31 fn default() -> Self {
32 Self::$default
33 }
34 }
35 };
36}
37
38#[cfg(any(adc_f1, adc_v1))]
39impl_sample_time!(
40 "1.5",
41 Cycles1_5,
42 (
43 ("1.5", Cycles1_5, CYCLES1_5),
44 ("7.5", Cycles7_5, CYCLES7_5),
45 ("13.5", Cycles13_5, CYCLES13_5),
46 ("28.5", Cycles28_5, CYCLES28_5),
47 ("41.5", Cycles41_5, CYCLES41_5),
48 ("55.5", Cycles55_5, CYCLES55_5),
49 ("71.5", Cycles71_5, CYCLES71_5),
50 ("239.5", Cycles239_5, CYCLES239_5)
51 )
52);
53
54#[cfg(adc_v2)]
55impl_sample_time!(
56 "3",
57 Cycles3,
58 (
59 ("3", Cycles3, CYCLES3),
60 ("15", Cycles15, CYCLES15),
61 ("28", Cycles28, CYCLES28),
62 ("56", Cycles56, CYCLES56),
63 ("84", Cycles84, CYCLES84),
64 ("112", Cycles112, CYCLES112),
65 ("144", Cycles144, CYCLES144),
66 ("480", Cycles480, CYCLES480)
67 )
68);
69
70#[cfg(any(adc_v3, adc_h5))]
71impl_sample_time!(
72 "2.5",
73 Cycles2_5,
74 (
75 ("2.5", Cycles2_5, CYCLES2_5),
76 ("6.5", Cycles6_5, CYCLES6_5),
77 ("12.5", Cycles12_5, CYCLES12_5),
78 ("24.5", Cycles24_5, CYCLES24_5),
79 ("47.5", Cycles47_5, CYCLES47_5),
80 ("92.5", Cycles92_5, CYCLES92_5),
81 ("247.5", Cycles247_5, CYCLES247_5),
82 ("640.5", Cycles640_5, CYCLES640_5)
83 )
84);
85
86#[cfg(any(adc_l0, adc_g0))]
87impl_sample_time!(
88 "1.5",
89 Cycles1_5,
90 (
91 ("1.5", Cycles1_5, CYCLES1_5),
92 ("3.5", Cycles3_5, CYCLES3_5),
93 ("7.5", Cycles7_5, CYCLES7_5),
94 ("12.5", Cycles12_5, CYCLES12_5),
95 ("19.5", Cycles19_5, CYCLES19_5),
96 ("39.5", Cycles39_5, CYCLES39_5),
97 ("79.5", Cycles79_5, CYCLES79_5),
98 ("160.5", Cycles160_5, CYCLES160_5)
99 )
100);
101
102#[cfg(adc_v4)]
103impl_sample_time!(
104 "1.5",
105 Cycles1_5,
106 (
107 ("1.5", Cycles1_5, CYCLES1_5),
108 ("2.5", Cycles2_5, CYCLES2_5),
109 ("8.5", Cycles8_5, CYCLES8_5),
110 ("16.5", Cycles16_5, CYCLES16_5),
111 ("32.5", Cycles32_5, CYCLES32_5),
112 ("64.5", Cycles64_5, CYCLES64_5),
113 ("387.5", Cycles387_5, CYCLES387_5),
114 ("810.5", Cycles810_5, CYCLES810_5)
115 )
116);
117
118#[cfg(adc_f3)]
119impl_sample_time!(
120 "1.5",
121 Cycles1_5,
122 (
123 ("1.5", Cycles1_5, CYCLES1_5),
124 ("2.5", Cycles2_5, CYCLES2_5),
125 ("4.5", Cycles4_5, CYCLES4_5),
126 ("7.5", Cycles7_5, CYCLES7_5),
127 ("19.5", Cycles19_5, CYCLES19_5),
128 ("61.5", Cycles61_5, CYCLES61_5),
129 ("181.5", Cycles181_5, CYCLES181_5),
130 ("601.5", Cycles601_5, CYCLES601_5)
131 )
132);
133
134#[cfg(any(adc_f3_v1_1))]
135impl_sample_time!(
136 "4",
137 Cycles4,
138 (
139 ("4", Cycles4, CYCLES4),
140 ("9", Cycles9, CYCLES9),
141 ("16", Cycles16, CYCLES16),
142 ("24", Cycles24, CYCLES24),
143 ("48", Cycles48, CYCLES48),
144 ("96", Cycles96, CYCLES96),
145 ("192", Cycles192, CYCLES192),
146 ("384", Cycles384, CYCLES384)
147 )
148);
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 37115dfab..a8dc6ce98 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -109,7 +109,7 @@ impl<'d, T: Instance> Adc<'d, T> {
109 109
110 Self { 110 Self {
111 adc, 111 adc,
112 sample_time: Default::default(), 112 sample_time: SampleTime::from_bits(0),
113 } 113 }
114 } 114 }
115 115
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index b37ac5a5d..f6f7dbfcc 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -111,7 +111,7 @@ where
111 111
112 Self { 112 Self {
113 adc, 113 adc,
114 sample_time: Default::default(), 114 sample_time: SampleTime::from_bits(0),
115 } 115 }
116 } 116 }
117 117
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 0c44e4400..5f3512cad 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -102,7 +102,7 @@ impl<'d, T: Instance> Adc<'d, T> {
102 102
103 Self { 103 Self {
104 adc, 104 adc,
105 sample_time: Default::default(), 105 sample_time: SampleTime::from_bits(0),
106 } 106 }
107 } 107 }
108 108
@@ -259,8 +259,8 @@ impl<'d, T: Instance> Adc<'d, T> {
259 } else { 259 } else {
260 let sample_time = sample_time.into(); 260 let sample_time = sample_time.into();
261 T::regs() 261 T::regs()
262 .smpr(ch as usize / 10) 262 .smpr(_ch as usize / 10)
263 .modify(|reg| reg.set_smp(ch as usize % 10, sample_time)); 263 .modify(|reg| reg.set_smp(_ch as usize % 10, sample_time));
264 } 264 }
265 } 265 }
266 } 266 }
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index 048e73184..3fd047375 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -159,7 +159,7 @@ impl<'d, T: Instance> Adc<'d, T> {
159 } 159 }
160 let mut s = Self { 160 let mut s = Self {
161 adc, 161 adc,
162 sample_time: Default::default(), 162 sample_time: SampleTime::from_bits(0),
163 }; 163 };
164 s.power_up(delay); 164 s.power_up(delay);
165 s.configure_differential_inputs(); 165 s.configure_differential_inputs();
diff --git a/examples/stm32f0/src/bin/adc.rs b/examples/stm32f0/src/bin/adc.rs
index 8fef062b3..c2fb143cd 100644
--- a/examples/stm32f0/src/bin/adc.rs
+++ b/examples/stm32f0/src/bin/adc.rs
@@ -19,7 +19,7 @@ async fn main(_spawner: Spawner) {
19 info!("Hello World!"); 19 info!("Hello World!");
20 20
21 let mut adc = Adc::new(p.ADC, Irqs, &mut Delay); 21 let mut adc = Adc::new(p.ADC, Irqs, &mut Delay);
22 adc.set_sample_time(SampleTime::Cycles71_5); 22 adc.set_sample_time(SampleTime::CYCLES71_5);
23 let mut pin = p.PA1; 23 let mut pin = p.PA1;
24 24
25 let mut vrefint = adc.enable_vref(&mut Delay); 25 let mut vrefint = adc.enable_vref(&mut Delay);
diff --git a/examples/stm32f334/src/bin/adc.rs b/examples/stm32f334/src/bin/adc.rs
index a9fb7f1a6..bd126ce68 100644
--- a/examples/stm32f334/src/bin/adc.rs
+++ b/examples/stm32f334/src/bin/adc.rs
@@ -40,7 +40,7 @@ async fn main(_spawner: Spawner) -> ! {
40 40
41 let mut adc = Adc::new(p.ADC1, Irqs, &mut Delay); 41 let mut adc = Adc::new(p.ADC1, Irqs, &mut Delay);
42 42
43 adc.set_sample_time(SampleTime::Cycles601_5); 43 adc.set_sample_time(SampleTime::CYCLES601_5);
44 44
45 info!("enable vrefint..."); 45 info!("enable vrefint...");
46 46
diff --git a/examples/stm32f334/src/bin/opamp.rs b/examples/stm32f334/src/bin/opamp.rs
index 6f25191be..a5c710aa2 100644
--- a/examples/stm32f334/src/bin/opamp.rs
+++ b/examples/stm32f334/src/bin/opamp.rs
@@ -42,7 +42,7 @@ async fn main(_spawner: Spawner) -> ! {
42 let mut adc = Adc::new(p.ADC2, Irqs, &mut Delay); 42 let mut adc = Adc::new(p.ADC2, Irqs, &mut Delay);
43 let mut opamp = OpAmp::new(p.OPAMP2); 43 let mut opamp = OpAmp::new(p.OPAMP2);
44 44
45 adc.set_sample_time(SampleTime::Cycles601_5); 45 adc.set_sample_time(SampleTime::CYCLES601_5);
46 46
47 info!("enable vrefint..."); 47 info!("enable vrefint...");
48 48
diff --git a/examples/stm32g4/src/bin/adc.rs b/examples/stm32g4/src/bin/adc.rs
index 99e3ef63b..6c6de1ffe 100644
--- a/examples/stm32g4/src/bin/adc.rs
+++ b/examples/stm32g4/src/bin/adc.rs
@@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) {
30 info!("Hello World!"); 30 info!("Hello World!");
31 31
32 let mut adc = Adc::new(p.ADC2, &mut Delay); 32 let mut adc = Adc::new(p.ADC2, &mut Delay);
33 adc.set_sample_time(SampleTime::Cycles32_5); 33 adc.set_sample_time(SampleTime::CYCLES32_5);
34 34
35 loop { 35 loop {
36 let measured = adc.read(&mut p.PA7); 36 let measured = adc.read(&mut p.PA7);
diff --git a/examples/stm32h7/src/bin/adc.rs b/examples/stm32h7/src/bin/adc.rs
index fe6fe69a1..f0278239f 100644
--- a/examples/stm32h7/src/bin/adc.rs
+++ b/examples/stm32h7/src/bin/adc.rs
@@ -46,7 +46,7 @@ async fn main(_spawner: Spawner) {
46 46
47 let mut adc = Adc::new(p.ADC3, &mut Delay); 47 let mut adc = Adc::new(p.ADC3, &mut Delay);
48 48
49 adc.set_sample_time(SampleTime::Cycles32_5); 49 adc.set_sample_time(SampleTime::CYCLES32_5);
50 50
51 let mut vrefint_channel = adc.enable_vrefint(); 51 let mut vrefint_channel = adc.enable_vrefint();
52 52
diff --git a/examples/stm32l0/src/bin/adc.rs b/examples/stm32l0/src/bin/adc.rs
index adeaa208a..97d41ca4b 100644
--- a/examples/stm32l0/src/bin/adc.rs
+++ b/examples/stm32l0/src/bin/adc.rs
@@ -19,7 +19,7 @@ async fn main(_spawner: Spawner) {
19 info!("Hello World!"); 19 info!("Hello World!");
20 20
21 let mut adc = Adc::new(p.ADC, Irqs, &mut Delay); 21 let mut adc = Adc::new(p.ADC, Irqs, &mut Delay);
22 adc.set_sample_time(SampleTime::Cycles79_5); 22 adc.set_sample_time(SampleTime::CYCLES79_5);
23 let mut pin = p.PA1; 23 let mut pin = p.PA1;
24 24
25 let mut vrefint = adc.enable_vref(&mut Delay); 25 let mut vrefint = adc.enable_vref(&mut Delay);
diff --git a/examples/stm32l4/src/bin/adc.rs b/examples/stm32l4/src/bin/adc.rs
index d01e9f1b3..910944673 100644
--- a/examples/stm32l4/src/bin/adc.rs
+++ b/examples/stm32l4/src/bin/adc.rs
@@ -20,7 +20,7 @@ fn main() -> ! {
20 20
21 let mut adc = Adc::new(p.ADC1, &mut Delay); 21 let mut adc = Adc::new(p.ADC1, &mut Delay);
22 //adc.enable_vref(); 22 //adc.enable_vref();
23 adc.set_resolution(Resolution::EightBit); 23 adc.set_resolution(Resolution::BITS8);
24 let mut channel = p.PC0; 24 let mut channel = p.PC0;
25 25
26 loop { 26 loop {
generated by cgit (git 2.34.1) at 2026-04-05 23:42:02 +0000