Further clean-up and adjustments. Follow RM for FIPS.

267 files changed, 3684 insertions, 3676 deletions

diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py
index 6dbe951d1..89c40ad7d 100644
--- a/embassy-stm32/gen.py
+++ b/embassy-stm32/gen.py
@@ -131,7 +131,7 @@ for chip in chips.values():
                             f.write(f'impl_usart_pin!({name}, CkPin, {pin}, {func});')
 
             if peri['block'] == 'rng_v1/RNG':
-                f.write(f'impl_rng!();')
+                f.write(f'impl_rng!({name});')
 
         for mod, version in peripheral_versions.items():
             f.write(f'pub use regs::{mod}_{version} as {mod};')
diff --git a/embassy-stm32/src/pac/regs.rs b/embassy-stm32/src/pac/regs.rs
index d34c8a69a..370d0c512 100644
--- a/embassy-stm32/src/pac/regs.rs
+++ b/embassy-stm32/src/pac/regs.rs
@@ -1,436 +1,299 @@
 #![no_std]
 #![doc = "Peripheral access API (generated using svd2rust v0.17.0 (507115a 2021-04-19))"]
-pub mod dma_v2 {
+pub mod rng_v1 {
     use crate::generic::*;
-    #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
+    #[doc = "Random number generator"]
     #[derive(Copy, Clone)]
-    pub struct St(pub *mut u8);
-    unsafe impl Send for St {}
-    unsafe impl Sync for St {}
-    impl St {
-        #[doc = "stream x configuration register"]
+    pub struct Rng(pub *mut u8);
+    unsafe impl Send for Rng {}
+    unsafe impl Sync for Rng {}
+    impl Rng {
+        #[doc = "control register"]
         pub fn cr(self) -> Reg<regs::Cr, RW> {
             unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
-        #[doc = "stream x number of data register"]
-        pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
+        #[doc = "status register"]
+        pub fn sr(self) -> Reg<regs::Sr, RW> {
             unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-        #[doc = "stream x peripheral address register"]
-        pub fn par(self) -> Reg<u32, RW> {
+        #[doc = "data register"]
+        pub fn dr(self) -> Reg<u32, R> {
             unsafe { Reg::from_ptr(self.0.add(8usize)) }
         }
-        #[doc = "stream x memory 0 address register"]
-        pub fn m0ar(self) -> Reg<u32, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
-        #[doc = "stream x memory 1 address register"]
-        pub fn m1ar(self) -> Reg<u32, RW> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
-        }
-        #[doc = "stream x FIFO control register"]
-        pub fn fcr(self) -> Reg<regs::Fcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
-        }
-    }
-    #[doc = "DMA controller"]
-    #[derive(Copy, Clone)]
-    pub struct Dma(pub *mut u8);
-    unsafe impl Send for Dma {}
-    unsafe impl Sync for Dma {}
-    impl Dma {
-        #[doc = "low interrupt status register"]
-        pub fn isr(self, n: usize) -> Reg<regs::Isr, R> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
-        }
-        #[doc = "low interrupt flag clear register"]
-        pub fn ifcr(self, n: usize) -> Reg<regs::Ifcr, W> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
-        }
-        #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
-        pub fn st(self, n: usize) -> St {
-            assert!(n < 8usize);
-            unsafe { St(self.0.add(16usize + n * 24usize)) }
-        }
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "stream x FIFO control register"]
+        #[doc = "control register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Fcr(pub u32);
-        impl Fcr {
-            #[doc = "FIFO threshold selection"]
-            pub const fn fth(&self) -> super::vals::Fth {
-                let val = (self.0 >> 0usize) & 0x03;
-                super::vals::Fth(val as u8)
-            }
-            #[doc = "FIFO threshold selection"]
-            pub fn set_fth(&mut self, val: super::vals::Fth) {
-                self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
-            }
-            #[doc = "Direct mode disable"]
-            pub const fn dmdis(&self) -> super::vals::Dmdis {
+        pub struct Cr(pub u32);
+        impl Cr {
+            #[doc = "Random number generator enable"]
+            pub const fn rngen(&self) -> bool {
                 let val = (self.0 >> 2usize) & 0x01;
-                super::vals::Dmdis(val as u8)
-            }
-            #[doc = "Direct mode disable"]
-            pub fn set_dmdis(&mut self, val: super::vals::Dmdis) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
-            }
-            #[doc = "FIFO status"]
-            pub const fn fs(&self) -> super::vals::Fs {
-                let val = (self.0 >> 3usize) & 0x07;
-                super::vals::Fs(val as u8)
+                val != 0
             }
-            #[doc = "FIFO status"]
-            pub fn set_fs(&mut self, val: super::vals::Fs) {
-                self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
+            #[doc = "Random number generator enable"]
+            pub fn set_rngen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "FIFO error interrupt enable"]
-            pub const fn feie(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
+            #[doc = "Interrupt enable"]
+            pub const fn ie(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
                 val != 0
             }
-            #[doc = "FIFO error interrupt enable"]
-            pub fn set_feie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            #[doc = "Interrupt enable"]
+            pub fn set_ie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
             }
         }
-        impl Default for Fcr {
-            fn default() -> Fcr {
-                Fcr(0)
+        impl Default for Cr {
+            fn default() -> Cr {
+                Cr(0)
             }
         }
-        #[doc = "low interrupt status register"]
+        #[doc = "status register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Isr(pub u32);
-        impl Isr {
-            #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
-            pub fn feif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                let val = (self.0 >> offs) & 0x01;
+        pub struct Sr(pub u32);
+        impl Sr {
+            #[doc = "Data ready"]
+            pub const fn drdy(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
-            pub fn set_feif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Data ready"]
+            pub fn set_drdy(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
-            pub fn dmeif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Clock error current status"]
+            pub const fn cecs(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
-            pub fn set_dmeif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Clock error current status"]
+            pub fn set_cecs(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
-            pub fn teif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Seed error current status"]
+            pub const fn secs(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
-            pub fn set_teif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Seed error current status"]
+            pub fn set_secs(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
-            pub fn htif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Clock error interrupt status"]
+            pub const fn ceis(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
-            pub fn set_htif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Clock error interrupt status"]
+            pub fn set_ceis(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
-            pub fn tcif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Seed error interrupt status"]
+            pub const fn seis(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
-            pub fn set_tcif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Seed error interrupt status"]
+            pub fn set_seis(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
         }
-        impl Default for Isr {
-            fn default() -> Isr {
-                Isr(0)
+        impl Default for Sr {
+            fn default() -> Sr {
+                Sr(0)
             }
         }
-        #[doc = "low interrupt flag clear register"]
+    }
+}
+pub mod gpio_v1 {
+    use crate::generic::*;
+    #[doc = "General purpose I/O"]
+    #[derive(Copy, Clone)]
+    pub struct Gpio(pub *mut u8);
+    unsafe impl Send for Gpio {}
+    unsafe impl Sync for Gpio {}
+    impl Gpio {
+        #[doc = "Port configuration register low (GPIOn_CRL)"]
+        pub fn cr(self, n: usize) -> Reg<regs::Cr, RW> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
+        }
+        #[doc = "Port input data register (GPIOn_IDR)"]
+        pub fn idr(self) -> Reg<regs::Idr, R> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "Port output data register (GPIOn_ODR)"]
+        pub fn odr(self) -> Reg<regs::Odr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
+        pub fn bsrr(self) -> Reg<regs::Bsrr, W> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "Port bit reset register (GPIOn_BRR)"]
+        pub fn brr(self) -> Reg<regs::Brr, W> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+        #[doc = "Port configuration lock register"]
+        pub fn lckr(self) -> Reg<regs::Lckr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+        }
+    }
+    pub mod regs {
+        use crate::generic::*;
+        #[doc = "Port output data register (GPIOn_ODR)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ifcr(pub u32);
-        impl Ifcr {
-            #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"]
-            pub fn cfeif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+        pub struct Odr(pub u32);
+        impl Odr {
+            #[doc = "Port output data"]
+            pub fn odr(&self, n: usize) -> super::vals::Odr {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
-                val != 0
+                super::vals::Odr(val as u8)
             }
-            #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"]
-            pub fn set_cfeif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Port output data"]
+            pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
             }
-            #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"]
-            pub fn cdmeif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+        }
+        impl Default for Odr {
+            fn default() -> Odr {
+                Odr(0)
+            }
+        }
+        #[doc = "Port configuration lock register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Lckr(pub u32);
+        impl Lckr {
+            #[doc = "Port A Lock bit"]
+            pub fn lck(&self, n: usize) -> super::vals::Lck {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
-                val != 0
+                super::vals::Lck(val as u8)
             }
-            #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"]
-            pub fn set_cdmeif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Port A Lock bit"]
+            pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
             }
-            #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"]
-            pub fn cteif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+            #[doc = "Lock key"]
+            pub const fn lckk(&self) -> super::vals::Lckk {
+                let val = (self.0 >> 16usize) & 0x01;
+                super::vals::Lckk(val as u8)
+            }
+            #[doc = "Lock key"]
+            pub fn set_lckk(&mut self, val: super::vals::Lckk) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
+            }
+        }
+        impl Default for Lckr {
+            fn default() -> Lckr {
+                Lckr(0)
+            }
+        }
+        #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Bsrr(pub u32);
+        impl Bsrr {
+            #[doc = "Set bit"]
+            pub fn bs(&self, n: usize) -> bool {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"]
-            pub fn set_cteif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+            #[doc = "Set bit"]
+            pub fn set_bs(&mut self, n: usize, val: bool) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"]
-            pub fn chtif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+            #[doc = "Reset bit"]
+            pub fn br(&self, n: usize) -> bool {
+                assert!(n < 16usize);
+                let offs = 16usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"]
-            pub fn set_chtif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+            #[doc = "Reset bit"]
+            pub fn set_br(&mut self, n: usize, val: bool) {
+                assert!(n < 16usize);
+                let offs = 16usize + n * 1usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"]
-            pub fn ctcif(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+        }
+        impl Default for Bsrr {
+            fn default() -> Bsrr {
+                Bsrr(0)
+            }
+        }
+        #[doc = "Port bit reset register (GPIOn_BRR)"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Brr(pub u32);
+        impl Brr {
+            #[doc = "Reset bit"]
+            pub fn br(&self, n: usize) -> bool {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"]
-            pub fn set_ctcif(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+            #[doc = "Reset bit"]
+            pub fn set_br(&mut self, n: usize, val: bool) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for Ifcr {
-            fn default() -> Ifcr {
-                Ifcr(0)
+        impl Default for Brr {
+            fn default() -> Brr {
+                Brr(0)
             }
         }
-        #[doc = "stream x configuration register"]
+        #[doc = "Port configuration register (GPIOn_CRx)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
         pub struct Cr(pub u32);
         impl Cr {
-            #[doc = "Stream enable / flag stream ready when read low"]
-            pub const fn en(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Stream enable / flag stream ready when read low"]
-            pub fn set_en(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Direct mode error interrupt enable"]
-            pub const fn dmeie(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Direct mode error interrupt enable"]
-            pub fn set_dmeie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
-            }
-            #[doc = "Transfer error interrupt enable"]
-            pub const fn teie(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Transfer error interrupt enable"]
-            pub fn set_teie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
-            }
-            #[doc = "Half transfer interrupt enable"]
-            pub const fn htie(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Half transfer interrupt enable"]
-            pub fn set_htie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
-            }
-            #[doc = "Transfer complete interrupt enable"]
-            pub const fn tcie(&self) -> bool {
-                let val = (self.0 >> 4usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Transfer complete interrupt enable"]
-            pub fn set_tcie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
-            }
-            #[doc = "Peripheral flow controller"]
-            pub const fn pfctrl(&self) -> super::vals::Pfctrl {
-                let val = (self.0 >> 5usize) & 0x01;
-                super::vals::Pfctrl(val as u8)
-            }
-            #[doc = "Peripheral flow controller"]
-            pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
-            }
-            #[doc = "Data transfer direction"]
-            pub const fn dir(&self) -> super::vals::Dir {
-                let val = (self.0 >> 6usize) & 0x03;
-                super::vals::Dir(val as u8)
-            }
-            #[doc = "Data transfer direction"]
-            pub fn set_dir(&mut self, val: super::vals::Dir) {
-                self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize);
-            }
-            #[doc = "Circular mode"]
-            pub const fn circ(&self) -> super::vals::Circ {
-                let val = (self.0 >> 8usize) & 0x01;
-                super::vals::Circ(val as u8)
-            }
-            #[doc = "Circular mode"]
-            pub fn set_circ(&mut self, val: super::vals::Circ) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
-            }
-            #[doc = "Peripheral increment mode"]
-            pub const fn pinc(&self) -> super::vals::Inc {
-                let val = (self.0 >> 9usize) & 0x01;
-                super::vals::Inc(val as u8)
-            }
-            #[doc = "Peripheral increment mode"]
-            pub fn set_pinc(&mut self, val: super::vals::Inc) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
-            }
-            #[doc = "Memory increment mode"]
-            pub const fn minc(&self) -> super::vals::Inc {
-                let val = (self.0 >> 10usize) & 0x01;
-                super::vals::Inc(val as u8)
-            }
-            #[doc = "Memory increment mode"]
-            pub fn set_minc(&mut self, val: super::vals::Inc) {
-                self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
-            }
-            #[doc = "Peripheral data size"]
-            pub const fn psize(&self) -> super::vals::Size {
-                let val = (self.0 >> 11usize) & 0x03;
-                super::vals::Size(val as u8)
-            }
-            #[doc = "Peripheral data size"]
-            pub fn set_psize(&mut self, val: super::vals::Size) {
-                self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize);
-            }
-            #[doc = "Memory data size"]
-            pub const fn msize(&self) -> super::vals::Size {
-                let val = (self.0 >> 13usize) & 0x03;
-                super::vals::Size(val as u8)
-            }
-            #[doc = "Memory data size"]
-            pub fn set_msize(&mut self, val: super::vals::Size) {
-                self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize);
-            }
-            #[doc = "Peripheral increment offset size"]
-            pub const fn pincos(&self) -> super::vals::Pincos {
-                let val = (self.0 >> 15usize) & 0x01;
-                super::vals::Pincos(val as u8)
-            }
-            #[doc = "Peripheral increment offset size"]
-            pub fn set_pincos(&mut self, val: super::vals::Pincos) {
-                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
-            }
-            #[doc = "Priority level"]
-            pub const fn pl(&self) -> super::vals::Pl {
-                let val = (self.0 >> 16usize) & 0x03;
-                super::vals::Pl(val as u8)
-            }
-            #[doc = "Priority level"]
-            pub fn set_pl(&mut self, val: super::vals::Pl) {
-                self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize);
-            }
-            #[doc = "Double buffer mode"]
-            pub const fn dbm(&self) -> super::vals::Dbm {
-                let val = (self.0 >> 18usize) & 0x01;
-                super::vals::Dbm(val as u8)
-            }
-            #[doc = "Double buffer mode"]
-            pub fn set_dbm(&mut self, val: super::vals::Dbm) {
-                self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
-            }
-            #[doc = "Current target (only in double buffer mode)"]
-            pub const fn ct(&self) -> super::vals::Ct {
-                let val = (self.0 >> 19usize) & 0x01;
-                super::vals::Ct(val as u8)
-            }
-            #[doc = "Current target (only in double buffer mode)"]
-            pub fn set_ct(&mut self, val: super::vals::Ct) {
-                self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
-            }
-            #[doc = "Peripheral burst transfer configuration"]
-            pub const fn pburst(&self) -> super::vals::Burst {
-                let val = (self.0 >> 21usize) & 0x03;
-                super::vals::Burst(val as u8)
-            }
-            #[doc = "Peripheral burst transfer configuration"]
-            pub fn set_pburst(&mut self, val: super::vals::Burst) {
-                self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize);
-            }
-            #[doc = "Memory burst transfer configuration"]
-            pub const fn mburst(&self) -> super::vals::Burst {
-                let val = (self.0 >> 23usize) & 0x03;
-                super::vals::Burst(val as u8)
+            #[doc = "Port n mode bits"]
+            pub fn mode(&self, n: usize) -> super::vals::Mode {
+                assert!(n < 8usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::Mode(val as u8)
             }
-            #[doc = "Memory burst transfer configuration"]
-            pub fn set_mburst(&mut self, val: super::vals::Burst) {
-                self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize);
+            #[doc = "Port n mode bits"]
+            pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) {
+                assert!(n < 8usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
             }
-            #[doc = "Channel selection"]
-            pub const fn chsel(&self) -> u8 {
-                let val = (self.0 >> 25usize) & 0x0f;
-                val as u8
+            #[doc = "Port n configuration bits"]
+            pub fn cnf(&self, n: usize) -> super::vals::Cnf {
+                assert!(n < 8usize);
+                let offs = 2usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::Cnf(val as u8)
             }
-            #[doc = "Channel selection"]
-            pub fn set_chsel(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize);
+            #[doc = "Port n configuration bits"]
+            pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) {
+                assert!(n < 8usize);
+                let offs = 2usize + n * 4usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
             }
         }
         impl Default for Cr {
@@ -438,24 +301,28 @@ pub mod dma_v2 {
                 Cr(0)
             }
         }
-        #[doc = "stream x number of data register"]
+        #[doc = "Port input data register (GPIOn_IDR)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ndtr(pub u32);
-        impl Ndtr {
-            #[doc = "Number of data items to transfer"]
-            pub const fn ndt(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
+        pub struct Idr(pub u32);
+        impl Idr {
+            #[doc = "Port input data"]
+            pub fn idr(&self, n: usize) -> super::vals::Idr {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Idr(val as u8)
             }
-            #[doc = "Number of data items to transfer"]
-            pub fn set_ndt(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            #[doc = "Port input data"]
+            pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
             }
         }
-        impl Default for Ndtr {
-            fn default() -> Ndtr {
-                Ndtr(0)
+        impl Default for Idr {
+            fn default() -> Idr {
+                Idr(0)
             }
         }
     }
@@ -463,144 +330,83 @@ pub mod dma_v2 {
         use crate::generic::*;
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ct(pub u8);
-        impl Ct {
-            #[doc = "The current target memory is Memory 0"]
-            pub const MEMORY0: Self = Self(0);
-            #[doc = "The current target memory is Memory 1"]
-            pub const MEMORY1: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Pl(pub u8);
-        impl Pl {
-            #[doc = "Low"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Medium"]
-            pub const MEDIUM: Self = Self(0x01);
-            #[doc = "High"]
-            pub const HIGH: Self = Self(0x02);
-            #[doc = "Very high"]
-            pub const VERYHIGH: Self = Self(0x03);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Circ(pub u8);
-        impl Circ {
-            #[doc = "Circular mode disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Circular mode enabled"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Fs(pub u8);
-        impl Fs {
-            #[doc = "0 < fifo_level < 1/4"]
-            pub const QUARTER1: Self = Self(0);
-            #[doc = "1/4 <= fifo_level < 1/2"]
-            pub const QUARTER2: Self = Self(0x01);
-            #[doc = "1/2 <= fifo_level < 3/4"]
-            pub const QUARTER3: Self = Self(0x02);
-            #[doc = "3/4 <= fifo_level < full"]
-            pub const QUARTER4: Self = Self(0x03);
-            #[doc = "FIFO is empty"]
-            pub const EMPTY: Self = Self(0x04);
-            #[doc = "FIFO is full"]
-            pub const FULL: Self = Self(0x05);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Size(pub u8);
-        impl Size {
-            #[doc = "Byte (8-bit)"]
-            pub const BITS8: Self = Self(0);
-            #[doc = "Half-word (16-bit)"]
-            pub const BITS16: Self = Self(0x01);
-            #[doc = "Word (32-bit)"]
-            pub const BITS32: Self = Self(0x02);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dmdis(pub u8);
-        impl Dmdis {
-            #[doc = "Direct mode is enabled"]
-            pub const ENABLED: Self = Self(0);
-            #[doc = "Direct mode is disabled"]
-            pub const DISABLED: Self = Self(0x01);
+        pub struct Lckk(pub u8);
+        impl Lckk {
+            #[doc = "Port configuration lock key not active"]
+            pub const NOTACTIVE: Self = Self(0);
+            #[doc = "Port configuration lock key active"]
+            pub const ACTIVE: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Burst(pub u8);
-        impl Burst {
-            #[doc = "Single transfer"]
-            pub const SINGLE: Self = Self(0);
-            #[doc = "Incremental burst of 4 beats"]
-            pub const INCR4: Self = Self(0x01);
-            #[doc = "Incremental burst of 8 beats"]
-            pub const INCR8: Self = Self(0x02);
-            #[doc = "Incremental burst of 16 beats"]
-            pub const INCR16: Self = Self(0x03);
+        pub struct Mode(pub u8);
+        impl Mode {
+            #[doc = "Input mode (reset state)"]
+            pub const INPUT: Self = Self(0);
+            #[doc = "Output mode 10 MHz"]
+            pub const OUTPUT: Self = Self(0x01);
+            #[doc = "Output mode 2 MHz"]
+            pub const OUTPUT2: Self = Self(0x02);
+            #[doc = "Output mode 50 MHz"]
+            pub const OUTPUT50: Self = Self(0x03);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Inc(pub u8);
-        impl Inc {
-            #[doc = "Address pointer is fixed"]
-            pub const FIXED: Self = Self(0);
-            #[doc = "Address pointer is incremented after each data transfer"]
-            pub const INCREMENTED: Self = Self(0x01);
+        pub struct Cnf(pub u8);
+        impl Cnf {
+            #[doc = "Analog mode / Push-Pull mode"]
+            pub const PUSHPULL: Self = Self(0);
+            #[doc = "Floating input (reset state) / Open Drain-Mode"]
+            pub const OPENDRAIN: Self = Self(0x01);
+            #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"]
+            pub const ALTPUSHPULL: Self = Self(0x02);
+            #[doc = "Alternate Function Open-Drain Mode"]
+            pub const ALTOPENDRAIN: Self = Self(0x03);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dir(pub u8);
-        impl Dir {
-            #[doc = "Peripheral-to-memory"]
-            pub const PERIPHERALTOMEMORY: Self = Self(0);
-            #[doc = "Memory-to-peripheral"]
-            pub const MEMORYTOPERIPHERAL: Self = Self(0x01);
-            #[doc = "Memory-to-memory"]
-            pub const MEMORYTOMEMORY: Self = Self(0x02);
+        pub struct Brw(pub u8);
+        impl Brw {
+            #[doc = "No action on the corresponding ODx bit"]
+            pub const NOACTION: Self = Self(0);
+            #[doc = "Reset the ODx bit"]
+            pub const RESET: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Pfctrl(pub u8);
-        impl Pfctrl {
-            #[doc = "The DMA is the flow controller"]
-            pub const DMA: Self = Self(0);
-            #[doc = "The peripheral is the flow controller"]
-            pub const PERIPHERAL: Self = Self(0x01);
+        pub struct Odr(pub u8);
+        impl Odr {
+            #[doc = "Set output to logic low"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Set output to logic high"]
+            pub const HIGH: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Fth(pub u8);
-        impl Fth {
-            #[doc = "1/4 full FIFO"]
-            pub const QUARTER: Self = Self(0);
-            #[doc = "1/2 full FIFO"]
-            pub const HALF: Self = Self(0x01);
-            #[doc = "3/4 full FIFO"]
-            pub const THREEQUARTERS: Self = Self(0x02);
-            #[doc = "Full FIFO"]
-            pub const FULL: Self = Self(0x03);
+        pub struct Idr(pub u8);
+        impl Idr {
+            #[doc = "Input is logic low"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Input is logic high"]
+            pub const HIGH: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dbm(pub u8);
-        impl Dbm {
-            #[doc = "No buffer switching at the end of transfer"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Memory target switched at the end of the DMA transfer"]
-            pub const ENABLED: Self = Self(0x01);
+        pub struct Lck(pub u8);
+        impl Lck {
+            #[doc = "Port configuration not locked"]
+            pub const UNLOCKED: Self = Self(0);
+            #[doc = "Port configuration locked"]
+            pub const LOCKED: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Pincos(pub u8);
-        impl Pincos {
-            #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"]
-            pub const PSIZE: Self = Self(0);
-            #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"]
-            pub const FIXED4: Self = Self(0x01);
+        pub struct Bsw(pub u8);
+        impl Bsw {
+            #[doc = "No action on the corresponding ODx bit"]
+            pub const NOACTION: Self = Self(0);
+            #[doc = "Sets the corresponding ODRx bit"]
+            pub const SET: Self = Self(0x01);
         }
     }
 }
@@ -652,30 +458,6 @@ pub mod gpio_v2 {
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "GPIO port mode register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Moder(pub u32);
-        impl Moder {
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn moder(&self, n: usize) -> super::vals::Moder {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 2usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::Moder(val as u8)
-            }
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 2usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
-            }
-        }
-        impl Default for Moder {
-            fn default() -> Moder {
-                Moder(0)
-            }
-        }
         #[doc = "GPIO alternate function register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -700,54 +482,6 @@ pub mod gpio_v2 {
                 Afr(0)
             }
         }
-        #[doc = "GPIO port input data register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Idr(pub u32);
-        impl Idr {
-            #[doc = "Port input data (y = 0..15)"]
-            pub fn idr(&self, n: usize) -> super::vals::Idr {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Idr(val as u8)
-            }
-            #[doc = "Port input data (y = 0..15)"]
-            pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
-            }
-        }
-        impl Default for Idr {
-            fn default() -> Idr {
-                Idr(0)
-            }
-        }
-        #[doc = "GPIO port pull-up/pull-down register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Pupdr(pub u32);
-        impl Pupdr {
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn pupdr(&self, n: usize) -> super::vals::Pupdr {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 2usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::Pupdr(val as u8)
-            }
-            #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 2usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
-            }
-        }
-        impl Default for Pupdr {
-            fn default() -> Pupdr {
-                Pupdr(0)
-            }
-        }
         #[doc = "GPIO port output data register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -796,6 +530,54 @@ pub mod gpio_v2 {
                 Otyper(0)
             }
         }
+        #[doc = "GPIO port pull-up/pull-down register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Pupdr(pub u32);
+        impl Pupdr {
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn pupdr(&self, n: usize) -> super::vals::Pupdr {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 2usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::Pupdr(val as u8)
+            }
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 2usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
+            }
+        }
+        impl Default for Pupdr {
+            fn default() -> Pupdr {
+                Pupdr(0)
+            }
+        }
+        #[doc = "GPIO port output speed register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ospeedr(pub u32);
+        impl Ospeedr {
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 2usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::Ospeedr(val as u8)
+            }
+            #[doc = "Port x configuration bits (y = 0..15)"]
+            pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 2usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
+            }
+        }
+        impl Default for Ospeedr {
+            fn default() -> Ospeedr {
+                Ospeedr(0)
+            }
+        }
         #[doc = "GPIO port configuration lock register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -829,28 +611,28 @@ pub mod gpio_v2 {
                 Lckr(0)
             }
         }
-        #[doc = "GPIO port output speed register"]
+        #[doc = "GPIO port mode register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ospeedr(pub u32);
-        impl Ospeedr {
+        pub struct Moder(pub u32);
+        impl Moder {
             #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr {
+            pub fn moder(&self, n: usize) -> super::vals::Moder {
                 assert!(n < 16usize);
                 let offs = 0usize + n * 2usize;
                 let val = (self.0 >> offs) & 0x03;
-                super::vals::Ospeedr(val as u8)
+                super::vals::Moder(val as u8)
             }
             #[doc = "Port x configuration bits (y = 0..15)"]
-            pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) {
+            pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) {
                 assert!(n < 16usize);
                 let offs = 0usize + n * 2usize;
                 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
             }
         }
-        impl Default for Ospeedr {
-            fn default() -> Ospeedr {
-                Ospeedr(0)
+        impl Default for Moder {
+            fn default() -> Moder {
+                Moder(0)
             }
         }
         #[doc = "GPIO port bit set/reset register"]
@@ -890,11 +672,91 @@ pub mod gpio_v2 {
                 Bsrr(0)
             }
         }
+        #[doc = "GPIO port input data register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Idr(pub u32);
+        impl Idr {
+            #[doc = "Port input data (y = 0..15)"]
+            pub fn idr(&self, n: usize) -> super::vals::Idr {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Idr(val as u8)
+            }
+            #[doc = "Port input data (y = 0..15)"]
+            pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
+                assert!(n < 16usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            }
+        }
+        impl Default for Idr {
+            fn default() -> Idr {
+                Idr(0)
+            }
+        }
     }
     pub mod vals {
         use crate::generic::*;
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ot(pub u8);
+        impl Ot {
+            #[doc = "Output push-pull (reset state)"]
+            pub const PUSHPULL: Self = Self(0);
+            #[doc = "Output open-drain"]
+            pub const OPENDRAIN: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Pupdr(pub u8);
+        impl Pupdr {
+            #[doc = "No pull-up, pull-down"]
+            pub const FLOATING: Self = Self(0);
+            #[doc = "Pull-up"]
+            pub const PULLUP: Self = Self(0x01);
+            #[doc = "Pull-down"]
+            pub const PULLDOWN: Self = Self(0x02);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Bsw(pub u8);
+        impl Bsw {
+            #[doc = "Sets the corresponding ODRx bit"]
+            pub const SET: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Moder(pub u8);
+        impl Moder {
+            #[doc = "Input mode (reset state)"]
+            pub const INPUT: Self = Self(0);
+            #[doc = "General purpose output mode"]
+            pub const OUTPUT: Self = Self(0x01);
+            #[doc = "Alternate function mode"]
+            pub const ALTERNATE: Self = Self(0x02);
+            #[doc = "Analog mode"]
+            pub const ANALOG: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Idr(pub u8);
+        impl Idr {
+            #[doc = "Input is logic low"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Input is logic high"]
+            pub const HIGH: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Brw(pub u8);
+        impl Brw {
+            #[doc = "Resets the corresponding ODRx bit"]
+            pub const RESET: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
         pub struct Lck(pub u8);
         impl Lck {
             #[doc = "Port configuration not locked"]
@@ -904,12 +766,12 @@ pub mod gpio_v2 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ot(pub u8);
-        impl Ot {
-            #[doc = "Output push-pull (reset state)"]
-            pub const PUSHPULL: Self = Self(0);
-            #[doc = "Output open-drain"]
-            pub const OPENDRAIN: Self = Self(0x01);
+        pub struct Lckk(pub u8);
+        impl Lckk {
+            #[doc = "Port configuration lock key not active"]
+            pub const NOTACTIVE: Self = Self(0);
+            #[doc = "Port configuration lock key active"]
+            pub const ACTIVE: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -963,44 +825,6 @@ pub mod gpio_v2 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Pupdr(pub u8);
-        impl Pupdr {
-            #[doc = "No pull-up, pull-down"]
-            pub const FLOATING: Self = Self(0);
-            #[doc = "Pull-up"]
-            pub const PULLUP: Self = Self(0x01);
-            #[doc = "Pull-down"]
-            pub const PULLDOWN: Self = Self(0x02);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Bsw(pub u8);
-        impl Bsw {
-            #[doc = "Sets the corresponding ODRx bit"]
-            pub const SET: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Brw(pub u8);
-        impl Brw {
-            #[doc = "Resets the corresponding ODRx bit"]
-            pub const RESET: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Moder(pub u8);
-        impl Moder {
-            #[doc = "Input mode (reset state)"]
-            pub const INPUT: Self = Self(0);
-            #[doc = "General purpose output mode"]
-            pub const OUTPUT: Self = Self(0x01);
-            #[doc = "Alternate function mode"]
-            pub const ALTERNATE: Self = Self(0x02);
-            #[doc = "Analog mode"]
-            pub const ANALOG: Self = Self(0x03);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
         pub struct Odr(pub u8);
         impl Odr {
             #[doc = "Set output to logic low"]
@@ -1008,104 +832,350 @@ pub mod gpio_v2 {
             #[doc = "Set output to logic high"]
             pub const HIGH: Self = Self(0x01);
         }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Lckk(pub u8);
-        impl Lckk {
-            #[doc = "Port configuration lock key not active"]
-            pub const NOTACTIVE: Self = Self(0);
-            #[doc = "Port configuration lock key active"]
-            pub const ACTIVE: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Idr(pub u8);
-        impl Idr {
-            #[doc = "Input is logic low"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Input is logic high"]
-            pub const HIGH: Self = Self(0x01);
-        }
     }
 }
-pub mod generic {
-    use core::marker::PhantomData;
-    #[derive(Copy, Clone)]
-    pub struct RW;
-    #[derive(Copy, Clone)]
-    pub struct R;
-    #[derive(Copy, Clone)]
-    pub struct W;
-    mod sealed {
-        use super::*;
-        pub trait Access {}
-        impl Access for R {}
-        impl Access for W {}
-        impl Access for RW {}
-    }
-    pub trait Access: sealed::Access + Copy {}
-    impl Access for R {}
-    impl Access for W {}
-    impl Access for RW {}
-    pub trait Read: Access {}
-    impl Read for RW {}
-    impl Read for R {}
-    pub trait Write: Access {}
-    impl Write for RW {}
-    impl Write for W {}
+pub mod syscfg_l4 {
+    use crate::generic::*;
+    #[doc = "System configuration controller"]
     #[derive(Copy, Clone)]
-    pub struct Reg<T: Copy, A: Access> {
-        ptr: *mut u8,
-        phantom: PhantomData<*mut (T, A)>,
+    pub struct Syscfg(pub *mut u8);
+    unsafe impl Send for Syscfg {}
+    unsafe impl Sync for Syscfg {}
+    impl Syscfg {
+        #[doc = "memory remap register"]
+        pub fn memrmp(self) -> Reg<regs::Memrmp, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "configuration register 1"]
+        pub fn cfgr1(self) -> Reg<regs::Cfgr1, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "external interrupt configuration register 1"]
+        pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
+            assert!(n < 4usize);
+            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
+        }
+        #[doc = "SCSR"]
+        pub fn scsr(self) -> Reg<regs::Scsr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+        }
+        #[doc = "CFGR2"]
+        pub fn cfgr2(self) -> Reg<regs::Cfgr2, RW> {
+            unsafe { Reg::from_ptr(self.0.add(28usize)) }
+        }
+        #[doc = "SWPR"]
+        pub fn swpr(self) -> Reg<regs::Swpr, W> {
+            unsafe { Reg::from_ptr(self.0.add(32usize)) }
+        }
+        #[doc = "SKR"]
+        pub fn skr(self) -> Reg<regs::Skr, W> {
+            unsafe { Reg::from_ptr(self.0.add(36usize)) }
+        }
     }
-    unsafe impl<T: Copy, A: Access> Send for Reg<T, A> {}
-    unsafe impl<T: Copy, A: Access> Sync for Reg<T, A> {}
-    impl<T: Copy, A: Access> Reg<T, A> {
-        pub fn from_ptr(ptr: *mut u8) -> Self {
-            Self {
-                ptr,
-                phantom: PhantomData,
+    pub mod regs {
+        use crate::generic::*;
+        #[doc = "SCSR"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Scsr(pub u32);
+        impl Scsr {
+            #[doc = "SRAM2 Erase"]
+            pub const fn sram2er(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "SRAM2 Erase"]
+            pub fn set_sram2er(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "SRAM2 busy by erase operation"]
+            pub const fn sram2bsy(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
+            }
+            #[doc = "SRAM2 busy by erase operation"]
+            pub fn set_sram2bsy(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
         }
-        pub fn ptr(&self) -> *mut T {
-            self.ptr as _
+        impl Default for Scsr {
+            fn default() -> Scsr {
+                Scsr(0)
+            }
         }
-    }
-    impl<T: Copy, A: Read> Reg<T, A> {
-        pub unsafe fn read(&self) -> T {
-            (self.ptr as *mut T).read_volatile()
+        #[doc = "CFGR2"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cfgr2(pub u32);
+        impl Cfgr2 {
+            #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
+            pub const fn cll(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
+            pub fn set_cll(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "SRAM2 parity lock bit"]
+            pub const fn spl(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
+            }
+            #[doc = "SRAM2 parity lock bit"]
+            pub fn set_spl(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            }
+            #[doc = "PVD lock enable bit"]
+            pub const fn pvdl(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
+                val != 0
+            }
+            #[doc = "PVD lock enable bit"]
+            pub fn set_pvdl(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            }
+            #[doc = "ECC Lock"]
+            pub const fn eccl(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
+            }
+            #[doc = "ECC Lock"]
+            pub fn set_eccl(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
+            #[doc = "SRAM2 parity error flag"]
+            pub const fn spf(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "SRAM2 parity error flag"]
+            pub fn set_spf(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
         }
-    }
-    impl<T: Copy, A: Write> Reg<T, A> {
-        pub unsafe fn write_value(&self, val: T) {
-            (self.ptr as *mut T).write_volatile(val)
+        impl Default for Cfgr2 {
+            fn default() -> Cfgr2 {
+                Cfgr2(0)
+            }
         }
-    }
-    impl<T: Default + Copy, A: Write> Reg<T, A> {
-        pub unsafe fn write<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
-            let mut val = Default::default();
-            let res = f(&mut val);
-            self.write_value(val);
-            res
+        #[doc = "configuration register 1"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cfgr1(pub u32);
+        impl Cfgr1 {
+            #[doc = "Firewall disable"]
+            pub const fn fwdis(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Firewall disable"]
+            pub fn set_fwdis(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "I/O analog switch voltage booster enable"]
+            pub const fn boosten(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "I/O analog switch voltage booster enable"]
+            pub fn set_boosten(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
+            pub const fn i2c_pb6_fmp(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
+            pub fn set_i2c_pb6_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
+            pub const fn i2c_pb7_fmp(&self) -> bool {
+                let val = (self.0 >> 17usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
+            pub fn set_i2c_pb7_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
+            pub const fn i2c_pb8_fmp(&self) -> bool {
+                let val = (self.0 >> 18usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
+            pub fn set_i2c_pb8_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
+            pub const fn i2c_pb9_fmp(&self) -> bool {
+                let val = (self.0 >> 19usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
+            pub fn set_i2c_pb9_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+            }
+            #[doc = "I2C1 Fast-mode Plus driving capability activation"]
+            pub const fn i2c1_fmp(&self) -> bool {
+                let val = (self.0 >> 20usize) & 0x01;
+                val != 0
+            }
+            #[doc = "I2C1 Fast-mode Plus driving capability activation"]
+            pub fn set_i2c1_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+            }
+            #[doc = "I2C2 Fast-mode Plus driving capability activation"]
+            pub const fn i2c2_fmp(&self) -> bool {
+                let val = (self.0 >> 21usize) & 0x01;
+                val != 0
+            }
+            #[doc = "I2C2 Fast-mode Plus driving capability activation"]
+            pub fn set_i2c2_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+            }
+            #[doc = "I2C3 Fast-mode Plus driving capability activation"]
+            pub const fn i2c3_fmp(&self) -> bool {
+                let val = (self.0 >> 22usize) & 0x01;
+                val != 0
+            }
+            #[doc = "I2C3 Fast-mode Plus driving capability activation"]
+            pub fn set_i2c3_fmp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+            }
+            #[doc = "Floating Point Unit interrupts enable bits"]
+            pub const fn fpu_ie(&self) -> u8 {
+                let val = (self.0 >> 26usize) & 0x3f;
+                val as u8
+            }
+            #[doc = "Floating Point Unit interrupts enable bits"]
+            pub fn set_fpu_ie(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize);
+            }
         }
-    }
-    impl<T: Copy, A: Read + Write> Reg<T, A> {
-        pub unsafe fn modify<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
-            let mut val = self.read();
-            let res = f(&mut val);
-            self.write_value(val);
-            res
+        impl Default for Cfgr1 {
+            fn default() -> Cfgr1 {
+                Cfgr1(0)
+            }
+        }
+        #[doc = "external interrupt configuration register 4"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Exticr(pub u32);
+        impl Exticr {
+            #[doc = "EXTI12 configuration bits"]
+            pub fn exti(&self, n: usize) -> u8 {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x0f;
+                val as u8
+            }
+            #[doc = "EXTI12 configuration bits"]
+            pub fn set_exti(&mut self, n: usize, val: u8) {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
+            }
+        }
+        impl Default for Exticr {
+            fn default() -> Exticr {
+                Exticr(0)
+            }
+        }
+        #[doc = "SKR"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Skr(pub u32);
+        impl Skr {
+            #[doc = "SRAM2 write protection key for software erase"]
+            pub const fn key(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0xff;
+                val as u8
+            }
+            #[doc = "SRAM2 write protection key for software erase"]
+            pub fn set_key(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+            }
+        }
+        impl Default for Skr {
+            fn default() -> Skr {
+                Skr(0)
+            }
+        }
+        #[doc = "memory remap register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Memrmp(pub u32);
+        impl Memrmp {
+            #[doc = "Memory mapping selection"]
+            pub const fn mem_mode(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x07;
+                val as u8
+            }
+            #[doc = "Memory mapping selection"]
+            pub fn set_mem_mode(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+            }
+            #[doc = "QUADSPI memory mapping swap"]
+            pub const fn qfs(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
+            }
+            #[doc = "QUADSPI memory mapping swap"]
+            pub fn set_qfs(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
+            #[doc = "Flash Bank mode selection"]
+            pub const fn fb_mode(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Flash Bank mode selection"]
+            pub fn set_fb_mode(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+        }
+        impl Default for Memrmp {
+            fn default() -> Memrmp {
+                Memrmp(0)
+            }
+        }
+        #[doc = "SWPR"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Swpr(pub u32);
+        impl Swpr {
+            #[doc = "SRAWM2 write protection."]
+            pub fn pwp(&self, n: usize) -> bool {
+                assert!(n < 32usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "SRAWM2 write protection."]
+            pub fn set_pwp(&mut self, n: usize, val: bool) {
+                assert!(n < 32usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+        }
+        impl Default for Swpr {
+            fn default() -> Swpr {
+                Swpr(0)
+            }
         }
     }
 }
 pub mod usart_v1 {
     use crate::generic::*;
-    #[doc = "Universal synchronous asynchronous receiver transmitter"]
+    #[doc = "Universal asynchronous receiver transmitter"]
     #[derive(Copy, Clone)]
-    pub struct Usart(pub *mut u8);
-    unsafe impl Send for Usart {}
-    unsafe impl Sync for Usart {}
-    impl Usart {
+    pub struct Uart(pub *mut u8);
+    unsafe impl Send for Uart {}
+    unsafe impl Sync for Uart {}
+    impl Uart {
         #[doc = "Status register"]
         pub fn sr(self) -> Reg<regs::Sr, RW> {
             unsafe { Reg::from_ptr(self.0.add(0usize)) }
@@ -1123,24 +1193,20 @@ pub mod usart_v1 {
             unsafe { Reg::from_ptr(self.0.add(12usize)) }
         }
         #[doc = "Control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2Usart, RW> {
+        pub fn cr2(self) -> Reg<regs::Cr2, RW> {
             unsafe { Reg::from_ptr(self.0.add(16usize)) }
         }
         #[doc = "Control register 3"]
-        pub fn cr3(self) -> Reg<regs::Cr3Usart, RW> {
+        pub fn cr3(self) -> Reg<regs::Cr3, RW> {
             unsafe { Reg::from_ptr(self.0.add(20usize)) }
         }
-        #[doc = "Guard time and prescaler register"]
-        pub fn gtpr(self) -> Reg<regs::Gtpr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(24usize)) }
-        }
     }
-    #[doc = "Universal asynchronous receiver transmitter"]
+    #[doc = "Universal synchronous asynchronous receiver transmitter"]
     #[derive(Copy, Clone)]
-    pub struct Uart(pub *mut u8);
-    unsafe impl Send for Uart {}
-    unsafe impl Sync for Uart {}
-    impl Uart {
+    pub struct Usart(pub *mut u8);
+    unsafe impl Send for Usart {}
+    unsafe impl Sync for Usart {}
+    impl Usart {
         #[doc = "Status register"]
         pub fn sr(self) -> Reg<regs::Sr, RW> {
             unsafe { Reg::from_ptr(self.0.add(0usize)) }
@@ -1158,24 +1224,28 @@ pub mod usart_v1 {
             unsafe { Reg::from_ptr(self.0.add(12usize)) }
         }
         #[doc = "Control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2, RW> {
+        pub fn cr2(self) -> Reg<regs::Cr2Usart, RW> {
             unsafe { Reg::from_ptr(self.0.add(16usize)) }
         }
         #[doc = "Control register 3"]
-        pub fn cr3(self) -> Reg<regs::Cr3, RW> {
+        pub fn cr3(self) -> Reg<regs::Cr3Usart, RW> {
             unsafe { Reg::from_ptr(self.0.add(20usize)) }
         }
+        #[doc = "Guard time and prescaler register"]
+        pub fn gtpr(self) -> Reg<regs::Gtpr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+        }
     }
     pub mod vals {
         use crate::generic::*;
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Irlp(pub u8);
-        impl Irlp {
-            #[doc = "Normal mode"]
-            pub const NORMAL: Self = Self(0);
-            #[doc = "Low-power mode"]
-            pub const LOWPOWER: Self = Self(0x01);
+        pub struct Ps(pub u8);
+        impl Ps {
+            #[doc = "Even parity"]
+            pub const EVEN: Self = Self(0);
+            #[doc = "Odd parity"]
+            pub const ODD: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -1188,6 +1258,37 @@ pub mod usart_v1 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Sbk(pub u8);
+        impl Sbk {
+            #[doc = "No break character is transmitted"]
+            pub const NOBREAK: Self = Self(0);
+            #[doc = "Break character transmitted"]
+            pub const BREAK: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Stop(pub u8);
+        impl Stop {
+            #[doc = "1 stop bit"]
+            pub const STOP1: Self = Self(0);
+            #[doc = "0.5 stop bits"]
+            pub const STOP0P5: Self = Self(0x01);
+            #[doc = "2 stop bits"]
+            pub const STOP2: Self = Self(0x02);
+            #[doc = "1.5 stop bits"]
+            pub const STOP1P5: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Hdsel(pub u8);
+        impl Hdsel {
+            #[doc = "Half duplex mode is not selected"]
+            pub const FULLDUPLEX: Self = Self(0);
+            #[doc = "Half duplex mode is selected"]
+            pub const HALFDUPLEX: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
         pub struct Wake(pub u8);
         impl Wake {
             #[doc = "USART wakeup on idle line"]
@@ -1197,12 +1298,12 @@ pub mod usart_v1 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cpha(pub u8);
-        impl Cpha {
-            #[doc = "The first clock transition is the first data capture edge"]
-            pub const FIRST: Self = Self(0);
-            #[doc = "The second clock transition is the first data capture edge"]
-            pub const SECOND: Self = Self(0x01);
+        pub struct Rwu(pub u8);
+        impl Rwu {
+            #[doc = "Receiver in active mode"]
+            pub const ACTIVE: Self = Self(0);
+            #[doc = "Receiver in mute mode"]
+            pub const MUTE: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -1215,33 +1316,6 @@ pub mod usart_v1 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ps(pub u8);
-        impl Ps {
-            #[doc = "Even parity"]
-            pub const EVEN: Self = Self(0);
-            #[doc = "Odd parity"]
-            pub const ODD: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Sbk(pub u8);
-        impl Sbk {
-            #[doc = "No break character is transmitted"]
-            pub const NOBREAK: Self = Self(0);
-            #[doc = "Break character transmitted"]
-            pub const BREAK: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Hdsel(pub u8);
-        impl Hdsel {
-            #[doc = "Half duplex mode is not selected"]
-            pub const FULLDUPLEX: Self = Self(0);
-            #[doc = "Half duplex mode is selected"]
-            pub const HALFDUPLEX: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
         pub struct Cpol(pub u8);
         impl Cpol {
             #[doc = "Steady low value on CK pin outside transmission window"]
@@ -1251,25 +1325,21 @@ pub mod usart_v1 {
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Rwu(pub u8);
-        impl Rwu {
-            #[doc = "Receiver in active mode"]
-            pub const ACTIVE: Self = Self(0);
-            #[doc = "Receiver in mute mode"]
-            pub const MUTE: Self = Self(0x01);
+        pub struct Cpha(pub u8);
+        impl Cpha {
+            #[doc = "The first clock transition is the first data capture edge"]
+            pub const FIRST: Self = Self(0);
+            #[doc = "The second clock transition is the first data capture edge"]
+            pub const SECOND: Self = Self(0x01);
         }
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Stop(pub u8);
-        impl Stop {
-            #[doc = "1 stop bit"]
-            pub const STOP1: Self = Self(0);
-            #[doc = "0.5 stop bits"]
-            pub const STOP0P5: Self = Self(0x01);
-            #[doc = "2 stop bits"]
-            pub const STOP2: Self = Self(0x02);
-            #[doc = "1.5 stop bits"]
-            pub const STOP1P5: Self = Self(0x03);
+        pub struct Irlp(pub u8);
+        impl Irlp {
+            #[doc = "Normal mode"]
+            pub const NORMAL: Self = Self(0);
+            #[doc = "Low-power mode"]
+            pub const LOWPOWER: Self = Self(0x01);
         }
     }
     pub mod regs {
@@ -1277,217 +1347,6 @@ pub mod usart_v1 {
         #[doc = "Control register 3"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr3Usart(pub u32);
-        impl Cr3Usart {
-            #[doc = "Error interrupt enable"]
-            pub const fn eie(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Error interrupt enable"]
-            pub fn set_eie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "IrDA mode enable"]
-            pub const fn iren(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
-            }
-            #[doc = "IrDA mode enable"]
-            pub fn set_iren(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
-            }
-            #[doc = "IrDA low-power"]
-            pub const fn irlp(&self) -> super::vals::Irlp {
-                let val = (self.0 >> 2usize) & 0x01;
-                super::vals::Irlp(val as u8)
-            }
-            #[doc = "IrDA low-power"]
-            pub fn set_irlp(&mut self, val: super::vals::Irlp) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
-            }
-            #[doc = "Half-duplex selection"]
-            pub const fn hdsel(&self) -> super::vals::Hdsel {
-                let val = (self.0 >> 3usize) & 0x01;
-                super::vals::Hdsel(val as u8)
-            }
-            #[doc = "Half-duplex selection"]
-            pub fn set_hdsel(&mut self, val: super::vals::Hdsel) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
-            }
-            #[doc = "Smartcard NACK enable"]
-            pub const fn nack(&self) -> bool {
-                let val = (self.0 >> 4usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Smartcard NACK enable"]
-            pub fn set_nack(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
-            }
-            #[doc = "Smartcard mode enable"]
-            pub const fn scen(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Smartcard mode enable"]
-            pub fn set_scen(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
-            }
-            #[doc = "DMA enable receiver"]
-            pub const fn dmar(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "DMA enable receiver"]
-            pub fn set_dmar(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-            #[doc = "DMA enable transmitter"]
-            pub const fn dmat(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
-                val != 0
-            }
-            #[doc = "DMA enable transmitter"]
-            pub fn set_dmat(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
-            }
-            #[doc = "RTS enable"]
-            pub const fn rtse(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "RTS enable"]
-            pub fn set_rtse(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-            #[doc = "CTS enable"]
-            pub const fn ctse(&self) -> bool {
-                let val = (self.0 >> 9usize) & 0x01;
-                val != 0
-            }
-            #[doc = "CTS enable"]
-            pub fn set_ctse(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
-            }
-            #[doc = "CTS interrupt enable"]
-            pub const fn ctsie(&self) -> bool {
-                let val = (self.0 >> 10usize) & 0x01;
-                val != 0
-            }
-            #[doc = "CTS interrupt enable"]
-            pub fn set_ctsie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
-            }
-        }
-        impl Default for Cr3Usart {
-            fn default() -> Cr3Usart {
-                Cr3Usart(0)
-            }
-        }
-        #[doc = "Status register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct SrUsart(pub u32);
-        impl SrUsart {
-            #[doc = "Parity error"]
-            pub const fn pe(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Parity error"]
-            pub fn set_pe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Framing error"]
-            pub const fn fe(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Framing error"]
-            pub fn set_fe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
-            }
-            #[doc = "Noise error flag"]
-            pub const fn ne(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Noise error flag"]
-            pub fn set_ne(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
-            }
-            #[doc = "Overrun error"]
-            pub const fn ore(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Overrun error"]
-            pub fn set_ore(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
-            }
-            #[doc = "IDLE line detected"]
-            pub const fn idle(&self) -> bool {
-                let val = (self.0 >> 4usize) & 0x01;
-                val != 0
-            }
-            #[doc = "IDLE line detected"]
-            pub fn set_idle(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
-            }
-            #[doc = "Read data register not empty"]
-            pub const fn rxne(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Read data register not empty"]
-            pub fn set_rxne(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
-            }
-            #[doc = "Transmission complete"]
-            pub const fn tc(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Transmission complete"]
-            pub fn set_tc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-            #[doc = "Transmit data register empty"]
-            pub const fn txe(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Transmit data register empty"]
-            pub fn set_txe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
-            }
-            #[doc = "LIN break detection flag"]
-            pub const fn lbd(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "LIN break detection flag"]
-            pub fn set_lbd(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-            #[doc = "CTS flag"]
-            pub const fn cts(&self) -> bool {
-                let val = (self.0 >> 9usize) & 0x01;
-                val != 0
-            }
-            #[doc = "CTS flag"]
-            pub fn set_cts(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
-            }
-        }
-        impl Default for SrUsart {
-            fn default() -> SrUsart {
-                SrUsart(0)
-            }
-        }
-        #[doc = "Control register 3"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
         pub struct Cr3(pub u32);
         impl Cr3 {
             #[doc = "Error interrupt enable"]
@@ -1606,147 +1465,6 @@ pub mod usart_v1 {
                 Cr2(0)
             }
         }
-        #[doc = "Status register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Sr(pub u32);
-        impl Sr {
-            #[doc = "Parity error"]
-            pub const fn pe(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Parity error"]
-            pub fn set_pe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Framing error"]
-            pub const fn fe(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Framing error"]
-            pub fn set_fe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
-            }
-            #[doc = "Noise error flag"]
-            pub const fn ne(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Noise error flag"]
-            pub fn set_ne(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
-            }
-            #[doc = "Overrun error"]
-            pub const fn ore(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Overrun error"]
-            pub fn set_ore(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
-            }
-            #[doc = "IDLE line detected"]
-            pub const fn idle(&self) -> bool {
-                let val = (self.0 >> 4usize) & 0x01;
-                val != 0
-            }
-            #[doc = "IDLE line detected"]
-            pub fn set_idle(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
-            }
-            #[doc = "Read data register not empty"]
-            pub const fn rxne(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Read data register not empty"]
-            pub fn set_rxne(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
-            }
-            #[doc = "Transmission complete"]
-            pub const fn tc(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Transmission complete"]
-            pub fn set_tc(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-            #[doc = "Transmit data register empty"]
-            pub const fn txe(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Transmit data register empty"]
-            pub fn set_txe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
-            }
-            #[doc = "LIN break detection flag"]
-            pub const fn lbd(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "LIN break detection flag"]
-            pub fn set_lbd(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-        }
-        impl Default for Sr {
-            fn default() -> Sr {
-                Sr(0)
-            }
-        }
-        #[doc = "Data register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dr(pub u32);
-        impl Dr {
-            #[doc = "Data value"]
-            pub const fn dr(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0x01ff;
-                val as u16
-            }
-            #[doc = "Data value"]
-            pub fn set_dr(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
-            }
-        }
-        impl Default for Dr {
-            fn default() -> Dr {
-                Dr(0)
-            }
-        }
-        #[doc = "Baud rate register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Brr(pub u32);
-        impl Brr {
-            #[doc = "fraction of USARTDIV"]
-            pub const fn div_fraction(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x0f;
-                val as u8
-            }
-            #[doc = "fraction of USARTDIV"]
-            pub fn set_div_fraction(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
-            }
-            #[doc = "mantissa of USARTDIV"]
-            pub const fn div_mantissa(&self) -> u16 {
-                let val = (self.0 >> 4usize) & 0x0fff;
-                val as u16
-            }
-            #[doc = "mantissa of USARTDIV"]
-            pub fn set_div_mantissa(&mut self, val: u16) {
-                self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize);
-            }
-        }
-        impl Default for Brr {
-            fn default() -> Brr {
-                Brr(0)
-            }
-        }
         #[doc = "Control register 2"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -1868,6 +1586,98 @@ pub mod usart_v1 {
                 Gtpr(0)
             }
         }
+        #[doc = "Status register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Sr(pub u32);
+        impl Sr {
+            #[doc = "Parity error"]
+            pub const fn pe(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Parity error"]
+            pub fn set_pe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Framing error"]
+            pub const fn fe(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Framing error"]
+            pub fn set_fe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            }
+            #[doc = "Noise error flag"]
+            pub const fn ne(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Noise error flag"]
+            pub fn set_ne(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            }
+            #[doc = "Overrun error"]
+            pub const fn ore(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Overrun error"]
+            pub fn set_ore(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
+            #[doc = "IDLE line detected"]
+            pub const fn idle(&self) -> bool {
+                let val = (self.0 >> 4usize) & 0x01;
+                val != 0
+            }
+            #[doc = "IDLE line detected"]
+            pub fn set_idle(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+            }
+            #[doc = "Read data register not empty"]
+            pub const fn rxne(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Read data register not empty"]
+            pub fn set_rxne(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
+            }
+            #[doc = "Transmission complete"]
+            pub const fn tc(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Transmission complete"]
+            pub fn set_tc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+            #[doc = "Transmit data register empty"]
+            pub const fn txe(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Transmit data register empty"]
+            pub fn set_txe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
+            }
+            #[doc = "LIN break detection flag"]
+            pub const fn lbd(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "LIN break detection flag"]
+            pub fn set_lbd(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+        }
+        impl Default for Sr {
+            fn default() -> Sr {
+                Sr(0)
+            }
+        }
         #[doc = "Control register 1"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -2005,465 +1815,438 @@ pub mod usart_v1 {
                 Cr1(0)
             }
         }
-    }
-}
-pub mod dma_v1 {
-    use crate::generic::*;
-    #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
-    #[derive(Copy, Clone)]
-    pub struct Ch(pub *mut u8);
-    unsafe impl Send for Ch {}
-    unsafe impl Sync for Ch {}
-    impl Ch {
-        #[doc = "DMA channel configuration register (DMA_CCR)"]
-        pub fn cr(self) -> Reg<regs::Cr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "DMA channel 1 number of data register"]
-        pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "DMA channel 1 peripheral address register"]
-        pub fn par(self) -> Reg<u32, RW> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
-        }
-        #[doc = "DMA channel 1 memory address register"]
-        pub fn mar(self) -> Reg<u32, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
-    }
-    #[doc = "DMA controller"]
-    #[derive(Copy, Clone)]
-    pub struct Dma(pub *mut u8);
-    unsafe impl Send for Dma {}
-    unsafe impl Sync for Dma {}
-    impl Dma {
-        #[doc = "DMA interrupt status register (DMA_ISR)"]
-        pub fn isr(self) -> Reg<regs::Isr, R> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
-        pub fn ifcr(self) -> Reg<regs::Ifcr, W> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
-        pub fn ch(self, n: usize) -> Ch {
-            assert!(n < 7usize);
-            unsafe { Ch(self.0.add(8usize + n * 20usize)) }
-        }
-    }
-    pub mod vals {
-        use crate::generic::*;
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Size(pub u8);
-        impl Size {
-            #[doc = "8-bit size"]
-            pub const BITS8: Self = Self(0);
-            #[doc = "16-bit size"]
-            pub const BITS16: Self = Self(0x01);
-            #[doc = "32-bit size"]
-            pub const BITS32: Self = Self(0x02);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Circ(pub u8);
-        impl Circ {
-            #[doc = "Circular buffer disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Circular buffer enabled"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dir(pub u8);
-        impl Dir {
-            #[doc = "Read from peripheral"]
-            pub const FROMPERIPHERAL: Self = Self(0);
-            #[doc = "Read from memory"]
-            pub const FROMMEMORY: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Pl(pub u8);
-        impl Pl {
-            #[doc = "Low priority"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Medium priority"]
-            pub const MEDIUM: Self = Self(0x01);
-            #[doc = "High priority"]
-            pub const HIGH: Self = Self(0x02);
-            #[doc = "Very high priority"]
-            pub const VERYHIGH: Self = Self(0x03);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Memmem(pub u8);
-        impl Memmem {
-            #[doc = "Memory to memory mode disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Memory to memory mode enabled"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Inc(pub u8);
-        impl Inc {
-            #[doc = "Increment mode disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Increment mode enabled"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-    }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "DMA channel 1 number of data register"]
+        #[doc = "Baud rate register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ndtr(pub u32);
-        impl Ndtr {
-            #[doc = "Number of data to transfer"]
-            pub const fn ndt(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
+        pub struct Brr(pub u32);
+        impl Brr {
+            #[doc = "fraction of USARTDIV"]
+            pub const fn div_fraction(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x0f;
+                val as u8
+            }
+            #[doc = "fraction of USARTDIV"]
+            pub fn set_div_fraction(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
+            }
+            #[doc = "mantissa of USARTDIV"]
+            pub const fn div_mantissa(&self) -> u16 {
+                let val = (self.0 >> 4usize) & 0x0fff;
                 val as u16
             }
-            #[doc = "Number of data to transfer"]
-            pub fn set_ndt(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            #[doc = "mantissa of USARTDIV"]
+            pub fn set_div_mantissa(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize);
             }
         }
-        impl Default for Ndtr {
-            fn default() -> Ndtr {
-                Ndtr(0)
+        impl Default for Brr {
+            fn default() -> Brr {
+                Brr(0)
             }
         }
-        #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
+        #[doc = "Status register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ifcr(pub u32);
-        impl Ifcr {
-            #[doc = "Channel 1 Global interrupt clear"]
-            pub fn cgif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+        pub struct SrUsart(pub u32);
+        impl SrUsart {
+            #[doc = "Parity error"]
+            pub const fn pe(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Channel 1 Global interrupt clear"]
-            pub fn set_cgif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Parity error"]
+            pub fn set_pe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Channel 1 Transfer Complete clear"]
-            pub fn ctcif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 1usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Framing error"]
+            pub const fn fe(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Channel 1 Transfer Complete clear"]
-            pub fn set_ctcif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 1usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Framing error"]
+            pub fn set_fe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Channel 1 Half Transfer clear"]
-            pub fn chtif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 2usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Noise error flag"]
+            pub const fn ne(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
                 val != 0
             }
-            #[doc = "Channel 1 Half Transfer clear"]
-            pub fn set_chtif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 2usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Noise error flag"]
+            pub fn set_ne(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "Channel 1 Transfer Error clear"]
-            pub fn cteif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 3usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Overrun error"]
+            pub const fn ore(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
                 val != 0
             }
-            #[doc = "Channel 1 Transfer Error clear"]
-            pub fn set_cteif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 3usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Overrun error"]
+            pub fn set_ore(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
             }
-        }
-        impl Default for Ifcr {
-            fn default() -> Ifcr {
-                Ifcr(0)
+            #[doc = "IDLE line detected"]
+            pub const fn idle(&self) -> bool {
+                let val = (self.0 >> 4usize) & 0x01;
+                val != 0
             }
-        }
-        #[doc = "DMA interrupt status register (DMA_ISR)"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Isr(pub u32);
-        impl Isr {
-            #[doc = "Channel 1 Global interrupt flag"]
-            pub fn gif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "IDLE line detected"]
+            pub fn set_idle(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+            }
+            #[doc = "Read data register not empty"]
+            pub const fn rxne(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "Channel 1 Global interrupt flag"]
-            pub fn set_gif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Read data register not empty"]
+            pub fn set_rxne(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Channel 1 Transfer Complete flag"]
-            pub fn tcif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 1usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Transmission complete"]
+            pub const fn tc(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Channel 1 Transfer Complete flag"]
-            pub fn set_tcif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 1usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Transmission complete"]
+            pub fn set_tc(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Channel 1 Half Transfer Complete flag"]
-            pub fn htif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 2usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Transmit data register empty"]
+            pub const fn txe(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "Channel 1 Half Transfer Complete flag"]
-            pub fn set_htif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 2usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Transmit data register empty"]
+            pub fn set_txe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "Channel 1 Transfer Error flag"]
-            pub fn teif(&self, n: usize) -> bool {
-                assert!(n < 7usize);
-                let offs = 3usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "LIN break detection flag"]
+            pub const fn lbd(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
                 val != 0
             }
-            #[doc = "Channel 1 Transfer Error flag"]
-            pub fn set_teif(&mut self, n: usize, val: bool) {
-                assert!(n < 7usize);
-                let offs = 3usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "LIN break detection flag"]
+            pub fn set_lbd(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "CTS flag"]
+            pub const fn cts(&self) -> bool {
+                let val = (self.0 >> 9usize) & 0x01;
+                val != 0
+            }
+            #[doc = "CTS flag"]
+            pub fn set_cts(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
             }
         }
-        impl Default for Isr {
-            fn default() -> Isr {
-                Isr(0)
+        impl Default for SrUsart {
+            fn default() -> SrUsart {
+                SrUsart(0)
             }
         }
-        #[doc = "DMA channel configuration register (DMA_CCR)"]
+        #[doc = "Control register 3"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr(pub u32);
-        impl Cr {
-            #[doc = "Channel enable"]
-            pub const fn en(&self) -> bool {
+        pub struct Cr3Usart(pub u32);
+        impl Cr3Usart {
+            #[doc = "Error interrupt enable"]
+            pub const fn eie(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Channel enable"]
-            pub fn set_en(&mut self, val: bool) {
+            #[doc = "Error interrupt enable"]
+            pub fn set_eie(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Transfer complete interrupt enable"]
-            pub const fn tcie(&self) -> bool {
+            #[doc = "IrDA mode enable"]
+            pub const fn iren(&self) -> bool {
                 let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "Transfer complete interrupt enable"]
-            pub fn set_tcie(&mut self, val: bool) {
+            #[doc = "IrDA mode enable"]
+            pub fn set_iren(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Half Transfer interrupt enable"]
-            pub const fn htie(&self) -> bool {
+            #[doc = "IrDA low-power"]
+            pub const fn irlp(&self) -> super::vals::Irlp {
                 let val = (self.0 >> 2usize) & 0x01;
-                val != 0
+                super::vals::Irlp(val as u8)
             }
-            #[doc = "Half Transfer interrupt enable"]
-            pub fn set_htie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            #[doc = "IrDA low-power"]
+            pub fn set_irlp(&mut self, val: super::vals::Irlp) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
             }
-            #[doc = "Transfer error interrupt enable"]
-            pub const fn teie(&self) -> bool {
+            #[doc = "Half-duplex selection"]
+            pub const fn hdsel(&self) -> super::vals::Hdsel {
                 let val = (self.0 >> 3usize) & 0x01;
-                val != 0
+                super::vals::Hdsel(val as u8)
             }
-            #[doc = "Transfer error interrupt enable"]
-            pub fn set_teie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            #[doc = "Half-duplex selection"]
+            pub fn set_hdsel(&mut self, val: super::vals::Hdsel) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
             }
-            #[doc = "Data transfer direction"]
-            pub const fn dir(&self) -> super::vals::Dir {
+            #[doc = "Smartcard NACK enable"]
+            pub const fn nack(&self) -> bool {
                 let val = (self.0 >> 4usize) & 0x01;
-                super::vals::Dir(val as u8)
+                val != 0
             }
-            #[doc = "Data transfer direction"]
-            pub fn set_dir(&mut self, val: super::vals::Dir) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
+            #[doc = "Smartcard NACK enable"]
+            pub fn set_nack(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
             }
-            #[doc = "Circular mode"]
-            pub const fn circ(&self) -> super::vals::Circ {
+            #[doc = "Smartcard mode enable"]
+            pub const fn scen(&self) -> bool {
                 let val = (self.0 >> 5usize) & 0x01;
-                super::vals::Circ(val as u8)
+                val != 0
             }
-            #[doc = "Circular mode"]
-            pub fn set_circ(&mut self, val: super::vals::Circ) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
+            #[doc = "Smartcard mode enable"]
+            pub fn set_scen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Peripheral increment mode"]
-            pub const fn pinc(&self) -> super::vals::Inc {
+            #[doc = "DMA enable receiver"]
+            pub const fn dmar(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
-                super::vals::Inc(val as u8)
+                val != 0
             }
-            #[doc = "Peripheral increment mode"]
-            pub fn set_pinc(&mut self, val: super::vals::Inc) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
+            #[doc = "DMA enable receiver"]
+            pub fn set_dmar(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Memory increment mode"]
-            pub const fn minc(&self) -> super::vals::Inc {
+            #[doc = "DMA enable transmitter"]
+            pub const fn dmat(&self) -> bool {
                 let val = (self.0 >> 7usize) & 0x01;
-                super::vals::Inc(val as u8)
+                val != 0
             }
-            #[doc = "Memory increment mode"]
-            pub fn set_minc(&mut self, val: super::vals::Inc) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
+            #[doc = "DMA enable transmitter"]
+            pub fn set_dmat(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "Peripheral size"]
-            pub const fn psize(&self) -> super::vals::Size {
-                let val = (self.0 >> 8usize) & 0x03;
-                super::vals::Size(val as u8)
+            #[doc = "RTS enable"]
+            pub const fn rtse(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
             }
-            #[doc = "Peripheral size"]
-            pub fn set_psize(&mut self, val: super::vals::Size) {
-                self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
+            #[doc = "RTS enable"]
+            pub fn set_rtse(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
             }
-            #[doc = "Memory size"]
-            pub const fn msize(&self) -> super::vals::Size {
-                let val = (self.0 >> 10usize) & 0x03;
-                super::vals::Size(val as u8)
+            #[doc = "CTS enable"]
+            pub const fn ctse(&self) -> bool {
+                let val = (self.0 >> 9usize) & 0x01;
+                val != 0
             }
-            #[doc = "Memory size"]
-            pub fn set_msize(&mut self, val: super::vals::Size) {
-                self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize);
+            #[doc = "CTS enable"]
+            pub fn set_ctse(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
             }
-            #[doc = "Channel Priority level"]
-            pub const fn pl(&self) -> super::vals::Pl {
-                let val = (self.0 >> 12usize) & 0x03;
-                super::vals::Pl(val as u8)
+            #[doc = "CTS interrupt enable"]
+            pub const fn ctsie(&self) -> bool {
+                let val = (self.0 >> 10usize) & 0x01;
+                val != 0
             }
-            #[doc = "Channel Priority level"]
-            pub fn set_pl(&mut self, val: super::vals::Pl) {
-                self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
+            #[doc = "CTS interrupt enable"]
+            pub fn set_ctsie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
             }
-            #[doc = "Memory to memory mode"]
-            pub const fn mem2mem(&self) -> super::vals::Memmem {
-                let val = (self.0 >> 14usize) & 0x01;
-                super::vals::Memmem(val as u8)
+        }
+        impl Default for Cr3Usart {
+            fn default() -> Cr3Usart {
+                Cr3Usart(0)
             }
-            #[doc = "Memory to memory mode"]
-            pub fn set_mem2mem(&mut self, val: super::vals::Memmem) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
+        }
+        #[doc = "Data register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Dr(pub u32);
+        impl Dr {
+            #[doc = "Data value"]
+            pub const fn dr(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0x01ff;
+                val as u16
+            }
+            #[doc = "Data value"]
+            pub fn set_dr(&mut self, val: u16) {
+                self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
             }
         }
-        impl Default for Cr {
-            fn default() -> Cr {
-                Cr(0)
+        impl Default for Dr {
+            fn default() -> Dr {
+                Dr(0)
             }
         }
     }
 }
-pub mod timer_v1 {
+pub mod syscfg_f4 {
     use crate::generic::*;
-    #[doc = "Advanced-timers"]
+    #[doc = "System configuration controller"]
     #[derive(Copy, Clone)]
-    pub struct TimAdv(pub *mut u8);
-    unsafe impl Send for TimAdv {}
-    unsafe impl Sync for TimAdv {}
-    impl TimAdv {
-        #[doc = "control register 1"]
-        pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
+    pub struct Syscfg(pub *mut u8);
+    unsafe impl Send for Syscfg {}
+    unsafe impl Sync for Syscfg {}
+    impl Syscfg {
+        #[doc = "memory remap register"]
+        pub fn memrm(self) -> Reg<regs::Memrm, RW> {
             unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
-        #[doc = "control register 2"]
-        pub fn cr2(self) -> Reg<regs::Cr2Adv, RW> {
+        #[doc = "peripheral mode configuration register"]
+        pub fn pmc(self) -> Reg<regs::Pmc, RW> {
             unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-        #[doc = "slave mode control register"]
-        pub fn smcr(self) -> Reg<regs::Smcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
-        }
-        #[doc = "DMA/Interrupt enable register"]
-        pub fn dier(self) -> Reg<regs::DierAdv, RW> {
-            unsafe { Reg::from_ptr(self.0.add(12usize)) }
-        }
-        #[doc = "status register"]
-        pub fn sr(self) -> Reg<regs::SrAdv, RW> {
-            unsafe { Reg::from_ptr(self.0.add(16usize)) }
-        }
-        #[doc = "event generation register"]
-        pub fn egr(self) -> Reg<regs::EgrAdv, W> {
-            unsafe { Reg::from_ptr(self.0.add(20usize)) }
-        }
-        #[doc = "capture/compare mode register 1 (input mode)"]
-        pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
-        }
-        #[doc = "capture/compare mode register 1 (output mode)"]
-        pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
-            assert!(n < 2usize);
-            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
+        #[doc = "external interrupt configuration register"]
+        pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
+            assert!(n < 4usize);
+            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
         }
-        #[doc = "capture/compare enable register"]
-        pub fn ccer(self) -> Reg<regs::CcerAdv, RW> {
+        #[doc = "Compensation cell control register"]
+        pub fn cmpcr(self) -> Reg<regs::Cmpcr, R> {
             unsafe { Reg::from_ptr(self.0.add(32usize)) }
         }
-        #[doc = "counter"]
-        pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
-            unsafe { Reg::from_ptr(self.0.add(36usize)) }
+    }
+    pub mod regs {
+        use crate::generic::*;
+        #[doc = "external interrupt configuration register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Exticr(pub u32);
+        impl Exticr {
+            #[doc = "EXTI x configuration"]
+            pub fn exti(&self, n: usize) -> u8 {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x0f;
+                val as u8
+            }
+            #[doc = "EXTI x configuration"]
+            pub fn set_exti(&mut self, n: usize, val: u8) {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
+            }
         }
-        #[doc = "prescaler"]
-        pub fn psc(self) -> Reg<regs::Psc, RW> {
-            unsafe { Reg::from_ptr(self.0.add(40usize)) }
+        impl Default for Exticr {
+            fn default() -> Exticr {
+                Exticr(0)
+            }
         }
-        #[doc = "auto-reload register"]
-        pub fn arr(self) -> Reg<regs::Arr16, RW> {
-            unsafe { Reg::from_ptr(self.0.add(44usize)) }
+        #[doc = "peripheral mode configuration register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Pmc(pub u32);
+        impl Pmc {
+            #[doc = "ADC1DC2"]
+            pub const fn adc1dc2(&self) -> bool {
+                let val = (self.0 >> 16usize) & 0x01;
+                val != 0
+            }
+            #[doc = "ADC1DC2"]
+            pub fn set_adc1dc2(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            }
+            #[doc = "ADC2DC2"]
+            pub const fn adc2dc2(&self) -> bool {
+                let val = (self.0 >> 17usize) & 0x01;
+                val != 0
+            }
+            #[doc = "ADC2DC2"]
+            pub fn set_adc2dc2(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+            }
+            #[doc = "ADC3DC2"]
+            pub const fn adc3dc2(&self) -> bool {
+                let val = (self.0 >> 18usize) & 0x01;
+                val != 0
+            }
+            #[doc = "ADC3DC2"]
+            pub fn set_adc3dc2(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+            }
+            #[doc = "Ethernet PHY interface selection"]
+            pub const fn mii_rmii_sel(&self) -> bool {
+                let val = (self.0 >> 23usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Ethernet PHY interface selection"]
+            pub fn set_mii_rmii_sel(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
+            }
         }
-        #[doc = "repetition counter register"]
-        pub fn rcr(self) -> Reg<regs::Rcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(48usize)) }
+        impl Default for Pmc {
+            fn default() -> Pmc {
+                Pmc(0)
+            }
         }
-        #[doc = "capture/compare register"]
-        pub fn ccr(self, n: usize) -> Reg<regs::Ccr16, RW> {
-            assert!(n < 4usize);
-            unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
+        #[doc = "Compensation cell control register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cmpcr(pub u32);
+        impl Cmpcr {
+            #[doc = "Compensation cell power-down"]
+            pub const fn cmp_pd(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Compensation cell power-down"]
+            pub fn set_cmp_pd(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "READY"]
+            pub const fn ready(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "READY"]
+            pub fn set_ready(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
         }
-        #[doc = "break and dead-time register"]
-        pub fn bdtr(self) -> Reg<regs::Bdtr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(68usize)) }
+        impl Default for Cmpcr {
+            fn default() -> Cmpcr {
+                Cmpcr(0)
+            }
         }
-        #[doc = "DMA control register"]
-        pub fn dcr(self) -> Reg<regs::Dcr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(72usize)) }
+        #[doc = "memory remap register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Memrm(pub u32);
+        impl Memrm {
+            #[doc = "Memory mapping selection"]
+            pub const fn mem_mode(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x07;
+                val as u8
+            }
+            #[doc = "Memory mapping selection"]
+            pub fn set_mem_mode(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
+            }
+            #[doc = "Flash bank mode selection"]
+            pub const fn fb_mode(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Flash bank mode selection"]
+            pub fn set_fb_mode(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "FMC memory mapping swap"]
+            pub const fn swp_fmc(&self) -> u8 {
+                let val = (self.0 >> 10usize) & 0x03;
+                val as u8
+            }
+            #[doc = "FMC memory mapping swap"]
+            pub fn set_swp_fmc(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
+            }
         }
-        #[doc = "DMA address for full transfer"]
-        pub fn dmar(self) -> Reg<regs::Dmar, RW> {
-            unsafe { Reg::from_ptr(self.0.add(76usize)) }
+        impl Default for Memrm {
+            fn default() -> Memrm {
+                Memrm(0)
+            }
         }
     }
+}
+pub mod timer_v1 {
+    use crate::generic::*;
     #[doc = "Basic timer"]
     #[derive(Copy, Clone)]
     pub struct TimBasic(pub *mut u8);
@@ -2573,6 +2356,84 @@ pub mod timer_v1 {
             unsafe { Reg::from_ptr(self.0.add(76usize)) }
         }
     }
+    #[doc = "Advanced-timers"]
+    #[derive(Copy, Clone)]
+    pub struct TimAdv(pub *mut u8);
+    unsafe impl Send for TimAdv {}
+    unsafe impl Sync for TimAdv {}
+    impl TimAdv {
+        #[doc = "control register 1"]
+        pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "control register 2"]
+        pub fn cr2(self) -> Reg<regs::Cr2Adv, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "slave mode control register"]
+        pub fn smcr(self) -> Reg<regs::Smcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
+        }
+        #[doc = "DMA/Interrupt enable register"]
+        pub fn dier(self) -> Reg<regs::DierAdv, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
+        }
+        #[doc = "status register"]
+        pub fn sr(self) -> Reg<regs::SrAdv, RW> {
+            unsafe { Reg::from_ptr(self.0.add(16usize)) }
+        }
+        #[doc = "event generation register"]
+        pub fn egr(self) -> Reg<regs::EgrAdv, W> {
+            unsafe { Reg::from_ptr(self.0.add(20usize)) }
+        }
+        #[doc = "capture/compare mode register 1 (input mode)"]
+        pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
+        }
+        #[doc = "capture/compare mode register 1 (output mode)"]
+        pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
+        }
+        #[doc = "capture/compare enable register"]
+        pub fn ccer(self) -> Reg<regs::CcerAdv, RW> {
+            unsafe { Reg::from_ptr(self.0.add(32usize)) }
+        }
+        #[doc = "counter"]
+        pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
+            unsafe { Reg::from_ptr(self.0.add(36usize)) }
+        }
+        #[doc = "prescaler"]
+        pub fn psc(self) -> Reg<regs::Psc, RW> {
+            unsafe { Reg::from_ptr(self.0.add(40usize)) }
+        }
+        #[doc = "auto-reload register"]
+        pub fn arr(self) -> Reg<regs::Arr16, RW> {
+            unsafe { Reg::from_ptr(self.0.add(44usize)) }
+        }
+        #[doc = "repetition counter register"]
+        pub fn rcr(self) -> Reg<regs::Rcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(48usize)) }
+        }
+        #[doc = "capture/compare register"]
+        pub fn ccr(self, n: usize) -> Reg<regs::Ccr16, RW> {
+            assert!(n < 4usize);
+            unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
+        }
+        #[doc = "break and dead-time register"]
+        pub fn bdtr(self) -> Reg<regs::Bdtr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(68usize)) }
+        }
+        #[doc = "DMA control register"]
+        pub fn dcr(self) -> Reg<regs::Dcr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(72usize)) }
+        }
+        #[doc = "DMA address for full transfer"]
+        pub fn dmar(self) -> Reg<regs::Dmar, RW> {
+            unsafe { Reg::from_ptr(self.0.add(76usize)) }
+        }
+    }
     #[doc = "General purpose 16-bit timer"]
     #[derive(Copy, Clone)]
     pub struct TimGp16(pub *mut u8);
@@ -2643,26 +2504,563 @@ pub mod timer_v1 {
             unsafe { Reg::from_ptr(self.0.add(76usize)) }
         }
     }
+    pub mod vals {
+        use crate::generic::*;
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct CcmrOutputCcs(pub u8);
+        impl CcmrOutputCcs {
+            #[doc = "CCx channel is configured as output"]
+            pub const OUTPUT: Self = Self(0);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Arpe(pub u8);
+        impl Arpe {
+            #[doc = "TIMx_APRR register is not buffered"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "TIMx_APRR register is buffered"]
+            pub const ENABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Etf(pub u8);
+        impl Etf {
+            #[doc = "No filter, sampling is done at fDTS"]
+            pub const NOFILTER: Self = Self(0);
+            #[doc = "fSAMPLING=fCK_INT, N=2"]
+            pub const FCK_INT_N2: Self = Self(0x01);
+            #[doc = "fSAMPLING=fCK_INT, N=4"]
+            pub const FCK_INT_N4: Self = Self(0x02);
+            #[doc = "fSAMPLING=fCK_INT, N=8"]
+            pub const FCK_INT_N8: Self = Self(0x03);
+            #[doc = "fSAMPLING=fDTS/2, N=6"]
+            pub const FDTS_DIV2_N6: Self = Self(0x04);
+            #[doc = "fSAMPLING=fDTS/2, N=8"]
+            pub const FDTS_DIV2_N8: Self = Self(0x05);
+            #[doc = "fSAMPLING=fDTS/4, N=6"]
+            pub const FDTS_DIV4_N6: Self = Self(0x06);
+            #[doc = "fSAMPLING=fDTS/4, N=8"]
+            pub const FDTS_DIV4_N8: Self = Self(0x07);
+            #[doc = "fSAMPLING=fDTS/8, N=6"]
+            pub const FDTS_DIV8_N6: Self = Self(0x08);
+            #[doc = "fSAMPLING=fDTS/8, N=8"]
+            pub const FDTS_DIV8_N8: Self = Self(0x09);
+            #[doc = "fSAMPLING=fDTS/16, N=5"]
+            pub const FDTS_DIV16_N5: Self = Self(0x0a);
+            #[doc = "fSAMPLING=fDTS/16, N=6"]
+            pub const FDTS_DIV16_N6: Self = Self(0x0b);
+            #[doc = "fSAMPLING=fDTS/16, N=8"]
+            pub const FDTS_DIV16_N8: Self = Self(0x0c);
+            #[doc = "fSAMPLING=fDTS/32, N=5"]
+            pub const FDTS_DIV32_N5: Self = Self(0x0d);
+            #[doc = "fSAMPLING=fDTS/32, N=6"]
+            pub const FDTS_DIV32_N6: Self = Self(0x0e);
+            #[doc = "fSAMPLING=fDTS/32, N=8"]
+            pub const FDTS_DIV32_N8: Self = Self(0x0f);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Urs(pub u8);
+        impl Urs {
+            #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
+            pub const ANYEVENT: Self = Self(0);
+            #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
+            pub const COUNTERONLY: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ocm(pub u8);
+        impl Ocm {
+            #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
+            pub const FROZEN: Self = Self(0);
+            #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
+            pub const ACTIVEONMATCH: Self = Self(0x01);
+            #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
+            pub const INACTIVEONMATCH: Self = Self(0x02);
+            #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
+            pub const TOGGLE: Self = Self(0x03);
+            #[doc = "OCyREF is forced low"]
+            pub const FORCEINACTIVE: Self = Self(0x04);
+            #[doc = "OCyREF is forced high"]
+            pub const FORCEACTIVE: Self = Self(0x05);
+            #[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
+            pub const PWMMODE1: Self = Self(0x06);
+            #[doc = "Inversely to PwmMode1"]
+            pub const PWMMODE2: Self = Self(0x07);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Etp(pub u8);
+        impl Etp {
+            #[doc = "ETR is noninverted, active at high level or rising edge"]
+            pub const NOTINVERTED: Self = Self(0);
+            #[doc = "ETR is inverted, active at low level or falling edge"]
+            pub const INVERTED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ossr(pub u8);
+        impl Ossr {
+            #[doc = "When inactive, OC/OCN outputs are disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"]
+            pub const IDLELEVEL: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ccds(pub u8);
+        impl Ccds {
+            #[doc = "CCx DMA request sent when CCx event occurs"]
+            pub const ONCOMPARE: Self = Self(0);
+            #[doc = "CCx DMA request sent when update event occurs"]
+            pub const ONUPDATE: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Sms(pub u8);
+        impl Sms {
+            #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."]
+            pub const ENCODER_MODE_1: Self = Self(0x01);
+            #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."]
+            pub const ENCODER_MODE_2: Self = Self(0x02);
+            #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."]
+            pub const ENCODER_MODE_3: Self = Self(0x03);
+            #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."]
+            pub const RESET_MODE: Self = Self(0x04);
+            #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."]
+            pub const GATED_MODE: Self = Self(0x05);
+            #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."]
+            pub const TRIGGER_MODE: Self = Self(0x06);
+            #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."]
+            pub const EXT_CLOCK_MODE: Self = Self(0x07);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ts(pub u8);
+        impl Ts {
+            #[doc = "Internal Trigger 0 (ITR0)"]
+            pub const ITR0: Self = Self(0);
+            #[doc = "Internal Trigger 1 (ITR1)"]
+            pub const ITR1: Self = Self(0x01);
+            #[doc = "Internal Trigger 2 (ITR2)"]
+            pub const ITR2: Self = Self(0x02);
+            #[doc = "TI1 Edge Detector (TI1F_ED)"]
+            pub const TI1F_ED: Self = Self(0x04);
+            #[doc = "Filtered Timer Input 1 (TI1FP1)"]
+            pub const TI1FP1: Self = Self(0x05);
+            #[doc = "Filtered Timer Input 2 (TI2FP2)"]
+            pub const TI2FP2: Self = Self(0x06);
+            #[doc = "External Trigger input (ETRF)"]
+            pub const ETRF: Self = Self(0x07);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ece(pub u8);
+        impl Ece {
+            #[doc = "External clock mode 2 disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
+            pub const ENABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Tis(pub u8);
+        impl Tis {
+            #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
+            pub const NORMAL: Self = Self(0);
+            #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
+            pub const XOR: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Opm(pub u8);
+        impl Opm {
+            #[doc = "Counter is not stopped at update event"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
+            pub const ENABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ossi(pub u8);
+        impl Ossi {
+            #[doc = "When inactive, OC/OCN outputs are disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "When inactive, OC/OCN outputs are forced to idle level"]
+            pub const IDLELEVEL: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ckd(pub u8);
+        impl Ckd {
+            #[doc = "t_DTS = t_CK_INT"]
+            pub const DIV1: Self = Self(0);
+            #[doc = "t_DTS = 2 × t_CK_INT"]
+            pub const DIV2: Self = Self(0x01);
+            #[doc = "t_DTS = 4 × t_CK_INT"]
+            pub const DIV4: Self = Self(0x02);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ocpe(pub u8);
+        impl Ocpe {
+            #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"]
+            pub const ENABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Cms(pub u8);
+        impl Cms {
+            #[doc = "The counter counts up or down depending on the direction bit"]
+            pub const EDGEALIGNED: Self = Self(0);
+            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
+            pub const CENTERALIGNED1: Self = Self(0x01);
+            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
+            pub const CENTERALIGNED2: Self = Self(0x02);
+            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
+            pub const CENTERALIGNED3: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Dir(pub u8);
+        impl Dir {
+            #[doc = "Counter used as upcounter"]
+            pub const UP: Self = Self(0);
+            #[doc = "Counter used as downcounter"]
+            pub const DOWN: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Mms(pub u8);
+        impl Mms {
+            #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
+            pub const RESET: Self = Self(0);
+            #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
+            pub const ENABLE: Self = Self(0x01);
+            #[doc = "The update event is selected as trigger output"]
+            pub const UPDATE: Self = Self(0x02);
+            #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
+            pub const COMPAREPULSE: Self = Self(0x03);
+            #[doc = "OC1REF signal is used as trigger output"]
+            pub const COMPAREOC1: Self = Self(0x04);
+            #[doc = "OC2REF signal is used as trigger output"]
+            pub const COMPAREOC2: Self = Self(0x05);
+            #[doc = "OC3REF signal is used as trigger output"]
+            pub const COMPAREOC3: Self = Self(0x06);
+            #[doc = "OC4REF signal is used as trigger output"]
+            pub const COMPAREOC4: Self = Self(0x07);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Msm(pub u8);
+        impl Msm {
+            #[doc = "No action"]
+            pub const NOSYNC: Self = Self(0);
+            #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
+            pub const SYNC: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Etps(pub u8);
+        impl Etps {
+            #[doc = "Prescaler OFF"]
+            pub const DIV1: Self = Self(0);
+            #[doc = "ETRP frequency divided by 2"]
+            pub const DIV2: Self = Self(0x01);
+            #[doc = "ETRP frequency divided by 4"]
+            pub const DIV4: Self = Self(0x02);
+            #[doc = "ETRP frequency divided by 8"]
+            pub const DIV8: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct CcmrInputCcs(pub u8);
+        impl CcmrInputCcs {
+            #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"]
+            pub const TI4: Self = Self(0x01);
+            #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"]
+            pub const TI3: Self = Self(0x02);
+            #[doc = "CCx channel is configured as input, ICx is mapped on TRC"]
+            pub const TRC: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Icf(pub u8);
+        impl Icf {
+            #[doc = "No filter, sampling is done at fDTS"]
+            pub const NOFILTER: Self = Self(0);
+            #[doc = "fSAMPLING=fCK_INT, N=2"]
+            pub const FCK_INT_N2: Self = Self(0x01);
+            #[doc = "fSAMPLING=fCK_INT, N=4"]
+            pub const FCK_INT_N4: Self = Self(0x02);
+            #[doc = "fSAMPLING=fCK_INT, N=8"]
+            pub const FCK_INT_N8: Self = Self(0x03);
+            #[doc = "fSAMPLING=fDTS/2, N=6"]
+            pub const FDTS_DIV2_N6: Self = Self(0x04);
+            #[doc = "fSAMPLING=fDTS/2, N=8"]
+            pub const FDTS_DIV2_N8: Self = Self(0x05);
+            #[doc = "fSAMPLING=fDTS/4, N=6"]
+            pub const FDTS_DIV4_N6: Self = Self(0x06);
+            #[doc = "fSAMPLING=fDTS/4, N=8"]
+            pub const FDTS_DIV4_N8: Self = Self(0x07);
+            #[doc = "fSAMPLING=fDTS/8, N=6"]
+            pub const FDTS_DIV8_N6: Self = Self(0x08);
+            #[doc = "fSAMPLING=fDTS/8, N=8"]
+            pub const FDTS_DIV8_N8: Self = Self(0x09);
+            #[doc = "fSAMPLING=fDTS/16, N=5"]
+            pub const FDTS_DIV16_N5: Self = Self(0x0a);
+            #[doc = "fSAMPLING=fDTS/16, N=6"]
+            pub const FDTS_DIV16_N6: Self = Self(0x0b);
+            #[doc = "fSAMPLING=fDTS/16, N=8"]
+            pub const FDTS_DIV16_N8: Self = Self(0x0c);
+            #[doc = "fSAMPLING=fDTS/32, N=5"]
+            pub const FDTS_DIV32_N5: Self = Self(0x0d);
+            #[doc = "fSAMPLING=fDTS/32, N=6"]
+            pub const FDTS_DIV32_N6: Self = Self(0x0e);
+            #[doc = "fSAMPLING=fDTS/32, N=8"]
+            pub const FDTS_DIV32_N8: Self = Self(0x0f);
+        }
+    }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "repetition counter register"]
+        #[doc = "DMA control register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Rcr(pub u32);
-        impl Rcr {
-            #[doc = "Repetition counter value"]
-            pub const fn rep(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0xff;
+        pub struct Dcr(pub u32);
+        impl Dcr {
+            #[doc = "DMA base address"]
+            pub const fn dba(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0x1f;
                 val as u8
             }
-            #[doc = "Repetition counter value"]
-            pub fn set_rep(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+            #[doc = "DMA base address"]
+            pub fn set_dba(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
+            }
+            #[doc = "DMA burst length"]
+            pub const fn dbl(&self) -> u8 {
+                let val = (self.0 >> 8usize) & 0x1f;
+                val as u8
+            }
+            #[doc = "DMA burst length"]
+            pub fn set_dbl(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
             }
         }
-        impl Default for Rcr {
-            fn default() -> Rcr {
-                Rcr(0)
+        impl Default for Dcr {
+            fn default() -> Dcr {
+                Dcr(0)
+            }
+        }
+        #[doc = "counter"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cnt16(pub u32);
+        impl Cnt16 {
+            #[doc = "counter value"]
+            pub const fn cnt(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "counter value"]
+            pub fn set_cnt(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Cnt16 {
+            fn default() -> Cnt16 {
+                Cnt16(0)
+            }
+        }
+        #[doc = "capture/compare enable register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct CcerAdv(pub u32);
+        impl CcerAdv {
+            #[doc = "Capture/Compare 1 output enable"]
+            pub fn cce(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 output enable"]
+            pub fn set_cce(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn ccp(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn set_ccp(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Capture/Compare 1 complementary output enable"]
+            pub fn ccne(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 2usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 complementary output enable"]
+            pub fn set_ccne(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 2usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn ccnp(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 3usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn set_ccnp(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 3usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+        }
+        impl Default for CcerAdv {
+            fn default() -> CcerAdv {
+                CcerAdv(0)
+            }
+        }
+        #[doc = "auto-reload register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Arr16(pub u32);
+        impl Arr16 {
+            #[doc = "Auto-reload value"]
+            pub const fn arr(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "Auto-reload value"]
+            pub fn set_arr(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Arr16 {
+            fn default() -> Arr16 {
+                Arr16(0)
+            }
+        }
+        #[doc = "event generation register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct EgrBasic(pub u32);
+        impl EgrBasic {
+            #[doc = "Update generation"]
+            pub const fn ug(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update generation"]
+            pub fn set_ug(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+        }
+        impl Default for EgrBasic {
+            fn default() -> EgrBasic {
+                EgrBasic(0)
+            }
+        }
+        #[doc = "control register 1"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr1Gp(pub u32);
+        impl Cr1Gp {
+            #[doc = "Counter enable"]
+            pub const fn cen(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Counter enable"]
+            pub fn set_cen(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Update disable"]
+            pub const fn udis(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update disable"]
+            pub fn set_udis(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            }
+            #[doc = "Update request source"]
+            pub const fn urs(&self) -> super::vals::Urs {
+                let val = (self.0 >> 2usize) & 0x01;
+                super::vals::Urs(val as u8)
+            }
+            #[doc = "Update request source"]
+            pub fn set_urs(&mut self, val: super::vals::Urs) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
+            }
+            #[doc = "One-pulse mode"]
+            pub const fn opm(&self) -> super::vals::Opm {
+                let val = (self.0 >> 3usize) & 0x01;
+                super::vals::Opm(val as u8)
+            }
+            #[doc = "One-pulse mode"]
+            pub fn set_opm(&mut self, val: super::vals::Opm) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
+            }
+            #[doc = "Direction"]
+            pub const fn dir(&self) -> super::vals::Dir {
+                let val = (self.0 >> 4usize) & 0x01;
+                super::vals::Dir(val as u8)
+            }
+            #[doc = "Direction"]
+            pub fn set_dir(&mut self, val: super::vals::Dir) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
+            }
+            #[doc = "Center-aligned mode selection"]
+            pub const fn cms(&self) -> super::vals::Cms {
+                let val = (self.0 >> 5usize) & 0x03;
+                super::vals::Cms(val as u8)
+            }
+            #[doc = "Center-aligned mode selection"]
+            pub fn set_cms(&mut self, val: super::vals::Cms) {
+                self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize);
+            }
+            #[doc = "Auto-reload preload enable"]
+            pub const fn arpe(&self) -> super::vals::Arpe {
+                let val = (self.0 >> 7usize) & 0x01;
+                super::vals::Arpe(val as u8)
+            }
+            #[doc = "Auto-reload preload enable"]
+            pub fn set_arpe(&mut self, val: super::vals::Arpe) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
+            }
+            #[doc = "Clock division"]
+            pub const fn ckd(&self) -> super::vals::Ckd {
+                let val = (self.0 >> 8usize) & 0x03;
+                super::vals::Ckd(val as u8)
+            }
+            #[doc = "Clock division"]
+            pub fn set_ckd(&mut self, val: super::vals::Ckd) {
+                self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
+            }
+        }
+        impl Default for Cr1Gp {
+            fn default() -> Cr1Gp {
+                Cr1Gp(0)
             }
         }
         #[doc = "counter"]
@@ -2686,148 +3084,104 @@ pub mod timer_v1 {
                 Cnt32(0)
             }
         }
-        #[doc = "status register"]
+        #[doc = "event generation register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct SrGp(pub u32);
-        impl SrGp {
-            #[doc = "Update interrupt flag"]
-            pub const fn uif(&self) -> bool {
+        pub struct EgrGp(pub u32);
+        impl EgrGp {
+            #[doc = "Update generation"]
+            pub const fn ug(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Update interrupt flag"]
-            pub fn set_uif(&mut self, val: bool) {
+            #[doc = "Update generation"]
+            pub fn set_ug(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Capture/compare 1 interrupt flag"]
-            pub fn ccif(&self, n: usize) -> bool {
+            #[doc = "Capture/compare 1 generation"]
+            pub fn ccg(&self, n: usize) -> bool {
                 assert!(n < 4usize);
                 let offs = 1usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Capture/compare 1 interrupt flag"]
-            pub fn set_ccif(&mut self, n: usize, val: bool) {
+            #[doc = "Capture/compare 1 generation"]
+            pub fn set_ccg(&mut self, n: usize, val: bool) {
                 assert!(n < 4usize);
                 let offs = 1usize + n * 1usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "COM interrupt flag"]
-            pub const fn comif(&self) -> bool {
+            #[doc = "Capture/Compare control update generation"]
+            pub const fn comg(&self) -> bool {
                 let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "COM interrupt flag"]
-            pub fn set_comif(&mut self, val: bool) {
+            #[doc = "Capture/Compare control update generation"]
+            pub fn set_comg(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Trigger interrupt flag"]
-            pub const fn tif(&self) -> bool {
+            #[doc = "Trigger generation"]
+            pub const fn tg(&self) -> bool {
                 let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Trigger interrupt flag"]
-            pub fn set_tif(&mut self, val: bool) {
+            #[doc = "Trigger generation"]
+            pub fn set_tg(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-            #[doc = "Break interrupt flag"]
-            pub const fn bif(&self) -> bool {
+            #[doc = "Break generation"]
+            pub const fn bg(&self) -> bool {
                 let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "Break interrupt flag"]
-            pub fn set_bif(&mut self, val: bool) {
+            #[doc = "Break generation"]
+            pub fn set_bg(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "Capture/Compare 1 overcapture flag"]
-            pub fn ccof(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 overcapture flag"]
-            pub fn set_ccof(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
         }
-        impl Default for SrGp {
-            fn default() -> SrGp {
-                SrGp(0)
+        impl Default for EgrGp {
+            fn default() -> EgrGp {
+                EgrGp(0)
             }
         }
-        #[doc = "capture/compare mode register 1 (input mode)"]
+        #[doc = "status register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct CcmrInput(pub u32);
-        impl CcmrInput {
-            #[doc = "Capture/Compare 1 selection"]
-            pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs {
-                assert!(n < 2usize);
-                let offs = 0usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::CcmrInputCcs(val as u8)
-            }
-            #[doc = "Capture/Compare 1 selection"]
-            pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) {
-                assert!(n < 2usize);
-                let offs = 0usize + n * 8usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
-            }
-            #[doc = "Input capture 1 prescaler"]
-            pub fn icpsc(&self, n: usize) -> u8 {
-                assert!(n < 2usize);
-                let offs = 2usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x03;
-                val as u8
-            }
-            #[doc = "Input capture 1 prescaler"]
-            pub fn set_icpsc(&mut self, n: usize, val: u8) {
-                assert!(n < 2usize);
-                let offs = 2usize + n * 8usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
-            }
-            #[doc = "Input capture 1 filter"]
-            pub fn icf(&self, n: usize) -> super::vals::Icf {
-                assert!(n < 2usize);
-                let offs = 4usize + n * 8usize;
-                let val = (self.0 >> offs) & 0x0f;
-                super::vals::Icf(val as u8)
+        pub struct SrBasic(pub u32);
+        impl SrBasic {
+            #[doc = "Update interrupt flag"]
+            pub const fn uif(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "Input capture 1 filter"]
-            pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) {
-                assert!(n < 2usize);
-                let offs = 4usize + n * 8usize;
-                self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
+            #[doc = "Update interrupt flag"]
+            pub fn set_uif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
         }
-        impl Default for CcmrInput {
-            fn default() -> CcmrInput {
-                CcmrInput(0)
+        impl Default for SrBasic {
+            fn default() -> SrBasic {
+                SrBasic(0)
             }
         }
-        #[doc = "capture/compare register 1"]
+        #[doc = "repetition counter register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ccr32(pub u32);
-        impl Ccr32 {
-            #[doc = "Capture/Compare 1 value"]
-            pub const fn ccr(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
+        pub struct Rcr(pub u32);
+        impl Rcr {
+            #[doc = "Repetition counter value"]
+            pub const fn rep(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0xff;
+                val as u8
             }
-            #[doc = "Capture/Compare 1 value"]
-            pub fn set_ccr(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
+            #[doc = "Repetition counter value"]
+            pub fn set_rep(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
             }
         }
-        impl Default for Ccr32 {
-            fn default() -> Ccr32 {
-                Ccr32(0)
+        impl Default for Rcr {
+            fn default() -> Rcr {
+                Rcr(0)
             }
         }
         #[doc = "control register 2"]
@@ -2926,6 +3280,324 @@ pub mod timer_v1 {
                 Cr2Adv(0)
             }
         }
+        #[doc = "control register 2"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr2Gp(pub u32);
+        impl Cr2Gp {
+            #[doc = "Capture/compare DMA selection"]
+            pub const fn ccds(&self) -> super::vals::Ccds {
+                let val = (self.0 >> 3usize) & 0x01;
+                super::vals::Ccds(val as u8)
+            }
+            #[doc = "Capture/compare DMA selection"]
+            pub fn set_ccds(&mut self, val: super::vals::Ccds) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
+            }
+            #[doc = "Master mode selection"]
+            pub const fn mms(&self) -> super::vals::Mms {
+                let val = (self.0 >> 4usize) & 0x07;
+                super::vals::Mms(val as u8)
+            }
+            #[doc = "Master mode selection"]
+            pub fn set_mms(&mut self, val: super::vals::Mms) {
+                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
+            }
+            #[doc = "TI1 selection"]
+            pub const fn ti1s(&self) -> super::vals::Tis {
+                let val = (self.0 >> 7usize) & 0x01;
+                super::vals::Tis(val as u8)
+            }
+            #[doc = "TI1 selection"]
+            pub fn set_ti1s(&mut self, val: super::vals::Tis) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
+            }
+        }
+        impl Default for Cr2Gp {
+            fn default() -> Cr2Gp {
+                Cr2Gp(0)
+            }
+        }
+        #[doc = "auto-reload register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Arr32(pub u32);
+        impl Arr32 {
+            #[doc = "Auto-reload value"]
+            pub const fn arr(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
+            }
+            #[doc = "Auto-reload value"]
+            pub fn set_arr(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
+            }
+        }
+        impl Default for Arr32 {
+            fn default() -> Arr32 {
+                Arr32(0)
+            }
+        }
+        #[doc = "DMA/Interrupt enable register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct DierBasic(pub u32);
+        impl DierBasic {
+            #[doc = "Update interrupt enable"]
+            pub const fn uie(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update interrupt enable"]
+            pub fn set_uie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Update DMA request enable"]
+            pub const fn ude(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update DMA request enable"]
+            pub fn set_ude(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+        }
+        impl Default for DierBasic {
+            fn default() -> DierBasic {
+                DierBasic(0)
+            }
+        }
+        #[doc = "break and dead-time register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Bdtr(pub u32);
+        impl Bdtr {
+            #[doc = "Dead-time generator setup"]
+            pub const fn dtg(&self) -> u8 {
+                let val = (self.0 >> 0usize) & 0xff;
+                val as u8
+            }
+            #[doc = "Dead-time generator setup"]
+            pub fn set_dtg(&mut self, val: u8) {
+                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+            }
+            #[doc = "Lock configuration"]
+            pub const fn lock(&self) -> u8 {
+                let val = (self.0 >> 8usize) & 0x03;
+                val as u8
+            }
+            #[doc = "Lock configuration"]
+            pub fn set_lock(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
+            }
+            #[doc = "Off-state selection for Idle mode"]
+            pub const fn ossi(&self) -> super::vals::Ossi {
+                let val = (self.0 >> 10usize) & 0x01;
+                super::vals::Ossi(val as u8)
+            }
+            #[doc = "Off-state selection for Idle mode"]
+            pub fn set_ossi(&mut self, val: super::vals::Ossi) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
+            }
+            #[doc = "Off-state selection for Run mode"]
+            pub const fn ossr(&self) -> super::vals::Ossr {
+                let val = (self.0 >> 11usize) & 0x01;
+                super::vals::Ossr(val as u8)
+            }
+            #[doc = "Off-state selection for Run mode"]
+            pub fn set_ossr(&mut self, val: super::vals::Ossr) {
+                self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
+            }
+            #[doc = "Break enable"]
+            pub const fn bke(&self) -> bool {
+                let val = (self.0 >> 12usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Break enable"]
+            pub fn set_bke(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+            }
+            #[doc = "Break polarity"]
+            pub const fn bkp(&self) -> bool {
+                let val = (self.0 >> 13usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Break polarity"]
+            pub fn set_bkp(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+            }
+            #[doc = "Automatic output enable"]
+            pub const fn aoe(&self) -> bool {
+                let val = (self.0 >> 14usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Automatic output enable"]
+            pub fn set_aoe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            }
+            #[doc = "Main output enable"]
+            pub const fn moe(&self) -> bool {
+                let val = (self.0 >> 15usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Main output enable"]
+            pub fn set_moe(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
+            }
+        }
+        impl Default for Bdtr {
+            fn default() -> Bdtr {
+                Bdtr(0)
+            }
+        }
+        #[doc = "DMA/Interrupt enable register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct DierGp(pub u32);
+        impl DierGp {
+            #[doc = "Update interrupt enable"]
+            pub const fn uie(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update interrupt enable"]
+            pub fn set_uie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            }
+            #[doc = "Capture/Compare 1 interrupt enable"]
+            pub fn ccie(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 interrupt enable"]
+            pub fn set_ccie(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Trigger interrupt enable"]
+            pub const fn tie(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Trigger interrupt enable"]
+            pub fn set_tie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
+            }
+            #[doc = "Update DMA request enable"]
+            pub const fn ude(&self) -> bool {
+                let val = (self.0 >> 8usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Update DMA request enable"]
+            pub fn set_ude(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            }
+            #[doc = "Capture/Compare 1 DMA request enable"]
+            pub fn ccde(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 9usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Capture/Compare 1 DMA request enable"]
+            pub fn set_ccde(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 9usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Trigger DMA request enable"]
+            pub const fn tde(&self) -> bool {
+                let val = (self.0 >> 14usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Trigger DMA request enable"]
+            pub fn set_tde(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            }
+        }
+        impl Default for DierGp {
+            fn default() -> DierGp {
+                DierGp(0)
+            }
+        }
+        #[doc = "slave mode control register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Smcr(pub u32);
+        impl Smcr {
+            #[doc = "Slave mode selection"]
+            pub const fn sms(&self) -> super::vals::Sms {
+                let val = (self.0 >> 0usize) & 0x07;
+                super::vals::Sms(val as u8)
+            }
+            #[doc = "Slave mode selection"]
+            pub fn set_sms(&mut self, val: super::vals::Sms) {
+                self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
+            }
+            #[doc = "Trigger selection"]
+            pub const fn ts(&self) -> super::vals::Ts {
+                let val = (self.0 >> 4usize) & 0x07;
+                super::vals::Ts(val as u8)
+            }
+            #[doc = "Trigger selection"]
+            pub fn set_ts(&mut self, val: super::vals::Ts) {
+                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
+            }
+            #[doc = "Master/Slave mode"]
+            pub const fn msm(&self) -> super::vals::Msm {
+                let val = (self.0 >> 7usize) & 0x01;
+                super::vals::Msm(val as u8)
+            }
+            #[doc = "Master/Slave mode"]
+            pub fn set_msm(&mut self, val: super::vals::Msm) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
+            }
+            #[doc = "External trigger filter"]
+            pub const fn etf(&self) -> super::vals::Etf {
+                let val = (self.0 >> 8usize) & 0x0f;
+                super::vals::Etf(val as u8)
+            }
+            #[doc = "External trigger filter"]
+            pub fn set_etf(&mut self, val: super::vals::Etf) {
+                self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize);
+            }
+            #[doc = "External trigger prescaler"]
+            pub const fn etps(&self) -> super::vals::Etps {
+                let val = (self.0 >> 12usize) & 0x03;
+                super::vals::Etps(val as u8)
+            }
+            #[doc = "External trigger prescaler"]
+            pub fn set_etps(&mut self, val: super::vals::Etps) {
+                self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
+            }
+            #[doc = "External clock enable"]
+            pub const fn ece(&self) -> super::vals::Ece {
+                let val = (self.0 >> 14usize) & 0x01;
+                super::vals::Ece(val as u8)
+            }
+            #[doc = "External clock enable"]
+            pub fn set_ece(&mut self, val: super::vals::Ece) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
+            }
+            #[doc = "External trigger polarity"]
+            pub const fn etp(&self) -> super::vals::Etp {
+                let val = (self.0 >> 15usize) & 0x01;
+                super::vals::Etp(val as u8)
+            }
+            #[doc = "External trigger polarity"]
+            pub fn set_etp(&mut self, val: super::vals::Etp) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
+            }
+        }
+        impl Default for Smcr {
+            fn default() -> Smcr {
+                Smcr(0)
+            }
+        }
         #[doc = "DMA/Interrupt enable register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -3026,189 +3698,147 @@ pub mod timer_v1 {
                 DierAdv(0)
             }
         }
-        #[doc = "capture/compare enable register"]
+        #[doc = "status register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct CcerAdv(pub u32);
-        impl CcerAdv {
-            #[doc = "Capture/Compare 1 output enable"]
-            pub fn cce(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+        pub struct SrAdv(pub u32);
+        impl SrAdv {
+            #[doc = "Update interrupt flag"]
+            pub const fn uif(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Capture/Compare 1 output enable"]
-            pub fn set_cce(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "Update interrupt flag"]
+            pub fn set_uif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn ccp(&self, n: usize) -> bool {
+            #[doc = "Capture/compare 1 interrupt flag"]
+            pub fn ccif(&self, n: usize) -> bool {
                 assert!(n < 4usize);
-                let offs = 1usize + n * 4usize;
+                let offs = 1usize + n * 1usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn set_ccp(&mut self, n: usize, val: bool) {
+            #[doc = "Capture/compare 1 interrupt flag"]
+            pub fn set_ccif(&mut self, n: usize, val: bool) {
                 assert!(n < 4usize);
-                let offs = 1usize + n * 4usize;
+                let offs = 1usize + n * 1usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Capture/Compare 1 complementary output enable"]
-            pub fn ccne(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 2usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "COM interrupt flag"]
+            pub const fn comif(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "Capture/Compare 1 complementary output enable"]
-            pub fn set_ccne(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 2usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            #[doc = "COM interrupt flag"]
+            pub fn set_comif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn ccnp(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 3usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
+            #[doc = "Trigger interrupt flag"]
+            pub const fn tif(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn set_ccnp(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 3usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-        }
-        impl Default for CcerAdv {
-            fn default() -> CcerAdv {
-                CcerAdv(0)
+            #[doc = "Trigger interrupt flag"]
+            pub fn set_tif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-        }
-        #[doc = "DMA/Interrupt enable register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct DierBasic(pub u32);
-        impl DierBasic {
-            #[doc = "Update interrupt enable"]
-            pub const fn uie(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
+            #[doc = "Break interrupt flag"]
+            pub const fn bif(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
                 val != 0
             }
-            #[doc = "Update interrupt enable"]
-            pub fn set_uie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "Break interrupt flag"]
+            pub fn set_bif(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
-            #[doc = "Update DMA request enable"]
-            pub const fn ude(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
+            #[doc = "Capture/Compare 1 overcapture flag"]
+            pub fn ccof(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 9usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Update DMA request enable"]
-            pub fn set_ude(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            #[doc = "Capture/Compare 1 overcapture flag"]
+            pub fn set_ccof(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 9usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for DierBasic {
-            fn default() -> DierBasic {
-                DierBasic(0)
+        impl Default for SrAdv {
+            fn default() -> SrAdv {
+                SrAdv(0)
             }
         }
-        #[doc = "DMA address for full transfer"]
+        #[doc = "prescaler"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dmar(pub u32);
-        impl Dmar {
-            #[doc = "DMA register for burst accesses"]
-            pub const fn dmab(&self) -> u16 {
+        pub struct Psc(pub u32);
+        impl Psc {
+            #[doc = "Prescaler value"]
+            pub const fn psc(&self) -> u16 {
                 let val = (self.0 >> 0usize) & 0xffff;
                 val as u16
             }
-            #[doc = "DMA register for burst accesses"]
-            pub fn set_dmab(&mut self, val: u16) {
+            #[doc = "Prescaler value"]
+            pub fn set_psc(&mut self, val: u16) {
                 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for Dmar {
-            fn default() -> Dmar {
-                Dmar(0)
+        impl Default for Psc {
+            fn default() -> Psc {
+                Psc(0)
             }
         }
-        #[doc = "DMA/Interrupt enable register"]
+        #[doc = "capture/compare enable register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct DierGp(pub u32);
-        impl DierGp {
-            #[doc = "Update interrupt enable"]
-            pub const fn uie(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update interrupt enable"]
-            pub fn set_uie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Capture/Compare 1 interrupt enable"]
-            pub fn ccie(&self, n: usize) -> bool {
+        pub struct CcerGp(pub u32);
+        impl CcerGp {
+            #[doc = "Capture/Compare 1 output enable"]
+            pub fn cce(&self, n: usize) -> bool {
                 assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
+                let offs = 0usize + n * 4usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Capture/Compare 1 interrupt enable"]
-            pub fn set_ccie(&mut self, n: usize, val: bool) {
+            #[doc = "Capture/Compare 1 output enable"]
+            pub fn set_cce(&mut self, n: usize, val: bool) {
                 assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
+                let offs = 0usize + n * 4usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Trigger interrupt enable"]
-            pub const fn tie(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Trigger interrupt enable"]
-            pub fn set_tie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-            #[doc = "Update DMA request enable"]
-            pub const fn ude(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update DMA request enable"]
-            pub fn set_ude(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-            #[doc = "Capture/Compare 1 DMA request enable"]
-            pub fn ccde(&self, n: usize) -> bool {
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn ccp(&self, n: usize) -> bool {
                 assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
+                let offs = 1usize + n * 4usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Capture/Compare 1 DMA request enable"]
-            pub fn set_ccde(&mut self, n: usize, val: bool) {
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn set_ccp(&mut self, n: usize, val: bool) {
                 assert!(n < 4usize);
-                let offs = 9usize + n * 1usize;
+                let offs = 1usize + n * 4usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Trigger DMA request enable"]
-            pub const fn tde(&self) -> bool {
-                let val = (self.0 >> 14usize) & 0x01;
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn ccnp(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 3usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Trigger DMA request enable"]
-            pub fn set_tde(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            #[doc = "Capture/Compare 1 output Polarity"]
+            pub fn set_ccnp(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 3usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for DierGp {
-            fn default() -> DierGp {
-                DierGp(0)
+        impl Default for CcerGp {
+            fn default() -> CcerGp {
+                CcerGp(0)
             }
         }
         #[doc = "capture/compare mode register 2 (output mode)"]
@@ -3287,271 +3917,174 @@ pub mod timer_v1 {
                 CcmrOutput(0)
             }
         }
-        #[doc = "counter"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cnt16(pub u32);
-        impl Cnt16 {
-            #[doc = "counter value"]
-            pub const fn cnt(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
-            }
-            #[doc = "counter value"]
-            pub fn set_cnt(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
-            }
-        }
-        impl Default for Cnt16 {
-            fn default() -> Cnt16 {
-                Cnt16(0)
-            }
-        }
-        #[doc = "control register 1"]
+        #[doc = "control register 2"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr1Gp(pub u32);
-        impl Cr1Gp {
-            #[doc = "Counter enable"]
-            pub const fn cen(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Counter enable"]
-            pub fn set_cen(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Update disable"]
-            pub const fn udis(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update disable"]
-            pub fn set_udis(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
-            }
-            #[doc = "Update request source"]
-            pub const fn urs(&self) -> super::vals::Urs {
-                let val = (self.0 >> 2usize) & 0x01;
-                super::vals::Urs(val as u8)
-            }
-            #[doc = "Update request source"]
-            pub fn set_urs(&mut self, val: super::vals::Urs) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
-            }
-            #[doc = "One-pulse mode"]
-            pub const fn opm(&self) -> super::vals::Opm {
-                let val = (self.0 >> 3usize) & 0x01;
-                super::vals::Opm(val as u8)
-            }
-            #[doc = "One-pulse mode"]
-            pub fn set_opm(&mut self, val: super::vals::Opm) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
-            }
-            #[doc = "Direction"]
-            pub const fn dir(&self) -> super::vals::Dir {
-                let val = (self.0 >> 4usize) & 0x01;
-                super::vals::Dir(val as u8)
-            }
-            #[doc = "Direction"]
-            pub fn set_dir(&mut self, val: super::vals::Dir) {
-                self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
-            }
-            #[doc = "Center-aligned mode selection"]
-            pub const fn cms(&self) -> super::vals::Cms {
-                let val = (self.0 >> 5usize) & 0x03;
-                super::vals::Cms(val as u8)
-            }
-            #[doc = "Center-aligned mode selection"]
-            pub fn set_cms(&mut self, val: super::vals::Cms) {
-                self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize);
-            }
-            #[doc = "Auto-reload preload enable"]
-            pub const fn arpe(&self) -> super::vals::Arpe {
-                let val = (self.0 >> 7usize) & 0x01;
-                super::vals::Arpe(val as u8)
-            }
-            #[doc = "Auto-reload preload enable"]
-            pub fn set_arpe(&mut self, val: super::vals::Arpe) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
-            }
-            #[doc = "Clock division"]
-            pub const fn ckd(&self) -> super::vals::Ckd {
-                let val = (self.0 >> 8usize) & 0x03;
-                super::vals::Ckd(val as u8)
+        pub struct Cr2Basic(pub u32);
+        impl Cr2Basic {
+            #[doc = "Master mode selection"]
+            pub const fn mms(&self) -> super::vals::Mms {
+                let val = (self.0 >> 4usize) & 0x07;
+                super::vals::Mms(val as u8)
             }
-            #[doc = "Clock division"]
-            pub fn set_ckd(&mut self, val: super::vals::Ckd) {
-                self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
+            #[doc = "Master mode selection"]
+            pub fn set_mms(&mut self, val: super::vals::Mms) {
+                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
             }
         }
-        impl Default for Cr1Gp {
-            fn default() -> Cr1Gp {
-                Cr1Gp(0)
+        impl Default for Cr2Basic {
+            fn default() -> Cr2Basic {
+                Cr2Basic(0)
             }
         }
-        #[doc = "auto-reload register"]
+        #[doc = "DMA address for full transfer"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Arr32(pub u32);
-        impl Arr32 {
-            #[doc = "Auto-reload value"]
-            pub const fn arr(&self) -> u32 {
-                let val = (self.0 >> 0usize) & 0xffff_ffff;
-                val as u32
+        pub struct Dmar(pub u32);
+        impl Dmar {
+            #[doc = "DMA register for burst accesses"]
+            pub const fn dmab(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
             }
-            #[doc = "Auto-reload value"]
-            pub fn set_arr(&mut self, val: u32) {
-                self.0 =
-                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
+            #[doc = "DMA register for burst accesses"]
+            pub fn set_dmab(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for Arr32 {
-            fn default() -> Arr32 {
-                Arr32(0)
+        impl Default for Dmar {
+            fn default() -> Dmar {
+                Dmar(0)
             }
         }
-        #[doc = "auto-reload register"]
+        #[doc = "capture/compare register 1"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Arr16(pub u32);
-        impl Arr16 {
-            #[doc = "Auto-reload value"]
-            pub const fn arr(&self) -> u16 {
+        pub struct Ccr16(pub u32);
+        impl Ccr16 {
+            #[doc = "Capture/Compare 1 value"]
+            pub const fn ccr(&self) -> u16 {
                 let val = (self.0 >> 0usize) & 0xffff;
                 val as u16
             }
-            #[doc = "Auto-reload value"]
-            pub fn set_arr(&mut self, val: u16) {
+            #[doc = "Capture/Compare 1 value"]
+            pub fn set_ccr(&mut self, val: u16) {
                 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
             }
         }
-        impl Default for Arr16 {
-            fn default() -> Arr16 {
-                Arr16(0)
+        impl Default for Ccr16 {
+            fn default() -> Ccr16 {
+                Ccr16(0)
             }
         }
-        #[doc = "break and dead-time register"]
+        #[doc = "capture/compare mode register 1 (input mode)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Bdtr(pub u32);
-        impl Bdtr {
-            #[doc = "Dead-time generator setup"]
-            pub const fn dtg(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0xff;
-                val as u8
+        pub struct CcmrInput(pub u32);
+        impl CcmrInput {
+            #[doc = "Capture/Compare 1 selection"]
+            pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs {
+                assert!(n < 2usize);
+                let offs = 0usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x03;
+                super::vals::CcmrInputCcs(val as u8)
             }
-            #[doc = "Dead-time generator setup"]
-            pub fn set_dtg(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
+            #[doc = "Capture/Compare 1 selection"]
+            pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) {
+                assert!(n < 2usize);
+                let offs = 0usize + n * 8usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
             }
-            #[doc = "Lock configuration"]
-            pub const fn lock(&self) -> u8 {
-                let val = (self.0 >> 8usize) & 0x03;
+            #[doc = "Input capture 1 prescaler"]
+            pub fn icpsc(&self, n: usize) -> u8 {
+                assert!(n < 2usize);
+                let offs = 2usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x03;
                 val as u8
             }
-            #[doc = "Lock configuration"]
-            pub fn set_lock(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
-            }
-            #[doc = "Off-state selection for Idle mode"]
-            pub const fn ossi(&self) -> super::vals::Ossi {
-                let val = (self.0 >> 10usize) & 0x01;
-                super::vals::Ossi(val as u8)
+            #[doc = "Input capture 1 prescaler"]
+            pub fn set_icpsc(&mut self, n: usize, val: u8) {
+                assert!(n < 2usize);
+                let offs = 2usize + n * 8usize;
+                self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
             }
-            #[doc = "Off-state selection for Idle mode"]
-            pub fn set_ossi(&mut self, val: super::vals::Ossi) {
-                self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
+            #[doc = "Input capture 1 filter"]
+            pub fn icf(&self, n: usize) -> super::vals::Icf {
+                assert!(n < 2usize);
+                let offs = 4usize + n * 8usize;
+                let val = (self.0 >> offs) & 0x0f;
+                super::vals::Icf(val as u8)
             }
-            #[doc = "Off-state selection for Run mode"]
-            pub const fn ossr(&self) -> super::vals::Ossr {
-                let val = (self.0 >> 11usize) & 0x01;
-                super::vals::Ossr(val as u8)
+            #[doc = "Input capture 1 filter"]
+            pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) {
+                assert!(n < 2usize);
+                let offs = 4usize + n * 8usize;
+                self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
             }
-            #[doc = "Off-state selection for Run mode"]
-            pub fn set_ossr(&mut self, val: super::vals::Ossr) {
-                self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
+        }
+        impl Default for CcmrInput {
+            fn default() -> CcmrInput {
+                CcmrInput(0)
             }
-            #[doc = "Break enable"]
-            pub const fn bke(&self) -> bool {
-                let val = (self.0 >> 12usize) & 0x01;
+        }
+        #[doc = "event generation register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct EgrAdv(pub u32);
+        impl EgrAdv {
+            #[doc = "Update generation"]
+            pub const fn ug(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Break enable"]
-            pub fn set_bke(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
+            #[doc = "Update generation"]
+            pub fn set_ug(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Break polarity"]
-            pub const fn bkp(&self) -> bool {
-                let val = (self.0 >> 13usize) & 0x01;
+            #[doc = "Capture/compare 1 generation"]
+            pub fn ccg(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Break polarity"]
-            pub fn set_bkp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
+            #[doc = "Capture/compare 1 generation"]
+            pub fn set_ccg(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 1usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Automatic output enable"]
-            pub const fn aoe(&self) -> bool {
-                let val = (self.0 >> 14usize) & 0x01;
+            #[doc = "Capture/Compare control update generation"]
+            pub const fn comg(&self) -> bool {
+                let val = (self.0 >> 5usize) & 0x01;
                 val != 0
             }
-            #[doc = "Automatic output enable"]
-            pub fn set_aoe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
+            #[doc = "Capture/Compare control update generation"]
+            pub fn set_comg(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
             }
-            #[doc = "Main output enable"]
-            pub const fn moe(&self) -> bool {
-                let val = (self.0 >> 15usize) & 0x01;
+            #[doc = "Trigger generation"]
+            pub const fn tg(&self) -> bool {
+                let val = (self.0 >> 6usize) & 0x01;
                 val != 0
             }
-            #[doc = "Main output enable"]
-            pub fn set_moe(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
-            }
-        }
-        impl Default for Bdtr {
-            fn default() -> Bdtr {
-                Bdtr(0)
-            }
-        }
-        #[doc = "capture/compare register 1"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Ccr16(pub u32);
-        impl Ccr16 {
-            #[doc = "Capture/Compare 1 value"]
-            pub const fn ccr(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
-            }
-            #[doc = "Capture/Compare 1 value"]
-            pub fn set_ccr(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
-            }
-        }
-        impl Default for Ccr16 {
-            fn default() -> Ccr16 {
-                Ccr16(0)
+            #[doc = "Trigger generation"]
+            pub fn set_tg(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
             }
-        }
-        #[doc = "prescaler"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Psc(pub u32);
-        impl Psc {
-            #[doc = "Prescaler value"]
-            pub const fn psc(&self) -> u16 {
-                let val = (self.0 >> 0usize) & 0xffff;
-                val as u16
+            #[doc = "Break generation"]
+            pub const fn bg(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
             }
-            #[doc = "Prescaler value"]
-            pub fn set_psc(&mut self, val: u16) {
-                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            #[doc = "Break generation"]
+            pub fn set_bg(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
         }
-        impl Default for Psc {
-            fn default() -> Psc {
-                Psc(0)
+        impl Default for EgrAdv {
+            fn default() -> EgrAdv {
+                EgrAdv(0)
             }
         }
         #[doc = "control register 1"]
@@ -3610,81 +4143,32 @@ pub mod timer_v1 {
                 Cr1Basic(0)
             }
         }
-        #[doc = "capture/compare enable register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct CcerGp(pub u32);
-        impl CcerGp {
-            #[doc = "Capture/Compare 1 output enable"]
-            pub fn cce(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 output enable"]
-            pub fn set_cce(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn ccp(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn set_ccp(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn ccnp(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 3usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare 1 output Polarity"]
-            pub fn set_ccnp(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 3usize + n * 4usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-        }
-        impl Default for CcerGp {
-            fn default() -> CcerGp {
-                CcerGp(0)
-            }
-        }
-        #[doc = "status register"]
+        #[doc = "capture/compare register 1"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct SrBasic(pub u32);
-        impl SrBasic {
-            #[doc = "Update interrupt flag"]
-            pub const fn uif(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
+        pub struct Ccr32(pub u32);
+        impl Ccr32 {
+            #[doc = "Capture/Compare 1 value"]
+            pub const fn ccr(&self) -> u32 {
+                let val = (self.0 >> 0usize) & 0xffff_ffff;
+                val as u32
             }
-            #[doc = "Update interrupt flag"]
-            pub fn set_uif(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "Capture/Compare 1 value"]
+            pub fn set_ccr(&mut self, val: u32) {
+                self.0 =
+                    (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
             }
         }
-        impl Default for SrBasic {
-            fn default() -> SrBasic {
-                SrBasic(0)
+        impl Default for Ccr32 {
+            fn default() -> Ccr32 {
+                Ccr32(0)
             }
         }
         #[doc = "status register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct SrAdv(pub u32);
-        impl SrAdv {
+        pub struct SrGp(pub u32);
+        impl SrGp {
             #[doc = "Update interrupt flag"]
             pub const fn uif(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
@@ -3748,910 +4232,9 @@ pub mod timer_v1 {
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for SrAdv {
-            fn default() -> SrAdv {
-                SrAdv(0)
-            }
-        }
-        #[doc = "event generation register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct EgrGp(pub u32);
-        impl EgrGp {
-            #[doc = "Update generation"]
-            pub const fn ug(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update generation"]
-            pub fn set_ug(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Capture/compare 1 generation"]
-            pub fn ccg(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/compare 1 generation"]
-            pub fn set_ccg(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare control update generation"]
-            pub const fn comg(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare control update generation"]
-            pub fn set_comg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
-            }
-            #[doc = "Trigger generation"]
-            pub const fn tg(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Trigger generation"]
-            pub fn set_tg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-            #[doc = "Break generation"]
-            pub const fn bg(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Break generation"]
-            pub fn set_bg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
-            }
-        }
-        impl Default for EgrGp {
-            fn default() -> EgrGp {
-                EgrGp(0)
-            }
-        }
-        #[doc = "event generation register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct EgrAdv(pub u32);
-        impl EgrAdv {
-            #[doc = "Update generation"]
-            pub const fn ug(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update generation"]
-            pub fn set_ug(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Capture/compare 1 generation"]
-            pub fn ccg(&self, n: usize) -> bool {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/compare 1 generation"]
-            pub fn set_ccg(&mut self, n: usize, val: bool) {
-                assert!(n < 4usize);
-                let offs = 1usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
-            }
-            #[doc = "Capture/Compare control update generation"]
-            pub const fn comg(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Capture/Compare control update generation"]
-            pub fn set_comg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
-            }
-            #[doc = "Trigger generation"]
-            pub const fn tg(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Trigger generation"]
-            pub fn set_tg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-            #[doc = "Break generation"]
-            pub const fn bg(&self) -> bool {
-                let val = (self.0 >> 7usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Break generation"]
-            pub fn set_bg(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
-            }
-        }
-        impl Default for EgrAdv {
-            fn default() -> EgrAdv {
-                EgrAdv(0)
-            }
-        }
-        #[doc = "event generation register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct EgrBasic(pub u32);
-        impl EgrBasic {
-            #[doc = "Update generation"]
-            pub const fn ug(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Update generation"]
-            pub fn set_ug(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-        }
-        impl Default for EgrBasic {
-            fn default() -> EgrBasic {
-                EgrBasic(0)
-            }
-        }
-        #[doc = "DMA control register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Dcr(pub u32);
-        impl Dcr {
-            #[doc = "DMA base address"]
-            pub const fn dba(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x1f;
-                val as u8
-            }
-            #[doc = "DMA base address"]
-            pub fn set_dba(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
-            }
-            #[doc = "DMA burst length"]
-            pub const fn dbl(&self) -> u8 {
-                let val = (self.0 >> 8usize) & 0x1f;
-                val as u8
-            }
-            #[doc = "DMA burst length"]
-            pub fn set_dbl(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
-            }
-        }
-        impl Default for Dcr {
-            fn default() -> Dcr {
-                Dcr(0)
-            }
-        }
-        #[doc = "slave mode control register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Smcr(pub u32);
-        impl Smcr {
-            #[doc = "Slave mode selection"]
-            pub const fn sms(&self) -> super::vals::Sms {
-                let val = (self.0 >> 0usize) & 0x07;
-                super::vals::Sms(val as u8)
-            }
-            #[doc = "Slave mode selection"]
-            pub fn set_sms(&mut self, val: super::vals::Sms) {
-                self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
-            }
-            #[doc = "Trigger selection"]
-            pub const fn ts(&self) -> super::vals::Ts {
-                let val = (self.0 >> 4usize) & 0x07;
-                super::vals::Ts(val as u8)
-            }
-            #[doc = "Trigger selection"]
-            pub fn set_ts(&mut self, val: super::vals::Ts) {
-                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
-            }
-            #[doc = "Master/Slave mode"]
-            pub const fn msm(&self) -> super::vals::Msm {
-                let val = (self.0 >> 7usize) & 0x01;
-                super::vals::Msm(val as u8)
-            }
-            #[doc = "Master/Slave mode"]
-            pub fn set_msm(&mut self, val: super::vals::Msm) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
-            }
-            #[doc = "External trigger filter"]
-            pub const fn etf(&self) -> super::vals::Etf {
-                let val = (self.0 >> 8usize) & 0x0f;
-                super::vals::Etf(val as u8)
-            }
-            #[doc = "External trigger filter"]
-            pub fn set_etf(&mut self, val: super::vals::Etf) {
-                self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize);
-            }
-            #[doc = "External trigger prescaler"]
-            pub const fn etps(&self) -> super::vals::Etps {
-                let val = (self.0 >> 12usize) & 0x03;
-                super::vals::Etps(val as u8)
-            }
-            #[doc = "External trigger prescaler"]
-            pub fn set_etps(&mut self, val: super::vals::Etps) {
-                self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
-            }
-            #[doc = "External clock enable"]
-            pub const fn ece(&self) -> super::vals::Ece {
-                let val = (self.0 >> 14usize) & 0x01;
-                super::vals::Ece(val as u8)
-            }
-            #[doc = "External clock enable"]
-            pub fn set_ece(&mut self, val: super::vals::Ece) {
-                self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
-            }
-            #[doc = "External trigger polarity"]
-            pub const fn etp(&self) -> super::vals::Etp {
-                let val = (self.0 >> 15usize) & 0x01;
-                super::vals::Etp(val as u8)
-            }
-            #[doc = "External trigger polarity"]
-            pub fn set_etp(&mut self, val: super::vals::Etp) {
-                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
-            }
-        }
-        impl Default for Smcr {
-            fn default() -> Smcr {
-                Smcr(0)
-            }
-        }
-        #[doc = "control register 2"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr2Gp(pub u32);
-        impl Cr2Gp {
-            #[doc = "Capture/compare DMA selection"]
-            pub const fn ccds(&self) -> super::vals::Ccds {
-                let val = (self.0 >> 3usize) & 0x01;
-                super::vals::Ccds(val as u8)
-            }
-            #[doc = "Capture/compare DMA selection"]
-            pub fn set_ccds(&mut self, val: super::vals::Ccds) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
-            }
-            #[doc = "Master mode selection"]
-            pub const fn mms(&self) -> super::vals::Mms {
-                let val = (self.0 >> 4usize) & 0x07;
-                super::vals::Mms(val as u8)
-            }
-            #[doc = "Master mode selection"]
-            pub fn set_mms(&mut self, val: super::vals::Mms) {
-                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
-            }
-            #[doc = "TI1 selection"]
-            pub const fn ti1s(&self) -> super::vals::Tis {
-                let val = (self.0 >> 7usize) & 0x01;
-                super::vals::Tis(val as u8)
-            }
-            #[doc = "TI1 selection"]
-            pub fn set_ti1s(&mut self, val: super::vals::Tis) {
-                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
-            }
-        }
-        impl Default for Cr2Gp {
-            fn default() -> Cr2Gp {
-                Cr2Gp(0)
-            }
-        }
-        #[doc = "control register 2"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr2Basic(pub u32);
-        impl Cr2Basic {
-            #[doc = "Master mode selection"]
-            pub const fn mms(&self) -> super::vals::Mms {
-                let val = (self.0 >> 4usize) & 0x07;
-                super::vals::Mms(val as u8)
-            }
-            #[doc = "Master mode selection"]
-            pub fn set_mms(&mut self, val: super::vals::Mms) {
-                self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
-            }
-        }
-        impl Default for Cr2Basic {
-            fn default() -> Cr2Basic {
-                Cr2Basic(0)
-            }
-        }
-    }
-    pub mod vals {
-        use crate::generic::*;
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Etp(pub u8);
-        impl Etp {
-            #[doc = "ETR is noninverted, active at high level or rising edge"]
-            pub const NOTINVERTED: Self = Self(0);
-            #[doc = "ETR is inverted, active at low level or falling edge"]
-            pub const INVERTED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ocm(pub u8);
-        impl Ocm {
-            #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
-            pub const FROZEN: Self = Self(0);
-            #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
-            pub const ACTIVEONMATCH: Self = Self(0x01);
-            #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
-            pub const INACTIVEONMATCH: Self = Self(0x02);
-            #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
-            pub const TOGGLE: Self = Self(0x03);
-            #[doc = "OCyREF is forced low"]
-            pub const FORCEINACTIVE: Self = Self(0x04);
-            #[doc = "OCyREF is forced high"]
-            pub const FORCEACTIVE: Self = Self(0x05);
-            #[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
-            pub const PWMMODE1: Self = Self(0x06);
-            #[doc = "Inversely to PwmMode1"]
-            pub const PWMMODE2: Self = Self(0x07);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Icf(pub u8);
-        impl Icf {
-            #[doc = "No filter, sampling is done at fDTS"]
-            pub const NOFILTER: Self = Self(0);
-            #[doc = "fSAMPLING=fCK_INT, N=2"]
-            pub const FCK_INT_N2: Self = Self(0x01);
-            #[doc = "fSAMPLING=fCK_INT, N=4"]
-            pub const FCK_INT_N4: Self = Self(0x02);
-            #[doc = "fSAMPLING=fCK_INT, N=8"]
-            pub const FCK_INT_N8: Self = Self(0x03);
-            #[doc = "fSAMPLING=fDTS/2, N=6"]
-            pub const FDTS_DIV2_N6: Self = Self(0x04);
-            #[doc = "fSAMPLING=fDTS/2, N=8"]
-            pub const FDTS_DIV2_N8: Self = Self(0x05);
-            #[doc = "fSAMPLING=fDTS/4, N=6"]
-            pub const FDTS_DIV4_N6: Self = Self(0x06);
-            #[doc = "fSAMPLING=fDTS/4, N=8"]
-            pub const FDTS_DIV4_N8: Self = Self(0x07);
-            #[doc = "fSAMPLING=fDTS/8, N=6"]
-            pub const FDTS_DIV8_N6: Self = Self(0x08);
-            #[doc = "fSAMPLING=fDTS/8, N=8"]
-            pub const FDTS_DIV8_N8: Self = Self(0x09);
-            #[doc = "fSAMPLING=fDTS/16, N=5"]
-            pub const FDTS_DIV16_N5: Self = Self(0x0a);
-            #[doc = "fSAMPLING=fDTS/16, N=6"]
-            pub const FDTS_DIV16_N6: Self = Self(0x0b);
-            #[doc = "fSAMPLING=fDTS/16, N=8"]
-            pub const FDTS_DIV16_N8: Self = Self(0x0c);
-            #[doc = "fSAMPLING=fDTS/32, N=5"]
-            pub const FDTS_DIV32_N5: Self = Self(0x0d);
-            #[doc = "fSAMPLING=fDTS/32, N=6"]
-            pub const FDTS_DIV32_N6: Self = Self(0x0e);
-            #[doc = "fSAMPLING=fDTS/32, N=8"]
-            pub const FDTS_DIV32_N8: Self = Self(0x0f);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Arpe(pub u8);
-        impl Arpe {
-            #[doc = "TIMx_APRR register is not buffered"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "TIMx_APRR register is buffered"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Sms(pub u8);
-        impl Sms {
-            #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."]
-            pub const ENCODER_MODE_1: Self = Self(0x01);
-            #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."]
-            pub const ENCODER_MODE_2: Self = Self(0x02);
-            #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."]
-            pub const ENCODER_MODE_3: Self = Self(0x03);
-            #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."]
-            pub const RESET_MODE: Self = Self(0x04);
-            #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."]
-            pub const GATED_MODE: Self = Self(0x05);
-            #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."]
-            pub const TRIGGER_MODE: Self = Self(0x06);
-            #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."]
-            pub const EXT_CLOCK_MODE: Self = Self(0x07);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Msm(pub u8);
-        impl Msm {
-            #[doc = "No action"]
-            pub const NOSYNC: Self = Self(0);
-            #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
-            pub const SYNC: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Dir(pub u8);
-        impl Dir {
-            #[doc = "Counter used as upcounter"]
-            pub const UP: Self = Self(0);
-            #[doc = "Counter used as downcounter"]
-            pub const DOWN: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ckd(pub u8);
-        impl Ckd {
-            #[doc = "t_DTS = t_CK_INT"]
-            pub const DIV1: Self = Self(0);
-            #[doc = "t_DTS = 2 × t_CK_INT"]
-            pub const DIV2: Self = Self(0x01);
-            #[doc = "t_DTS = 4 × t_CK_INT"]
-            pub const DIV4: Self = Self(0x02);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Opm(pub u8);
-        impl Opm {
-            #[doc = "Counter is not stopped at update event"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ece(pub u8);
-        impl Ece {
-            #[doc = "External clock mode 2 disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct CcmrOutputCcs(pub u8);
-        impl CcmrOutputCcs {
-            #[doc = "CCx channel is configured as output"]
-            pub const OUTPUT: Self = Self(0);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ossr(pub u8);
-        impl Ossr {
-            #[doc = "When inactive, OC/OCN outputs are disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"]
-            pub const IDLELEVEL: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct CcmrInputCcs(pub u8);
-        impl CcmrInputCcs {
-            #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"]
-            pub const TI4: Self = Self(0x01);
-            #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"]
-            pub const TI3: Self = Self(0x02);
-            #[doc = "CCx channel is configured as input, ICx is mapped on TRC"]
-            pub const TRC: Self = Self(0x03);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Mms(pub u8);
-        impl Mms {
-            #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
-            pub const RESET: Self = Self(0);
-            #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
-            pub const ENABLE: Self = Self(0x01);
-            #[doc = "The update event is selected as trigger output"]
-            pub const UPDATE: Self = Self(0x02);
-            #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
-            pub const COMPAREPULSE: Self = Self(0x03);
-            #[doc = "OC1REF signal is used as trigger output"]
-            pub const COMPAREOC1: Self = Self(0x04);
-            #[doc = "OC2REF signal is used as trigger output"]
-            pub const COMPAREOC2: Self = Self(0x05);
-            #[doc = "OC3REF signal is used as trigger output"]
-            pub const COMPAREOC3: Self = Self(0x06);
-            #[doc = "OC4REF signal is used as trigger output"]
-            pub const COMPAREOC4: Self = Self(0x07);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ossi(pub u8);
-        impl Ossi {
-            #[doc = "When inactive, OC/OCN outputs are disabled"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "When inactive, OC/OCN outputs are forced to idle level"]
-            pub const IDLELEVEL: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Etf(pub u8);
-        impl Etf {
-            #[doc = "No filter, sampling is done at fDTS"]
-            pub const NOFILTER: Self = Self(0);
-            #[doc = "fSAMPLING=fCK_INT, N=2"]
-            pub const FCK_INT_N2: Self = Self(0x01);
-            #[doc = "fSAMPLING=fCK_INT, N=4"]
-            pub const FCK_INT_N4: Self = Self(0x02);
-            #[doc = "fSAMPLING=fCK_INT, N=8"]
-            pub const FCK_INT_N8: Self = Self(0x03);
-            #[doc = "fSAMPLING=fDTS/2, N=6"]
-            pub const FDTS_DIV2_N6: Self = Self(0x04);
-            #[doc = "fSAMPLING=fDTS/2, N=8"]
-            pub const FDTS_DIV2_N8: Self = Self(0x05);
-            #[doc = "fSAMPLING=fDTS/4, N=6"]
-            pub const FDTS_DIV4_N6: Self = Self(0x06);
-            #[doc = "fSAMPLING=fDTS/4, N=8"]
-            pub const FDTS_DIV4_N8: Self = Self(0x07);
-            #[doc = "fSAMPLING=fDTS/8, N=6"]
-            pub const FDTS_DIV8_N6: Self = Self(0x08);
-            #[doc = "fSAMPLING=fDTS/8, N=8"]
-            pub const FDTS_DIV8_N8: Self = Self(0x09);
-            #[doc = "fSAMPLING=fDTS/16, N=5"]
-            pub const FDTS_DIV16_N5: Self = Self(0x0a);
-            #[doc = "fSAMPLING=fDTS/16, N=6"]
-            pub const FDTS_DIV16_N6: Self = Self(0x0b);
-            #[doc = "fSAMPLING=fDTS/16, N=8"]
-            pub const FDTS_DIV16_N8: Self = Self(0x0c);
-            #[doc = "fSAMPLING=fDTS/32, N=5"]
-            pub const FDTS_DIV32_N5: Self = Self(0x0d);
-            #[doc = "fSAMPLING=fDTS/32, N=6"]
-            pub const FDTS_DIV32_N6: Self = Self(0x0e);
-            #[doc = "fSAMPLING=fDTS/32, N=8"]
-            pub const FDTS_DIV32_N8: Self = Self(0x0f);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Etps(pub u8);
-        impl Etps {
-            #[doc = "Prescaler OFF"]
-            pub const DIV1: Self = Self(0);
-            #[doc = "ETRP frequency divided by 2"]
-            pub const DIV2: Self = Self(0x01);
-            #[doc = "ETRP frequency divided by 4"]
-            pub const DIV4: Self = Self(0x02);
-            #[doc = "ETRP frequency divided by 8"]
-            pub const DIV8: Self = Self(0x03);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ts(pub u8);
-        impl Ts {
-            #[doc = "Internal Trigger 0 (ITR0)"]
-            pub const ITR0: Self = Self(0);
-            #[doc = "Internal Trigger 1 (ITR1)"]
-            pub const ITR1: Self = Self(0x01);
-            #[doc = "Internal Trigger 2 (ITR2)"]
-            pub const ITR2: Self = Self(0x02);
-            #[doc = "TI1 Edge Detector (TI1F_ED)"]
-            pub const TI1F_ED: Self = Self(0x04);
-            #[doc = "Filtered Timer Input 1 (TI1FP1)"]
-            pub const TI1FP1: Self = Self(0x05);
-            #[doc = "Filtered Timer Input 2 (TI2FP2)"]
-            pub const TI2FP2: Self = Self(0x06);
-            #[doc = "External Trigger input (ETRF)"]
-            pub const ETRF: Self = Self(0x07);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ccds(pub u8);
-        impl Ccds {
-            #[doc = "CCx DMA request sent when CCx event occurs"]
-            pub const ONCOMPARE: Self = Self(0);
-            #[doc = "CCx DMA request sent when update event occurs"]
-            pub const ONUPDATE: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cms(pub u8);
-        impl Cms {
-            #[doc = "The counter counts up or down depending on the direction bit"]
-            pub const EDGEALIGNED: Self = Self(0);
-            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
-            pub const CENTERALIGNED1: Self = Self(0x01);
-            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
-            pub const CENTERALIGNED2: Self = Self(0x02);
-            #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
-            pub const CENTERALIGNED3: Self = Self(0x03);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Tis(pub u8);
-        impl Tis {
-            #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
-            pub const NORMAL: Self = Self(0);
-            #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
-            pub const XOR: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Ocpe(pub u8);
-        impl Ocpe {
-            #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"]
-            pub const DISABLED: Self = Self(0);
-            #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"]
-            pub const ENABLED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Urs(pub u8);
-        impl Urs {
-            #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
-            pub const ANYEVENT: Self = Self(0);
-            #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
-            pub const COUNTERONLY: Self = Self(0x01);
-        }
-    }
-}
-pub mod syscfg_f4 {
-    use crate::generic::*;
-    #[doc = "System configuration controller"]
-    #[derive(Copy, Clone)]
-    pub struct Syscfg(pub *mut u8);
-    unsafe impl Send for Syscfg {}
-    unsafe impl Sync for Syscfg {}
-    impl Syscfg {
-        #[doc = "memory remap register"]
-        pub fn memrm(self) -> Reg<regs::Memrm, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "peripheral mode configuration register"]
-        pub fn pmc(self) -> Reg<regs::Pmc, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "external interrupt configuration register"]
-        pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
-            assert!(n < 4usize);
-            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
-        }
-        #[doc = "Compensation cell control register"]
-        pub fn cmpcr(self) -> Reg<regs::Cmpcr, R> {
-            unsafe { Reg::from_ptr(self.0.add(32usize)) }
-        }
-    }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "external interrupt configuration register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Exticr(pub u32);
-        impl Exticr {
-            #[doc = "EXTI x configuration"]
-            pub fn exti(&self, n: usize) -> u8 {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x0f;
-                val as u8
-            }
-            #[doc = "EXTI x configuration"]
-            pub fn set_exti(&mut self, n: usize, val: u8) {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
-            }
-        }
-        impl Default for Exticr {
-            fn default() -> Exticr {
-                Exticr(0)
-            }
-        }
-        #[doc = "Compensation cell control register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cmpcr(pub u32);
-        impl Cmpcr {
-            #[doc = "Compensation cell power-down"]
-            pub const fn cmp_pd(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Compensation cell power-down"]
-            pub fn set_cmp_pd(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "READY"]
-            pub const fn ready(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "READY"]
-            pub fn set_ready(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-        }
-        impl Default for Cmpcr {
-            fn default() -> Cmpcr {
-                Cmpcr(0)
-            }
-        }
-        #[doc = "memory remap register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Memrm(pub u32);
-        impl Memrm {
-            #[doc = "Memory mapping selection"]
-            pub const fn mem_mode(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x07;
-                val as u8
-            }
-            #[doc = "Memory mapping selection"]
-            pub fn set_mem_mode(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
-            }
-            #[doc = "Flash bank mode selection"]
-            pub const fn fb_mode(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Flash bank mode selection"]
-            pub fn set_fb_mode(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
-            #[doc = "FMC memory mapping swap"]
-            pub const fn swp_fmc(&self) -> u8 {
-                let val = (self.0 >> 10usize) & 0x03;
-                val as u8
-            }
-            #[doc = "FMC memory mapping swap"]
-            pub fn set_swp_fmc(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
-            }
-        }
-        impl Default for Memrm {
-            fn default() -> Memrm {
-                Memrm(0)
-            }
-        }
-        #[doc = "peripheral mode configuration register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Pmc(pub u32);
-        impl Pmc {
-            #[doc = "ADC1DC2"]
-            pub const fn adc1dc2(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
-                val != 0
-            }
-            #[doc = "ADC1DC2"]
-            pub fn set_adc1dc2(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
-            }
-            #[doc = "ADC2DC2"]
-            pub const fn adc2dc2(&self) -> bool {
-                let val = (self.0 >> 17usize) & 0x01;
-                val != 0
-            }
-            #[doc = "ADC2DC2"]
-            pub fn set_adc2dc2(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
-            }
-            #[doc = "ADC3DC2"]
-            pub const fn adc3dc2(&self) -> bool {
-                let val = (self.0 >> 18usize) & 0x01;
-                val != 0
-            }
-            #[doc = "ADC3DC2"]
-            pub fn set_adc3dc2(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
-            }
-            #[doc = "Ethernet PHY interface selection"]
-            pub const fn mii_rmii_sel(&self) -> bool {
-                let val = (self.0 >> 23usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Ethernet PHY interface selection"]
-            pub fn set_mii_rmii_sel(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
-            }
-        }
-        impl Default for Pmc {
-            fn default() -> Pmc {
-                Pmc(0)
-            }
-        }
-    }
-}
-pub mod rng_v1 {
-    use crate::generic::*;
-    #[doc = "Random number generator"]
-    #[derive(Copy, Clone)]
-    pub struct Rng(pub *mut u8);
-    unsafe impl Send for Rng {}
-    unsafe impl Sync for Rng {}
-    impl Rng {
-        #[doc = "control register"]
-        pub fn cr(self) -> Reg<regs::Cr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(0usize)) }
-        }
-        #[doc = "status register"]
-        pub fn sr(self) -> Reg<regs::Sr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(4usize)) }
-        }
-        #[doc = "data register"]
-        pub fn dr(self) -> Reg<u32, R> {
-            unsafe { Reg::from_ptr(self.0.add(8usize)) }
-        }
-    }
-    pub mod regs {
-        use crate::generic::*;
-        #[doc = "control register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cr(pub u32);
-        impl Cr {
-            #[doc = "Random number generator enable"]
-            pub const fn rngen(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Random number generator enable"]
-            pub fn set_rngen(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
-            }
-            #[doc = "Interrupt enable"]
-            pub const fn ie(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Interrupt enable"]
-            pub fn set_ie(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
-            }
-        }
-        impl Default for Cr {
-            fn default() -> Cr {
-                Cr(0)
-            }
-        }
-        #[doc = "status register"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Sr(pub u32);
-        impl Sr {
-            #[doc = "Data ready"]
-            pub const fn drdy(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Data ready"]
-            pub fn set_drdy(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "Clock error current status"]
-            pub const fn cecs(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Clock error current status"]
-            pub fn set_cecs(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
-            }
-            #[doc = "Seed error current status"]
-            pub const fn secs(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Seed error current status"]
-            pub fn set_secs(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
-            }
-            #[doc = "Clock error interrupt status"]
-            pub const fn ceis(&self) -> bool {
-                let val = (self.0 >> 5usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Clock error interrupt status"]
-            pub fn set_ceis(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
-            }
-            #[doc = "Seed error interrupt status"]
-            pub const fn seis(&self) -> bool {
-                let val = (self.0 >> 6usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Seed error interrupt status"]
-            pub fn set_seis(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
-            }
-        }
-        impl Default for Sr {
-            fn default() -> Sr {
-                Sr(0)
+        impl Default for SrGp {
+            fn default() -> SrGp {
+                SrGp(0)
             }
         }
     }
@@ -4715,30 +4298,6 @@ pub mod exti_v1 {
                 Imr(0)
             }
         }
-        #[doc = "Event mask register (EXTI_EMR)"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Emr(pub u32);
-        impl Emr {
-            #[doc = "Event Mask on line 0"]
-            pub fn mr(&self, n: usize) -> super::vals::Mr {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Mr(val as u8)
-            }
-            #[doc = "Event Mask on line 0"]
-            pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) {
-                assert!(n < 23usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
-            }
-        }
-        impl Default for Emr {
-            fn default() -> Emr {
-                Emr(0)
-            }
-        }
         #[doc = "Falling Trigger selection register (EXTI_FTSR)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -4811,6 +4370,30 @@ pub mod exti_v1 {
                 Pr(0)
             }
         }
+        #[doc = "Event mask register (EXTI_EMR)"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Emr(pub u32);
+        impl Emr {
+            #[doc = "Event Mask on line 0"]
+            pub fn mr(&self, n: usize) -> super::vals::Mr {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                let val = (self.0 >> offs) & 0x01;
+                super::vals::Mr(val as u8)
+            }
+            #[doc = "Event Mask on line 0"]
+            pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) {
+                assert!(n < 23usize);
+                let offs = 0usize + n * 1usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            }
+        }
+        impl Default for Emr {
+            fn default() -> Emr {
+                Emr(0)
+            }
+        }
         #[doc = "Rising Trigger selection register (EXTI_RTSR)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
@@ -4840,20 +4423,6 @@ pub mod exti_v1 {
         use crate::generic::*;
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Swierw(pub u8);
-        impl Swierw {
-            #[doc = "Generates an interrupt request"]
-            pub const PEND: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Prw(pub u8);
-        impl Prw {
-            #[doc = "Clears pending bit"]
-            pub const CLEAR: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
         pub struct Mr(pub u8);
         impl Mr {
             #[doc = "Interrupt request line is masked"]
@@ -4879,74 +4448,488 @@ pub mod exti_v1 {
             #[doc = "Selected trigger request occurred"]
             pub const PENDING: Self = Self(0x01);
         }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Swierw(pub u8);
+        impl Swierw {
+            #[doc = "Generates an interrupt request"]
+            pub const PEND: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Prw(pub u8);
+        impl Prw {
+            #[doc = "Clears pending bit"]
+            pub const CLEAR: Self = Self(0x01);
+        }
     }
 }
-pub mod gpio_v1 {
+pub mod generic {
+    use core::marker::PhantomData;
+    #[derive(Copy, Clone)]
+    pub struct RW;
+    #[derive(Copy, Clone)]
+    pub struct R;
+    #[derive(Copy, Clone)]
+    pub struct W;
+    mod sealed {
+        use super::*;
+        pub trait Access {}
+        impl Access for R {}
+        impl Access for W {}
+        impl Access for RW {}
+    }
+    pub trait Access: sealed::Access + Copy {}
+    impl Access for R {}
+    impl Access for W {}
+    impl Access for RW {}
+    pub trait Read: Access {}
+    impl Read for RW {}
+    impl Read for R {}
+    pub trait Write: Access {}
+    impl Write for RW {}
+    impl Write for W {}
+    #[derive(Copy, Clone)]
+    pub struct Reg<T: Copy, A: Access> {
+        ptr: *mut u8,
+        phantom: PhantomData<*mut (T, A)>,
+    }
+    unsafe impl<T: Copy, A: Access> Send for Reg<T, A> {}
+    unsafe impl<T: Copy, A: Access> Sync for Reg<T, A> {}
+    impl<T: Copy, A: Access> Reg<T, A> {
+        pub fn from_ptr(ptr: *mut u8) -> Self {
+            Self {
+                ptr,
+                phantom: PhantomData,
+            }
+        }
+        pub fn ptr(&self) -> *mut T {
+            self.ptr as _
+        }
+    }
+    impl<T: Copy, A: Read> Reg<T, A> {
+        pub unsafe fn read(&self) -> T {
+            (self.ptr as *mut T).read_volatile()
+        }
+    }
+    impl<T: Copy, A: Write> Reg<T, A> {
+        pub unsafe fn write_value(&self, val: T) {
+            (self.ptr as *mut T).write_volatile(val)
+        }
+    }
+    impl<T: Default + Copy, A: Write> Reg<T, A> {
+        pub unsafe fn write<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
+            let mut val = Default::default();
+            let res = f(&mut val);
+            self.write_value(val);
+            res
+        }
+    }
+    impl<T: Copy, A: Read + Write> Reg<T, A> {
+        pub unsafe fn modify<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
+            let mut val = self.read();
+            let res = f(&mut val);
+            self.write_value(val);
+            res
+        }
+    }
+}
+pub mod dma_v2 {
     use crate::generic::*;
-    #[doc = "General purpose I/O"]
+    #[doc = "DMA controller"]
     #[derive(Copy, Clone)]
-    pub struct Gpio(pub *mut u8);
-    unsafe impl Send for Gpio {}
-    unsafe impl Sync for Gpio {}
-    impl Gpio {
-        #[doc = "Port configuration register low (GPIOn_CRL)"]
-        pub fn cr(self, n: usize) -> Reg<regs::Cr, RW> {
+    pub struct Dma(pub *mut u8);
+    unsafe impl Send for Dma {}
+    unsafe impl Sync for Dma {}
+    impl Dma {
+        #[doc = "low interrupt status register"]
+        pub fn isr(self, n: usize) -> Reg<regs::Isr, R> {
             assert!(n < 2usize);
             unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
         }
-        #[doc = "Port input data register (GPIOn_IDR)"]
-        pub fn idr(self) -> Reg<regs::Idr, R> {
+        #[doc = "low interrupt flag clear register"]
+        pub fn ifcr(self, n: usize) -> Reg<regs::Ifcr, W> {
+            assert!(n < 2usize);
+            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
+        }
+        #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
+        pub fn st(self, n: usize) -> St {
+            assert!(n < 8usize);
+            unsafe { St(self.0.add(16usize + n * 24usize)) }
+        }
+    }
+    #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
+    #[derive(Copy, Clone)]
+    pub struct St(pub *mut u8);
+    unsafe impl Send for St {}
+    unsafe impl Sync for St {}
+    impl St {
+        #[doc = "stream x configuration register"]
+        pub fn cr(self) -> Reg<regs::Cr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
+        }
+        #[doc = "stream x number of data register"]
+        pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
+        }
+        #[doc = "stream x peripheral address register"]
+        pub fn par(self) -> Reg<u32, RW> {
             unsafe { Reg::from_ptr(self.0.add(8usize)) }
         }
-        #[doc = "Port output data register (GPIOn_ODR)"]
-        pub fn odr(self) -> Reg<regs::Odr, RW> {
+        #[doc = "stream x memory 0 address register"]
+        pub fn m0ar(self) -> Reg<u32, RW> {
             unsafe { Reg::from_ptr(self.0.add(12usize)) }
         }
-        #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
-        pub fn bsrr(self) -> Reg<regs::Bsrr, W> {
+        #[doc = "stream x memory 1 address register"]
+        pub fn m1ar(self) -> Reg<u32, RW> {
             unsafe { Reg::from_ptr(self.0.add(16usize)) }
         }
-        #[doc = "Port bit reset register (GPIOn_BRR)"]
-        pub fn brr(self) -> Reg<regs::Brr, W> {
+        #[doc = "stream x FIFO control register"]
+        pub fn fcr(self) -> Reg<regs::Fcr, RW> {
             unsafe { Reg::from_ptr(self.0.add(20usize)) }
         }
-        #[doc = "Port configuration lock register"]
-        pub fn lckr(self) -> Reg<regs::Lckr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+    }
+    pub mod vals {
+        use crate::generic::*;
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Inc(pub u8);
+        impl Inc {
+            #[doc = "Address pointer is fixed"]
+            pub const FIXED: Self = Self(0);
+            #[doc = "Address pointer is incremented after each data transfer"]
+            pub const INCREMENTED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Dbm(pub u8);
+        impl Dbm {
+            #[doc = "No buffer switching at the end of transfer"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Memory target switched at the end of the DMA transfer"]
+            pub const ENABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Pfctrl(pub u8);
+        impl Pfctrl {
+            #[doc = "The DMA is the flow controller"]
+            pub const DMA: Self = Self(0);
+            #[doc = "The peripheral is the flow controller"]
+            pub const PERIPHERAL: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Pl(pub u8);
+        impl Pl {
+            #[doc = "Low"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Medium"]
+            pub const MEDIUM: Self = Self(0x01);
+            #[doc = "High"]
+            pub const HIGH: Self = Self(0x02);
+            #[doc = "Very high"]
+            pub const VERYHIGH: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Fth(pub u8);
+        impl Fth {
+            #[doc = "1/4 full FIFO"]
+            pub const QUARTER: Self = Self(0);
+            #[doc = "1/2 full FIFO"]
+            pub const HALF: Self = Self(0x01);
+            #[doc = "3/4 full FIFO"]
+            pub const THREEQUARTERS: Self = Self(0x02);
+            #[doc = "Full FIFO"]
+            pub const FULL: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Burst(pub u8);
+        impl Burst {
+            #[doc = "Single transfer"]
+            pub const SINGLE: Self = Self(0);
+            #[doc = "Incremental burst of 4 beats"]
+            pub const INCR4: Self = Self(0x01);
+            #[doc = "Incremental burst of 8 beats"]
+            pub const INCR8: Self = Self(0x02);
+            #[doc = "Incremental burst of 16 beats"]
+            pub const INCR16: Self = Self(0x03);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Dmdis(pub u8);
+        impl Dmdis {
+            #[doc = "Direct mode is enabled"]
+            pub const ENABLED: Self = Self(0);
+            #[doc = "Direct mode is disabled"]
+            pub const DISABLED: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Dir(pub u8);
+        impl Dir {
+            #[doc = "Peripheral-to-memory"]
+            pub const PERIPHERALTOMEMORY: Self = Self(0);
+            #[doc = "Memory-to-peripheral"]
+            pub const MEMORYTOPERIPHERAL: Self = Self(0x01);
+            #[doc = "Memory-to-memory"]
+            pub const MEMORYTOMEMORY: Self = Self(0x02);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Pincos(pub u8);
+        impl Pincos {
+            #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"]
+            pub const PSIZE: Self = Self(0);
+            #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"]
+            pub const FIXED4: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Size(pub u8);
+        impl Size {
+            #[doc = "Byte (8-bit)"]
+            pub const BITS8: Self = Self(0);
+            #[doc = "Half-word (16-bit)"]
+            pub const BITS16: Self = Self(0x01);
+            #[doc = "Word (32-bit)"]
+            pub const BITS32: Self = Self(0x02);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Ct(pub u8);
+        impl Ct {
+            #[doc = "The current target memory is Memory 0"]
+            pub const MEMORY0: Self = Self(0);
+            #[doc = "The current target memory is Memory 1"]
+            pub const MEMORY1: Self = Self(0x01);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Fs(pub u8);
+        impl Fs {
+            #[doc = "0 < fifo_level < 1/4"]
+            pub const QUARTER1: Self = Self(0);
+            #[doc = "1/4 <= fifo_level < 1/2"]
+            pub const QUARTER2: Self = Self(0x01);
+            #[doc = "1/2 <= fifo_level < 3/4"]
+            pub const QUARTER3: Self = Self(0x02);
+            #[doc = "3/4 <= fifo_level < full"]
+            pub const QUARTER4: Self = Self(0x03);
+            #[doc = "FIFO is empty"]
+            pub const EMPTY: Self = Self(0x04);
+            #[doc = "FIFO is full"]
+            pub const FULL: Self = Self(0x05);
+        }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Circ(pub u8);
+        impl Circ {
+            #[doc = "Circular mode disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Circular mode enabled"]
+            pub const ENABLED: Self = Self(0x01);
         }
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "Port configuration register (GPIOn_CRx)"]
+        #[doc = "stream x number of data register"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Ndtr(pub u32);
+        impl Ndtr {
+            #[doc = "Number of data items to transfer"]
+            pub const fn ndt(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "Number of data items to transfer"]
+            pub fn set_ndt(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Ndtr {
+            fn default() -> Ndtr {
+                Ndtr(0)
+            }
+        }
+        #[doc = "stream x configuration register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
         pub struct Cr(pub u32);
         impl Cr {
-            #[doc = "Port n mode bits"]
-            pub fn mode(&self, n: usize) -> super::vals::Mode {
-                assert!(n < 8usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::Mode(val as u8)
+            #[doc = "Stream enable / flag stream ready when read low"]
+            pub const fn en(&self) -> bool {
+                let val = (self.0 >> 0usize) & 0x01;
+                val != 0
             }
-            #[doc = "Port n mode bits"]
-            pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) {
-                assert!(n < 8usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
+            #[doc = "Stream enable / flag stream ready when read low"]
+            pub fn set_en(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "Port n configuration bits"]
-            pub fn cnf(&self, n: usize) -> super::vals::Cnf {
-                assert!(n < 8usize);
-                let offs = 2usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x03;
-                super::vals::Cnf(val as u8)
+            #[doc = "Direct mode error interrupt enable"]
+            pub const fn dmeie(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
+                val != 0
             }
-            #[doc = "Port n configuration bits"]
-            pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) {
-                assert!(n < 8usize);
-                let offs = 2usize + n * 4usize;
-                self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
+            #[doc = "Direct mode error interrupt enable"]
+            pub fn set_dmeie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            }
+            #[doc = "Transfer error interrupt enable"]
+            pub const fn teie(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Transfer error interrupt enable"]
+            pub fn set_teie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            }
+            #[doc = "Half transfer interrupt enable"]
+            pub const fn htie(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Half transfer interrupt enable"]
+            pub fn set_htie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            }
+            #[doc = "Transfer complete interrupt enable"]
+            pub const fn tcie(&self) -> bool {
+                let val = (self.0 >> 4usize) & 0x01;
+                val != 0
+            }
+            #[doc = "Transfer complete interrupt enable"]
+            pub fn set_tcie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
+            }
+            #[doc = "Peripheral flow controller"]
+            pub const fn pfctrl(&self) -> super::vals::Pfctrl {
+                let val = (self.0 >> 5usize) & 0x01;
+                super::vals::Pfctrl(val as u8)
+            }
+            #[doc = "Peripheral flow controller"]
+            pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
+            }
+            #[doc = "Data transfer direction"]
+            pub const fn dir(&self) -> super::vals::Dir {
+                let val = (self.0 >> 6usize) & 0x03;
+                super::vals::Dir(val as u8)
+            }
+            #[doc = "Data transfer direction"]
+            pub fn set_dir(&mut self, val: super::vals::Dir) {
+                self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize);
+            }
+            #[doc = "Circular mode"]
+            pub const fn circ(&self) -> super::vals::Circ {
+                let val = (self.0 >> 8usize) & 0x01;
+                super::vals::Circ(val as u8)
+            }
+            #[doc = "Circular mode"]
+            pub fn set_circ(&mut self, val: super::vals::Circ) {
+                self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
+            }
+            #[doc = "Peripheral increment mode"]
+            pub const fn pinc(&self) -> super::vals::Inc {
+                let val = (self.0 >> 9usize) & 0x01;
+                super::vals::Inc(val as u8)
+            }
+            #[doc = "Peripheral increment mode"]
+            pub fn set_pinc(&mut self, val: super::vals::Inc) {
+                self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
+            }
+            #[doc = "Memory increment mode"]
+            pub const fn minc(&self) -> super::vals::Inc {
+                let val = (self.0 >> 10usize) & 0x01;
+                super::vals::Inc(val as u8)
+            }
+            #[doc = "Memory increment mode"]
+            pub fn set_minc(&mut self, val: super::vals::Inc) {
+                self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
+            }
+            #[doc = "Peripheral data size"]
+            pub const fn psize(&self) -> super::vals::Size {
+                let val = (self.0 >> 11usize) & 0x03;
+                super::vals::Size(val as u8)
+            }
+            #[doc = "Peripheral data size"]
+            pub fn set_psize(&mut self, val: super::vals::Size) {
+                self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize);
+            }
+            #[doc = "Memory data size"]
+            pub const fn msize(&self) -> super::vals::Size {
+                let val = (self.0 >> 13usize) & 0x03;
+                super::vals::Size(val as u8)
+            }
+            #[doc = "Memory data size"]
+            pub fn set_msize(&mut self, val: super::vals::Size) {
+                self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize);
+            }
+            #[doc = "Peripheral increment offset size"]
+            pub const fn pincos(&self) -> super::vals::Pincos {
+                let val = (self.0 >> 15usize) & 0x01;
+                super::vals::Pincos(val as u8)
+            }
+            #[doc = "Peripheral increment offset size"]
+            pub fn set_pincos(&mut self, val: super::vals::Pincos) {
+                self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
+            }
+            #[doc = "Priority level"]
+            pub const fn pl(&self) -> super::vals::Pl {
+                let val = (self.0 >> 16usize) & 0x03;
+                super::vals::Pl(val as u8)
+            }
+            #[doc = "Priority level"]
+            pub fn set_pl(&mut self, val: super::vals::Pl) {
+                self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize);
+            }
+            #[doc = "Double buffer mode"]
+            pub const fn dbm(&self) -> super::vals::Dbm {
+                let val = (self.0 >> 18usize) & 0x01;
+                super::vals::Dbm(val as u8)
+            }
+            #[doc = "Double buffer mode"]
+            pub fn set_dbm(&mut self, val: super::vals::Dbm) {
+                self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
+            }
+            #[doc = "Current target (only in double buffer mode)"]
+            pub const fn ct(&self) -> super::vals::Ct {
+                let val = (self.0 >> 19usize) & 0x01;
+                super::vals::Ct(val as u8)
+            }
+            #[doc = "Current target (only in double buffer mode)"]
+            pub fn set_ct(&mut self, val: super::vals::Ct) {
+                self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
+            }
+            #[doc = "Peripheral burst transfer configuration"]
+            pub const fn pburst(&self) -> super::vals::Burst {
+                let val = (self.0 >> 21usize) & 0x03;
+                super::vals::Burst(val as u8)
+            }
+            #[doc = "Peripheral burst transfer configuration"]
+            pub fn set_pburst(&mut self, val: super::vals::Burst) {
+                self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize);
+            }
+            #[doc = "Memory burst transfer configuration"]
+            pub const fn mburst(&self) -> super::vals::Burst {
+                let val = (self.0 >> 23usize) & 0x03;
+                super::vals::Burst(val as u8)
+            }
+            #[doc = "Memory burst transfer configuration"]
+            pub fn set_mburst(&mut self, val: super::vals::Burst) {
+                self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize);
+            }
+            #[doc = "Channel selection"]
+            pub const fn chsel(&self) -> u8 {
+                let val = (self.0 >> 25usize) & 0x0f;
+                val as u8
+            }
+            #[doc = "Channel selection"]
+            pub fn set_chsel(&mut self, val: u8) {
+                self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize);
             }
         }
         impl Default for Cr {
@@ -4954,564 +4937,581 @@ pub mod gpio_v1 {
                 Cr(0)
             }
         }
-        #[doc = "Port output data register (GPIOn_ODR)"]
+        #[doc = "stream x FIFO control register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Odr(pub u32);
-        impl Odr {
-            #[doc = "Port output data"]
-            pub fn odr(&self, n: usize) -> super::vals::Odr {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                let val = (self.0 >> offs) & 0x01;
-                super::vals::Odr(val as u8)
+        pub struct Fcr(pub u32);
+        impl Fcr {
+            #[doc = "FIFO threshold selection"]
+            pub const fn fth(&self) -> super::vals::Fth {
+                let val = (self.0 >> 0usize) & 0x03;
+                super::vals::Fth(val as u8)
             }
-            #[doc = "Port output data"]
-            pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            #[doc = "FIFO threshold selection"]
+            pub fn set_fth(&mut self, val: super::vals::Fth) {
+                self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
+            }
+            #[doc = "Direct mode disable"]
+            pub const fn dmdis(&self) -> super::vals::Dmdis {
+                let val = (self.0 >> 2usize) & 0x01;
+                super::vals::Dmdis(val as u8)
+            }
+            #[doc = "Direct mode disable"]
+            pub fn set_dmdis(&mut self, val: super::vals::Dmdis) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
+            }
+            #[doc = "FIFO status"]
+            pub const fn fs(&self) -> super::vals::Fs {
+                let val = (self.0 >> 3usize) & 0x07;
+                super::vals::Fs(val as u8)
+            }
+            #[doc = "FIFO status"]
+            pub fn set_fs(&mut self, val: super::vals::Fs) {
+                self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
+            }
+            #[doc = "FIFO error interrupt enable"]
+            pub const fn feie(&self) -> bool {
+                let val = (self.0 >> 7usize) & 0x01;
+                val != 0
+            }
+            #[doc = "FIFO error interrupt enable"]
+            pub fn set_feie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
             }
         }
-        impl Default for Odr {
-            fn default() -> Odr {
-                Odr(0)
+        impl Default for Fcr {
+            fn default() -> Fcr {
+                Fcr(0)
             }
         }
-        #[doc = "Port configuration lock register"]
+        #[doc = "low interrupt flag clear register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Lckr(pub u32);
-        impl Lckr {
-            #[doc = "Port A Lock bit"]
-            pub fn lck(&self, n: usize) -> super::vals::Lck {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
+        pub struct Ifcr(pub u32);
+        impl Ifcr {
+            #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"]
+            pub fn cfeif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
                 let val = (self.0 >> offs) & 0x01;
-                super::vals::Lck(val as u8)
+                val != 0
             }
-            #[doc = "Port A Lock bit"]
-            pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"]
+            pub fn set_cfeif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Lock key"]
-            pub const fn lckk(&self) -> super::vals::Lckk {
-                let val = (self.0 >> 16usize) & 0x01;
-                super::vals::Lckk(val as u8)
+            #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"]
+            pub fn cdmeif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
             }
-            #[doc = "Lock key"]
-            pub fn set_lckk(&mut self, val: super::vals::Lckk) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
+            #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"]
+            pub fn set_cdmeif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-        }
-        impl Default for Lckr {
-            fn default() -> Lckr {
-                Lckr(0)
+            #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"]
+            pub fn cteif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
             }
-        }
-        #[doc = "Port bit reset register (GPIOn_BRR)"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Brr(pub u32);
-        impl Brr {
-            #[doc = "Reset bit"]
-            pub fn br(&self, n: usize) -> bool {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
+            #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"]
+            pub fn set_cteif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"]
+            pub fn chtif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Reset bit"]
-            pub fn set_br(&mut self, n: usize, val: bool) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
+            #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"]
+            pub fn set_chtif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"]
+            pub fn ctcif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"]
+            pub fn set_ctcif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for Brr {
-            fn default() -> Brr {
-                Brr(0)
+        impl Default for Ifcr {
+            fn default() -> Ifcr {
+                Ifcr(0)
             }
         }
-        #[doc = "Port input data register (GPIOn_IDR)"]
+        #[doc = "low interrupt status register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Idr(pub u32);
-        impl Idr {
-            #[doc = "Port input data"]
-            pub fn idr(&self, n: usize) -> super::vals::Idr {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
+        pub struct Isr(pub u32);
+        impl Isr {
+            #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
+            pub fn feif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
                 let val = (self.0 >> offs) & 0x01;
-                super::vals::Idr(val as u8)
+                val != 0
             }
-            #[doc = "Port input data"]
-            pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
-                self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
+            #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
+            pub fn set_feif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-        }
-        impl Default for Idr {
-            fn default() -> Idr {
-                Idr(0)
+            #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
+            pub fn dmeif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
             }
-        }
-        #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Bsrr(pub u32);
-        impl Bsrr {
-            #[doc = "Set bit"]
-            pub fn bs(&self, n: usize) -> bool {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
+            #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
+            pub fn set_dmeif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
+            pub fn teif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Set bit"]
-            pub fn set_bs(&mut self, n: usize, val: bool) {
-                assert!(n < 16usize);
-                let offs = 0usize + n * 1usize;
+            #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
+            pub fn set_teif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "Reset bit"]
-            pub fn br(&self, n: usize) -> bool {
-                assert!(n < 16usize);
-                let offs = 16usize + n * 1usize;
+            #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
+            pub fn htif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "Reset bit"]
-            pub fn set_br(&mut self, n: usize, val: bool) {
-                assert!(n < 16usize);
-                let offs = 16usize + n * 1usize;
+            #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
+            pub fn set_htif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-        }
-        impl Default for Bsrr {
-            fn default() -> Bsrr {
-                Bsrr(0)
+            #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
+            pub fn tcif(&self, n: usize) -> bool {
+                assert!(n < 4usize);
+                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
+            }
+            #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
+            pub fn set_tcif(&mut self, n: usize, val: bool) {
+                assert!(n < 4usize);
+                let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-    }
-    pub mod vals {
-        use crate::generic::*;
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Lck(pub u8);
-        impl Lck {
-            #[doc = "Port configuration not locked"]
-            pub const UNLOCKED: Self = Self(0);
-            #[doc = "Port configuration locked"]
-            pub const LOCKED: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Cnf(pub u8);
-        impl Cnf {
-            #[doc = "Analog mode / Push-Pull mode"]
-            pub const PUSHPULL: Self = Self(0);
-            #[doc = "Floating input (reset state) / Open Drain-Mode"]
-            pub const OPENDRAIN: Self = Self(0x01);
-            #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"]
-            pub const ALTPUSHPULL: Self = Self(0x02);
-            #[doc = "Alternate Function Open-Drain Mode"]
-            pub const ALTOPENDRAIN: Self = Self(0x03);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Odr(pub u8);
-        impl Odr {
-            #[doc = "Set output to logic low"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Set output to logic high"]
-            pub const HIGH: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Mode(pub u8);
-        impl Mode {
-            #[doc = "Input mode (reset state)"]
-            pub const INPUT: Self = Self(0);
-            #[doc = "Output mode 10 MHz"]
-            pub const OUTPUT: Self = Self(0x01);
-            #[doc = "Output mode 2 MHz"]
-            pub const OUTPUT2: Self = Self(0x02);
-            #[doc = "Output mode 50 MHz"]
-            pub const OUTPUT50: Self = Self(0x03);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Lckk(pub u8);
-        impl Lckk {
-            #[doc = "Port configuration lock key not active"]
-            pub const NOTACTIVE: Self = Self(0);
-            #[doc = "Port configuration lock key active"]
-            pub const ACTIVE: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Brw(pub u8);
-        impl Brw {
-            #[doc = "No action on the corresponding ODx bit"]
-            pub const NOACTION: Self = Self(0);
-            #[doc = "Reset the ODx bit"]
-            pub const RESET: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Idr(pub u8);
-        impl Idr {
-            #[doc = "Input is logic low"]
-            pub const LOW: Self = Self(0);
-            #[doc = "Input is logic high"]
-            pub const HIGH: Self = Self(0x01);
-        }
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
-        pub struct Bsw(pub u8);
-        impl Bsw {
-            #[doc = "No action on the corresponding ODx bit"]
-            pub const NOACTION: Self = Self(0);
-            #[doc = "Sets the corresponding ODRx bit"]
-            pub const SET: Self = Self(0x01);
+        impl Default for Isr {
+            fn default() -> Isr {
+                Isr(0)
+            }
         }
     }
 }
-pub mod syscfg_l4 {
+pub mod dma_v1 {
     use crate::generic::*;
-    #[doc = "System configuration controller"]
+    #[doc = "DMA controller"]
     #[derive(Copy, Clone)]
-    pub struct Syscfg(pub *mut u8);
-    unsafe impl Send for Syscfg {}
-    unsafe impl Sync for Syscfg {}
-    impl Syscfg {
-        #[doc = "memory remap register"]
-        pub fn memrmp(self) -> Reg<regs::Memrmp, RW> {
+    pub struct Dma(pub *mut u8);
+    unsafe impl Send for Dma {}
+    unsafe impl Sync for Dma {}
+    impl Dma {
+        #[doc = "DMA interrupt status register (DMA_ISR)"]
+        pub fn isr(self) -> Reg<regs::Isr, R> {
             unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
-        #[doc = "configuration register 1"]
-        pub fn cfgr1(self) -> Reg<regs::Cfgr1, RW> {
+        #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
+        pub fn ifcr(self) -> Reg<regs::Ifcr, W> {
             unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-        #[doc = "external interrupt configuration register 1"]
-        pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
-            assert!(n < 4usize);
-            unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
+        #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
+        pub fn ch(self, n: usize) -> Ch {
+            assert!(n < 7usize);
+            unsafe { Ch(self.0.add(8usize + n * 20usize)) }
         }
-        #[doc = "SCSR"]
-        pub fn scsr(self) -> Reg<regs::Scsr, RW> {
-            unsafe { Reg::from_ptr(self.0.add(24usize)) }
+    }
+    #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
+    #[derive(Copy, Clone)]
+    pub struct Ch(pub *mut u8);
+    unsafe impl Send for Ch {}
+    unsafe impl Sync for Ch {}
+    impl Ch {
+        #[doc = "DMA channel configuration register (DMA_CCR)"]
+        pub fn cr(self) -> Reg<regs::Cr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(0usize)) }
         }
-        #[doc = "CFGR2"]
-        pub fn cfgr2(self) -> Reg<regs::Cfgr2, RW> {
-            unsafe { Reg::from_ptr(self.0.add(28usize)) }
+        #[doc = "DMA channel 1 number of data register"]
+        pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
+            unsafe { Reg::from_ptr(self.0.add(4usize)) }
         }
-        #[doc = "SWPR"]
-        pub fn swpr(self) -> Reg<regs::Swpr, W> {
-            unsafe { Reg::from_ptr(self.0.add(32usize)) }
+        #[doc = "DMA channel 1 peripheral address register"]
+        pub fn par(self) -> Reg<u32, RW> {
+            unsafe { Reg::from_ptr(self.0.add(8usize)) }
         }
-        #[doc = "SKR"]
-        pub fn skr(self) -> Reg<regs::Skr, W> {
-            unsafe { Reg::from_ptr(self.0.add(36usize)) }
+        #[doc = "DMA channel 1 memory address register"]
+        pub fn mar(self) -> Reg<u32, RW> {
+            unsafe { Reg::from_ptr(self.0.add(12usize)) }
         }
     }
     pub mod regs {
         use crate::generic::*;
-        #[doc = "configuration register 1"]
+        #[doc = "DMA channel 1 number of data register"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cfgr1(pub u32);
-        impl Cfgr1 {
-            #[doc = "Firewall disable"]
-            pub const fn fwdis(&self) -> bool {
+        pub struct Ndtr(pub u32);
+        impl Ndtr {
+            #[doc = "Number of data to transfer"]
+            pub const fn ndt(&self) -> u16 {
+                let val = (self.0 >> 0usize) & 0xffff;
+                val as u16
+            }
+            #[doc = "Number of data to transfer"]
+            pub fn set_ndt(&mut self, val: u16) {
+                self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
+            }
+        }
+        impl Default for Ndtr {
+            fn default() -> Ndtr {
+                Ndtr(0)
+            }
+        }
+        #[doc = "DMA channel configuration register (DMA_CCR)"]
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq)]
+        pub struct Cr(pub u32);
+        impl Cr {
+            #[doc = "Channel enable"]
+            pub const fn en(&self) -> bool {
                 let val = (self.0 >> 0usize) & 0x01;
                 val != 0
             }
-            #[doc = "Firewall disable"]
-            pub fn set_fwdis(&mut self, val: bool) {
+            #[doc = "Channel enable"]
+            pub fn set_en(&mut self, val: bool) {
                 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
             }
-            #[doc = "I/O analog switch voltage booster enable"]
-            pub const fn boosten(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
+            #[doc = "Transfer complete interrupt enable"]
+            pub const fn tcie(&self) -> bool {
+                let val = (self.0 >> 1usize) & 0x01;
                 val != 0
             }
-            #[doc = "I/O analog switch voltage booster enable"]
-            pub fn set_boosten(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            #[doc = "Transfer complete interrupt enable"]
+            pub fn set_tcie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
-            pub const fn i2c_pb6_fmp(&self) -> bool {
-                let val = (self.0 >> 16usize) & 0x01;
+            #[doc = "Half Transfer interrupt enable"]
+            pub const fn htie(&self) -> bool {
+                let val = (self.0 >> 2usize) & 0x01;
                 val != 0
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
-            pub fn set_i2c_pb6_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
+            #[doc = "Half Transfer interrupt enable"]
+            pub fn set_htie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
-            pub const fn i2c_pb7_fmp(&self) -> bool {
-                let val = (self.0 >> 17usize) & 0x01;
+            #[doc = "Transfer error interrupt enable"]
+            pub const fn teie(&self) -> bool {
+                let val = (self.0 >> 3usize) & 0x01;
                 val != 0
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
-            pub fn set_i2c_pb7_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
+            #[doc = "Transfer error interrupt enable"]
+            pub fn set_teie(&mut self, val: bool) {
+                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
-            pub const fn i2c_pb8_fmp(&self) -> bool {
-                let val = (self.0 >> 18usize) & 0x01;
-                val != 0
+            #[doc = "Data transfer direction"]
+            pub const fn dir(&self) -> super::vals::Dir {
+                let val = (self.0 >> 4usize) & 0x01;
+                super::vals::Dir(val as u8)
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
-            pub fn set_i2c_pb8_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
+            #[doc = "Data transfer direction"]
+            pub fn set_dir(&mut self, val: super::vals::Dir) {
+                self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
-            pub const fn i2c_pb9_fmp(&self) -> bool {
-                let val = (self.0 >> 19usize) & 0x01;
-                val != 0
+            #[doc = "Circular mode"]
+            pub const fn circ(&self) -> super::vals::Circ {
+                let val = (self.0 >> 5usize) & 0x01;
+                super::vals::Circ(val as u8)
             }
-            #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
-            pub fn set_i2c_pb9_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
+            #[doc = "Circular mode"]
+            pub fn set_circ(&mut self, val: super::vals::Circ) {
+                self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
             }
-            #[doc = "I2C1 Fast-mode Plus driving capability activation"]
-            pub const fn i2c1_fmp(&self) -> bool {
-                let val = (self.0 >> 20usize) & 0x01;
-                val != 0
+            #[doc = "Peripheral increment mode"]
+            pub const fn pinc(&self) -> super::vals::Inc {
+                let val = (self.0 >> 6usize) & 0x01;
+                super::vals::Inc(val as u8)
             }
-            #[doc = "I2C1 Fast-mode Plus driving capability activation"]
-            pub fn set_i2c1_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
+            #[doc = "Peripheral increment mode"]
+            pub fn set_pinc(&mut self, val: super::vals::Inc) {
+                self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
             }
-            #[doc = "I2C2 Fast-mode Plus driving capability activation"]
-            pub const fn i2c2_fmp(&self) -> bool {
-                let val = (self.0 >> 21usize) & 0x01;
-                val != 0
+            #[doc = "Memory increment mode"]
+            pub const fn minc(&self) -> super::vals::Inc {
+                let val = (self.0 >> 7usize) & 0x01;
+                super::vals::Inc(val as u8)
             }
-            #[doc = "I2C2 Fast-mode Plus driving capability activation"]
-            pub fn set_i2c2_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
+            #[doc = "Memory increment mode"]
+            pub fn set_minc(&mut self, val: super::vals::Inc) {
+                self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
             }
-            #[doc = "I2C3 Fast-mode Plus driving capability activation"]
-            pub const fn i2c3_fmp(&self) -> bool {
-                let val = (self.0 >> 22usize) & 0x01;
-                val != 0
+            #[doc = "Peripheral size"]
+            pub const fn psize(&self) -> super::vals::Size {
+                let val = (self.0 >> 8usize) & 0x03;
+                super::vals::Size(val as u8)
             }
-            #[doc = "I2C3 Fast-mode Plus driving capability activation"]
-            pub fn set_i2c3_fmp(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
+            #[doc = "Peripheral size"]
+            pub fn set_psize(&mut self, val: super::vals::Size) {
+                self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
             }
-            #[doc = "Floating Point Unit interrupts enable bits"]
-            pub const fn fpu_ie(&self) -> u8 {
-                let val = (self.0 >> 26usize) & 0x3f;
-                val as u8
+            #[doc = "Memory size"]
+            pub const fn msize(&self) -> super::vals::Size {
+                let val = (self.0 >> 10usize) & 0x03;
+                super::vals::Size(val as u8)
             }
-            #[doc = "Floating Point Unit interrupts enable bits"]
-            pub fn set_fpu_ie(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize);
+            #[doc = "Memory size"]
+            pub fn set_msize(&mut self, val: super::vals::Size) {
+                self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize);
+            }
+            #[doc = "Channel Priority level"]
+            pub const fn pl(&self) -> super::vals::Pl {
+                let val = (self.0 >> 12usize) & 0x03;
+                super::vals::Pl(val as u8)
+            }
+            #[doc = "Channel Priority level"]
+            pub fn set_pl(&mut self, val: super::vals::Pl) {
+                self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
+            }
+            #[doc = "Memory to memory mode"]
+            pub const fn mem2mem(&self) -> super::vals::Memmem {
+                let val = (self.0 >> 14usize) & 0x01;
+                super::vals::Memmem(val as u8)
+            }
+            #[doc = "Memory to memory mode"]
+            pub fn set_mem2mem(&mut self, val: super::vals::Memmem) {
+                self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
             }
         }
-        impl Default for Cfgr1 {
-            fn default() -> Cfgr1 {
-                Cfgr1(0)
+        impl Default for Cr {
+            fn default() -> Cr {
+                Cr(0)
             }
         }
-        #[doc = "CFGR2"]
+        #[doc = "DMA interrupt status register (DMA_ISR)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Cfgr2(pub u32);
-        impl Cfgr2 {
-            #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
-            pub const fn cll(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
-            pub fn set_cll(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
-            }
-            #[doc = "SRAM2 parity lock bit"]
-            pub const fn spl(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
+        pub struct Isr(pub u32);
+        impl Isr {
+            #[doc = "Channel 1 Global interrupt flag"]
+            pub fn gif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 0usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "SRAM2 parity lock bit"]
-            pub fn set_spl(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            #[doc = "Channel 1 Global interrupt flag"]
+            pub fn set_gif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 0usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "PVD lock enable bit"]
-            pub const fn pvdl(&self) -> bool {
-                let val = (self.0 >> 2usize) & 0x01;
+            #[doc = "Channel 1 Transfer Complete flag"]
+            pub fn tcif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 1usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "PVD lock enable bit"]
-            pub fn set_pvdl(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
+            #[doc = "Channel 1 Transfer Complete flag"]
+            pub fn set_tcif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 1usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "ECC Lock"]
-            pub const fn eccl(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
+            #[doc = "Channel 1 Half Transfer Complete flag"]
+            pub fn htif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 2usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "ECC Lock"]
-            pub fn set_eccl(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
+            #[doc = "Channel 1 Half Transfer Complete flag"]
+            pub fn set_htif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 2usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "SRAM2 parity error flag"]
-            pub const fn spf(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
+            #[doc = "Channel 1 Transfer Error flag"]
+            pub fn teif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 3usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "SRAM2 parity error flag"]
-            pub fn set_spf(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
+            #[doc = "Channel 1 Transfer Error flag"]
+            pub fn set_teif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 3usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for Cfgr2 {
-            fn default() -> Cfgr2 {
-                Cfgr2(0)
+        impl Default for Isr {
+            fn default() -> Isr {
+                Isr(0)
             }
         }
-        #[doc = "SWPR"]
+        #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
         #[repr(transparent)]
         #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Swpr(pub u32);
-        impl Swpr {
-            #[doc = "SRAWM2 write protection."]
-            pub fn pwp(&self, n: usize) -> bool {
-                assert!(n < 32usize);
-                let offs = 0usize + n * 1usize;
+        pub struct Ifcr(pub u32);
+        impl Ifcr {
+            #[doc = "Channel 1 Global interrupt clear"]
+            pub fn cgif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 0usize + n * 4usize;
                 let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "SRAWM2 write protection."]
-            pub fn set_pwp(&mut self, n: usize, val: bool) {
-                assert!(n < 32usize);
-                let offs = 0usize + n * 1usize;
+            #[doc = "Channel 1 Global interrupt clear"]
+            pub fn set_cgif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 0usize + n * 4usize;
                 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-        }
-        impl Default for Swpr {
-            fn default() -> Swpr {
-                Swpr(0)
+            #[doc = "Channel 1 Transfer Complete clear"]
+            pub fn ctcif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 1usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
+                val != 0
             }
-        }
-        #[doc = "SCSR"]
-        #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Scsr(pub u32);
-        impl Scsr {
-            #[doc = "SRAM2 Erase"]
-            pub const fn sram2er(&self) -> bool {
-                let val = (self.0 >> 0usize) & 0x01;
+            #[doc = "Channel 1 Transfer Complete clear"]
+            pub fn set_ctcif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 1usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
+            }
+            #[doc = "Channel 1 Half Transfer clear"]
+            pub fn chtif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 2usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "SRAM2 Erase"]
-            pub fn set_sram2er(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
+            #[doc = "Channel 1 Half Transfer clear"]
+            pub fn set_chtif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 2usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
-            #[doc = "SRAM2 busy by erase operation"]
-            pub const fn sram2bsy(&self) -> bool {
-                let val = (self.0 >> 1usize) & 0x01;
+            #[doc = "Channel 1 Transfer Error clear"]
+            pub fn cteif(&self, n: usize) -> bool {
+                assert!(n < 7usize);
+                let offs = 3usize + n * 4usize;
+                let val = (self.0 >> offs) & 0x01;
                 val != 0
             }
-            #[doc = "SRAM2 busy by erase operation"]
-            pub fn set_sram2bsy(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
+            #[doc = "Channel 1 Transfer Error clear"]
+            pub fn set_cteif(&mut self, n: usize, val: bool) {
+                assert!(n < 7usize);
+                let offs = 3usize + n * 4usize;
+                self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
             }
         }
-        impl Default for Scsr {
-            fn default() -> Scsr {
-                Scsr(0)
+        impl Default for Ifcr {
+            fn default() -> Ifcr {
+                Ifcr(0)
             }
         }
-        #[doc = "external interrupt configuration register 4"]
+    }
+    pub mod vals {
+        use crate::generic::*;
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Exticr(pub u32);
-        impl Exticr {
-            #[doc = "EXTI12 configuration bits"]
-            pub fn exti(&self, n: usize) -> u8 {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                let val = (self.0 >> offs) & 0x0f;
-                val as u8
-            }
-            #[doc = "EXTI12 configuration bits"]
-            pub fn set_exti(&mut self, n: usize, val: u8) {
-                assert!(n < 4usize);
-                let offs = 0usize + n * 4usize;
-                self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
-            }
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Dir(pub u8);
+        impl Dir {
+            #[doc = "Read from peripheral"]
+            pub const FROMPERIPHERAL: Self = Self(0);
+            #[doc = "Read from memory"]
+            pub const FROMMEMORY: Self = Self(0x01);
         }
-        impl Default for Exticr {
-            fn default() -> Exticr {
-                Exticr(0)
-            }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Inc(pub u8);
+        impl Inc {
+            #[doc = "Increment mode disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Increment mode enabled"]
+            pub const ENABLED: Self = Self(0x01);
         }
-        #[doc = "memory remap register"]
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Memrmp(pub u32);
-        impl Memrmp {
-            #[doc = "Memory mapping selection"]
-            pub const fn mem_mode(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0x07;
-                val as u8
-            }
-            #[doc = "Memory mapping selection"]
-            pub fn set_mem_mode(&mut self, val: u8) {
-                self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
-            }
-            #[doc = "QUADSPI memory mapping swap"]
-            pub const fn qfs(&self) -> bool {
-                let val = (self.0 >> 3usize) & 0x01;
-                val != 0
-            }
-            #[doc = "QUADSPI memory mapping swap"]
-            pub fn set_qfs(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
-            }
-            #[doc = "Flash Bank mode selection"]
-            pub const fn fb_mode(&self) -> bool {
-                let val = (self.0 >> 8usize) & 0x01;
-                val != 0
-            }
-            #[doc = "Flash Bank mode selection"]
-            pub fn set_fb_mode(&mut self, val: bool) {
-                self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
-            }
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Memmem(pub u8);
+        impl Memmem {
+            #[doc = "Memory to memory mode disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Memory to memory mode enabled"]
+            pub const ENABLED: Self = Self(0x01);
         }
-        impl Default for Memrmp {
-            fn default() -> Memrmp {
-                Memrmp(0)
-            }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Size(pub u8);
+        impl Size {
+            #[doc = "8-bit size"]
+            pub const BITS8: Self = Self(0);
+            #[doc = "16-bit size"]
+            pub const BITS16: Self = Self(0x01);
+            #[doc = "32-bit size"]
+            pub const BITS32: Self = Self(0x02);
         }
-        #[doc = "SKR"]
         #[repr(transparent)]
-        #[derive(Copy, Clone, Eq, PartialEq)]
-        pub struct Skr(pub u32);
-        impl Skr {
-            #[doc = "SRAM2 write protection key for software erase"]
-            pub const fn key(&self) -> u8 {
-                let val = (self.0 >> 0usize) & 0xff;
-                val as u8
-            }
-            #[doc = "SRAM2 write protection key for software erase"]
-            pub fn set_key(&mut self, val: u8) {
-                self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
-            }
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Pl(pub u8);
+        impl Pl {
+            #[doc = "Low priority"]
+            pub const LOW: Self = Self(0);
+            #[doc = "Medium priority"]
+            pub const MEDIUM: Self = Self(0x01);
+            #[doc = "High priority"]
+            pub const HIGH: Self = Self(0x02);
+            #[doc = "Very high priority"]
+            pub const VERYHIGH: Self = Self(0x03);
         }
-        impl Default for Skr {
-            fn default() -> Skr {
-                Skr(0)
-            }
+        #[repr(transparent)]
+        #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+        pub struct Circ(pub u8);
+        impl Circ {
+            #[doc = "Circular buffer disabled"]
+            pub const DISABLED: Self = Self(0);
+            #[doc = "Circular buffer enabled"]
+            pub const ENABLED: Self = Self(0x01);
         }
     }
 }
diff --git a/embassy-stm32/src/pac/stm32f405oe.rs b/embassy-stm32/src/pac/stm32f405oe.rs
index cd1b5efdb..55def9b77 100644
--- a/embassy-stm32/src/pac/stm32f405oe.rs
+++ b/embassy-stm32/src/pac/stm32f405oe.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f405og.rs b/embassy-stm32/src/pac/stm32f405og.rs
index cd1b5efdb..55def9b77 100644
--- a/embassy-stm32/src/pac/stm32f405og.rs
+++ b/embassy-stm32/src/pac/stm32f405og.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f405rg.rs b/embassy-stm32/src/pac/stm32f405rg.rs
index cd1b5efdb..55def9b77 100644
--- a/embassy-stm32/src/pac/stm32f405rg.rs
+++ b/embassy-stm32/src/pac/stm32f405rg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f405vg.rs b/embassy-stm32/src/pac/stm32f405vg.rs
index cd1b5efdb..55def9b77 100644
--- a/embassy-stm32/src/pac/stm32f405vg.rs
+++ b/embassy-stm32/src/pac/stm32f405vg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f405zg.rs b/embassy-stm32/src/pac/stm32f405zg.rs
index cd1b5efdb..55def9b77 100644
--- a/embassy-stm32/src/pac/stm32f405zg.rs
+++ b/embassy-stm32/src/pac/stm32f405zg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f407ie.rs b/embassy-stm32/src/pac/stm32f407ie.rs
index cd9ac846d..d54d54fe8 100644
--- a/embassy-stm32/src/pac/stm32f407ie.rs
+++ b/embassy-stm32/src/pac/stm32f407ie.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f407ig.rs b/embassy-stm32/src/pac/stm32f407ig.rs
index cd9ac846d..d54d54fe8 100644
--- a/embassy-stm32/src/pac/stm32f407ig.rs
+++ b/embassy-stm32/src/pac/stm32f407ig.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f407ve.rs b/embassy-stm32/src/pac/stm32f407ve.rs
index cd9ac846d..d54d54fe8 100644
--- a/embassy-stm32/src/pac/stm32f407ve.rs
+++ b/embassy-stm32/src/pac/stm32f407ve.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f407vg.rs b/embassy-stm32/src/pac/stm32f407vg.rs
index cd9ac846d..d54d54fe8 100644
--- a/embassy-stm32/src/pac/stm32f407vg.rs
+++ b/embassy-stm32/src/pac/stm32f407vg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f407ze.rs b/embassy-stm32/src/pac/stm32f407ze.rs
index cd9ac846d..d54d54fe8 100644
--- a/embassy-stm32/src/pac/stm32f407ze.rs
+++ b/embassy-stm32/src/pac/stm32f407ze.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f407zg.rs b/embassy-stm32/src/pac/stm32f407zg.rs
index cd9ac846d..d54d54fe8 100644
--- a/embassy-stm32/src/pac/stm32f407zg.rs
+++ b/embassy-stm32/src/pac/stm32f407zg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f410c8.rs b/embassy-stm32/src/pac/stm32f410c8.rs
index a5c8a6b64..c5eb48a7f 100644
--- a/embassy-stm32/src/pac/stm32f410c8.rs
+++ b/embassy-stm32/src/pac/stm32f410c8.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f410cb.rs b/embassy-stm32/src/pac/stm32f410cb.rs
index a5c8a6b64..c5eb48a7f 100644
--- a/embassy-stm32/src/pac/stm32f410cb.rs
+++ b/embassy-stm32/src/pac/stm32f410cb.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f410r8.rs b/embassy-stm32/src/pac/stm32f410r8.rs
index a5c8a6b64..c5eb48a7f 100644
--- a/embassy-stm32/src/pac/stm32f410r8.rs
+++ b/embassy-stm32/src/pac/stm32f410r8.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f410rb.rs b/embassy-stm32/src/pac/stm32f410rb.rs
index a5c8a6b64..c5eb48a7f 100644
--- a/embassy-stm32/src/pac/stm32f410rb.rs
+++ b/embassy-stm32/src/pac/stm32f410rb.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f410t8.rs b/embassy-stm32/src/pac/stm32f410t8.rs
index 0b82a79c7..1eb28b9fc 100644
--- a/embassy-stm32/src/pac/stm32f410t8.rs
+++ b/embassy-stm32/src/pac/stm32f410t8.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f410tb.rs b/embassy-stm32/src/pac/stm32f410tb.rs
index 0b82a79c7..1eb28b9fc 100644
--- a/embassy-stm32/src/pac/stm32f410tb.rs
+++ b/embassy-stm32/src/pac/stm32f410tb.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f412ce.rs b/embassy-stm32/src/pac/stm32f412ce.rs
index 71c50ac96..0684b55da 100644
--- a/embassy-stm32/src/pac/stm32f412ce.rs
+++ b/embassy-stm32/src/pac/stm32f412ce.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f412cg.rs b/embassy-stm32/src/pac/stm32f412cg.rs
index 71c50ac96..0684b55da 100644
--- a/embassy-stm32/src/pac/stm32f412cg.rs
+++ b/embassy-stm32/src/pac/stm32f412cg.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f412re.rs b/embassy-stm32/src/pac/stm32f412re.rs
index 54ae3a02b..1c1d5221d 100644
--- a/embassy-stm32/src/pac/stm32f412re.rs
+++ b/embassy-stm32/src/pac/stm32f412re.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f412rg.rs b/embassy-stm32/src/pac/stm32f412rg.rs
index 54ae3a02b..1c1d5221d 100644
--- a/embassy-stm32/src/pac/stm32f412rg.rs
+++ b/embassy-stm32/src/pac/stm32f412rg.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f412ve.rs b/embassy-stm32/src/pac/stm32f412ve.rs
index d6e4e116a..b45a90fad 100644
--- a/embassy-stm32/src/pac/stm32f412ve.rs
+++ b/embassy-stm32/src/pac/stm32f412ve.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f412vg.rs b/embassy-stm32/src/pac/stm32f412vg.rs
index d6e4e116a..b45a90fad 100644
--- a/embassy-stm32/src/pac/stm32f412vg.rs
+++ b/embassy-stm32/src/pac/stm32f412vg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f412ze.rs b/embassy-stm32/src/pac/stm32f412ze.rs
index d6e4e116a..b45a90fad 100644
--- a/embassy-stm32/src/pac/stm32f412ze.rs
+++ b/embassy-stm32/src/pac/stm32f412ze.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f412zg.rs b/embassy-stm32/src/pac/stm32f412zg.rs
index d6e4e116a..b45a90fad 100644
--- a/embassy-stm32/src/pac/stm32f412zg.rs
+++ b/embassy-stm32/src/pac/stm32f412zg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f413cg.rs b/embassy-stm32/src/pac/stm32f413cg.rs
index fe503b506..3ac805c97 100644
--- a/embassy-stm32/src/pac/stm32f413cg.rs
+++ b/embassy-stm32/src/pac/stm32f413cg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f413ch.rs b/embassy-stm32/src/pac/stm32f413ch.rs
index fe503b506..3ac805c97 100644
--- a/embassy-stm32/src/pac/stm32f413ch.rs
+++ b/embassy-stm32/src/pac/stm32f413ch.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f413mg.rs b/embassy-stm32/src/pac/stm32f413mg.rs
index 81fe90c18..d841d79f5 100644
--- a/embassy-stm32/src/pac/stm32f413mg.rs
+++ b/embassy-stm32/src/pac/stm32f413mg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f413mh.rs b/embassy-stm32/src/pac/stm32f413mh.rs
index 81fe90c18..d841d79f5 100644
--- a/embassy-stm32/src/pac/stm32f413mh.rs
+++ b/embassy-stm32/src/pac/stm32f413mh.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f413rg.rs b/embassy-stm32/src/pac/stm32f413rg.rs
index 81fe90c18..d841d79f5 100644
--- a/embassy-stm32/src/pac/stm32f413rg.rs
+++ b/embassy-stm32/src/pac/stm32f413rg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f413rh.rs b/embassy-stm32/src/pac/stm32f413rh.rs
index 81fe90c18..d841d79f5 100644
--- a/embassy-stm32/src/pac/stm32f413rh.rs
+++ b/embassy-stm32/src/pac/stm32f413rh.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f413vg.rs b/embassy-stm32/src/pac/stm32f413vg.rs
index 81fe90c18..d841d79f5 100644
--- a/embassy-stm32/src/pac/stm32f413vg.rs
+++ b/embassy-stm32/src/pac/stm32f413vg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f413vh.rs b/embassy-stm32/src/pac/stm32f413vh.rs
index 81fe90c18..d841d79f5 100644
--- a/embassy-stm32/src/pac/stm32f413vh.rs
+++ b/embassy-stm32/src/pac/stm32f413vh.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f413zg.rs b/embassy-stm32/src/pac/stm32f413zg.rs
index 81fe90c18..d841d79f5 100644
--- a/embassy-stm32/src/pac/stm32f413zg.rs
+++ b/embassy-stm32/src/pac/stm32f413zg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f413zh.rs b/embassy-stm32/src/pac/stm32f413zh.rs
index 81fe90c18..d841d79f5 100644
--- a/embassy-stm32/src/pac/stm32f413zh.rs
+++ b/embassy-stm32/src/pac/stm32f413zh.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f415og.rs b/embassy-stm32/src/pac/stm32f415og.rs
index 7b3b9554d..df71f8770 100644
--- a/embassy-stm32/src/pac/stm32f415og.rs
+++ b/embassy-stm32/src/pac/stm32f415og.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f415rg.rs b/embassy-stm32/src/pac/stm32f415rg.rs
index 7b3b9554d..df71f8770 100644
--- a/embassy-stm32/src/pac/stm32f415rg.rs
+++ b/embassy-stm32/src/pac/stm32f415rg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f415vg.rs b/embassy-stm32/src/pac/stm32f415vg.rs
index 7b3b9554d..df71f8770 100644
--- a/embassy-stm32/src/pac/stm32f415vg.rs
+++ b/embassy-stm32/src/pac/stm32f415vg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f415zg.rs b/embassy-stm32/src/pac/stm32f415zg.rs
index 7b3b9554d..df71f8770 100644
--- a/embassy-stm32/src/pac/stm32f415zg.rs
+++ b/embassy-stm32/src/pac/stm32f415zg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f417ie.rs b/embassy-stm32/src/pac/stm32f417ie.rs
index ed84cd007..2e802e9e9 100644
--- a/embassy-stm32/src/pac/stm32f417ie.rs
+++ b/embassy-stm32/src/pac/stm32f417ie.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f417ig.rs b/embassy-stm32/src/pac/stm32f417ig.rs
index ed84cd007..2e802e9e9 100644
--- a/embassy-stm32/src/pac/stm32f417ig.rs
+++ b/embassy-stm32/src/pac/stm32f417ig.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f417ve.rs b/embassy-stm32/src/pac/stm32f417ve.rs
index ed84cd007..2e802e9e9 100644
--- a/embassy-stm32/src/pac/stm32f417ve.rs
+++ b/embassy-stm32/src/pac/stm32f417ve.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f417vg.rs b/embassy-stm32/src/pac/stm32f417vg.rs
index ed84cd007..2e802e9e9 100644
--- a/embassy-stm32/src/pac/stm32f417vg.rs
+++ b/embassy-stm32/src/pac/stm32f417vg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f417ze.rs b/embassy-stm32/src/pac/stm32f417ze.rs
index ed84cd007..2e802e9e9 100644
--- a/embassy-stm32/src/pac/stm32f417ze.rs
+++ b/embassy-stm32/src/pac/stm32f417ze.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f417zg.rs b/embassy-stm32/src/pac/stm32f417zg.rs
index ed84cd007..2e802e9e9 100644
--- a/embassy-stm32/src/pac/stm32f417zg.rs
+++ b/embassy-stm32/src/pac/stm32f417zg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f423ch.rs b/embassy-stm32/src/pac/stm32f423ch.rs
index f2d37b514..3dd033251 100644
--- a/embassy-stm32/src/pac/stm32f423ch.rs
+++ b/embassy-stm32/src/pac/stm32f423ch.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f423mh.rs b/embassy-stm32/src/pac/stm32f423mh.rs
index ab5370902..0e844e7db 100644
--- a/embassy-stm32/src/pac/stm32f423mh.rs
+++ b/embassy-stm32/src/pac/stm32f423mh.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f423rh.rs b/embassy-stm32/src/pac/stm32f423rh.rs
index ab5370902..0e844e7db 100644
--- a/embassy-stm32/src/pac/stm32f423rh.rs
+++ b/embassy-stm32/src/pac/stm32f423rh.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f423vh.rs b/embassy-stm32/src/pac/stm32f423vh.rs
index ab5370902..0e844e7db 100644
--- a/embassy-stm32/src/pac/stm32f423vh.rs
+++ b/embassy-stm32/src/pac/stm32f423vh.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f423zh.rs b/embassy-stm32/src/pac/stm32f423zh.rs
index ab5370902..0e844e7db 100644
--- a/embassy-stm32/src/pac/stm32f423zh.rs
+++ b/embassy-stm32/src/pac/stm32f423zh.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f427ag.rs b/embassy-stm32/src/pac/stm32f427ag.rs
index 25ef303f2..36a117c12 100644
--- a/embassy-stm32/src/pac/stm32f427ag.rs
+++ b/embassy-stm32/src/pac/stm32f427ag.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f427ai.rs b/embassy-stm32/src/pac/stm32f427ai.rs
index 25ef303f2..36a117c12 100644
--- a/embassy-stm32/src/pac/stm32f427ai.rs
+++ b/embassy-stm32/src/pac/stm32f427ai.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f427ig.rs b/embassy-stm32/src/pac/stm32f427ig.rs
index 25ef303f2..36a117c12 100644
--- a/embassy-stm32/src/pac/stm32f427ig.rs
+++ b/embassy-stm32/src/pac/stm32f427ig.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f427ii.rs b/embassy-stm32/src/pac/stm32f427ii.rs
index 25ef303f2..36a117c12 100644
--- a/embassy-stm32/src/pac/stm32f427ii.rs
+++ b/embassy-stm32/src/pac/stm32f427ii.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f427vg.rs b/embassy-stm32/src/pac/stm32f427vg.rs
index 25ef303f2..36a117c12 100644
--- a/embassy-stm32/src/pac/stm32f427vg.rs
+++ b/embassy-stm32/src/pac/stm32f427vg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f427vi.rs b/embassy-stm32/src/pac/stm32f427vi.rs
index 25ef303f2..36a117c12 100644
--- a/embassy-stm32/src/pac/stm32f427vi.rs
+++ b/embassy-stm32/src/pac/stm32f427vi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f427zg.rs b/embassy-stm32/src/pac/stm32f427zg.rs
index 25ef303f2..36a117c12 100644
--- a/embassy-stm32/src/pac/stm32f427zg.rs
+++ b/embassy-stm32/src/pac/stm32f427zg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f427zi.rs b/embassy-stm32/src/pac/stm32f427zi.rs
index 25ef303f2..36a117c12 100644
--- a/embassy-stm32/src/pac/stm32f427zi.rs
+++ b/embassy-stm32/src/pac/stm32f427zi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429ag.rs b/embassy-stm32/src/pac/stm32f429ag.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429ag.rs
+++ b/embassy-stm32/src/pac/stm32f429ag.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429ai.rs b/embassy-stm32/src/pac/stm32f429ai.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429ai.rs
+++ b/embassy-stm32/src/pac/stm32f429ai.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429be.rs b/embassy-stm32/src/pac/stm32f429be.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429be.rs
+++ b/embassy-stm32/src/pac/stm32f429be.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429bg.rs b/embassy-stm32/src/pac/stm32f429bg.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429bg.rs
+++ b/embassy-stm32/src/pac/stm32f429bg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429bi.rs b/embassy-stm32/src/pac/stm32f429bi.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429bi.rs
+++ b/embassy-stm32/src/pac/stm32f429bi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429ie.rs b/embassy-stm32/src/pac/stm32f429ie.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429ie.rs
+++ b/embassy-stm32/src/pac/stm32f429ie.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429ig.rs b/embassy-stm32/src/pac/stm32f429ig.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429ig.rs
+++ b/embassy-stm32/src/pac/stm32f429ig.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429ii.rs b/embassy-stm32/src/pac/stm32f429ii.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429ii.rs
+++ b/embassy-stm32/src/pac/stm32f429ii.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429ne.rs b/embassy-stm32/src/pac/stm32f429ne.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429ne.rs
+++ b/embassy-stm32/src/pac/stm32f429ne.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429ng.rs b/embassy-stm32/src/pac/stm32f429ng.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429ng.rs
+++ b/embassy-stm32/src/pac/stm32f429ng.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429ni.rs b/embassy-stm32/src/pac/stm32f429ni.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429ni.rs
+++ b/embassy-stm32/src/pac/stm32f429ni.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429ve.rs b/embassy-stm32/src/pac/stm32f429ve.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429ve.rs
+++ b/embassy-stm32/src/pac/stm32f429ve.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429vg.rs b/embassy-stm32/src/pac/stm32f429vg.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429vg.rs
+++ b/embassy-stm32/src/pac/stm32f429vg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429vi.rs b/embassy-stm32/src/pac/stm32f429vi.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429vi.rs
+++ b/embassy-stm32/src/pac/stm32f429vi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429ze.rs b/embassy-stm32/src/pac/stm32f429ze.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429ze.rs
+++ b/embassy-stm32/src/pac/stm32f429ze.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429zg.rs b/embassy-stm32/src/pac/stm32f429zg.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429zg.rs
+++ b/embassy-stm32/src/pac/stm32f429zg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f429zi.rs b/embassy-stm32/src/pac/stm32f429zi.rs
index 92d69e1ee..2e314d2f3 100644
--- a/embassy-stm32/src/pac/stm32f429zi.rs
+++ b/embassy-stm32/src/pac/stm32f429zi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f437ai.rs b/embassy-stm32/src/pac/stm32f437ai.rs
index bd699f405..a0f5e14ea 100644
--- a/embassy-stm32/src/pac/stm32f437ai.rs
+++ b/embassy-stm32/src/pac/stm32f437ai.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f437ig.rs b/embassy-stm32/src/pac/stm32f437ig.rs
index bd699f405..a0f5e14ea 100644
--- a/embassy-stm32/src/pac/stm32f437ig.rs
+++ b/embassy-stm32/src/pac/stm32f437ig.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f437ii.rs b/embassy-stm32/src/pac/stm32f437ii.rs
index bd699f405..a0f5e14ea 100644
--- a/embassy-stm32/src/pac/stm32f437ii.rs
+++ b/embassy-stm32/src/pac/stm32f437ii.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f437vg.rs b/embassy-stm32/src/pac/stm32f437vg.rs
index bd699f405..a0f5e14ea 100644
--- a/embassy-stm32/src/pac/stm32f437vg.rs
+++ b/embassy-stm32/src/pac/stm32f437vg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f437vi.rs b/embassy-stm32/src/pac/stm32f437vi.rs
index bd699f405..a0f5e14ea 100644
--- a/embassy-stm32/src/pac/stm32f437vi.rs
+++ b/embassy-stm32/src/pac/stm32f437vi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f437zg.rs b/embassy-stm32/src/pac/stm32f437zg.rs
index bd699f405..a0f5e14ea 100644
--- a/embassy-stm32/src/pac/stm32f437zg.rs
+++ b/embassy-stm32/src/pac/stm32f437zg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f437zi.rs b/embassy-stm32/src/pac/stm32f437zi.rs
index bd699f405..a0f5e14ea 100644
--- a/embassy-stm32/src/pac/stm32f437zi.rs
+++ b/embassy-stm32/src/pac/stm32f437zi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439ai.rs b/embassy-stm32/src/pac/stm32f439ai.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439ai.rs
+++ b/embassy-stm32/src/pac/stm32f439ai.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439bg.rs b/embassy-stm32/src/pac/stm32f439bg.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439bg.rs
+++ b/embassy-stm32/src/pac/stm32f439bg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439bi.rs b/embassy-stm32/src/pac/stm32f439bi.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439bi.rs
+++ b/embassy-stm32/src/pac/stm32f439bi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439ig.rs b/embassy-stm32/src/pac/stm32f439ig.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439ig.rs
+++ b/embassy-stm32/src/pac/stm32f439ig.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439ii.rs b/embassy-stm32/src/pac/stm32f439ii.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439ii.rs
+++ b/embassy-stm32/src/pac/stm32f439ii.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439ng.rs b/embassy-stm32/src/pac/stm32f439ng.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439ng.rs
+++ b/embassy-stm32/src/pac/stm32f439ng.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439ni.rs b/embassy-stm32/src/pac/stm32f439ni.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439ni.rs
+++ b/embassy-stm32/src/pac/stm32f439ni.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439vg.rs b/embassy-stm32/src/pac/stm32f439vg.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439vg.rs
+++ b/embassy-stm32/src/pac/stm32f439vg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439vi.rs b/embassy-stm32/src/pac/stm32f439vi.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439vi.rs
+++ b/embassy-stm32/src/pac/stm32f439vi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439zg.rs b/embassy-stm32/src/pac/stm32f439zg.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439zg.rs
+++ b/embassy-stm32/src/pac/stm32f439zg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f439zi.rs b/embassy-stm32/src/pac/stm32f439zi.rs
index ba416f544..80e31cb15 100644
--- a/embassy-stm32/src/pac/stm32f439zi.rs
+++ b/embassy-stm32/src/pac/stm32f439zi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ae.rs b/embassy-stm32/src/pac/stm32f469ae.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ae.rs
+++ b/embassy-stm32/src/pac/stm32f469ae.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ag.rs b/embassy-stm32/src/pac/stm32f469ag.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ag.rs
+++ b/embassy-stm32/src/pac/stm32f469ag.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ai.rs b/embassy-stm32/src/pac/stm32f469ai.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ai.rs
+++ b/embassy-stm32/src/pac/stm32f469ai.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469be.rs b/embassy-stm32/src/pac/stm32f469be.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469be.rs
+++ b/embassy-stm32/src/pac/stm32f469be.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469bg.rs b/embassy-stm32/src/pac/stm32f469bg.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469bg.rs
+++ b/embassy-stm32/src/pac/stm32f469bg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469bi.rs b/embassy-stm32/src/pac/stm32f469bi.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469bi.rs
+++ b/embassy-stm32/src/pac/stm32f469bi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ie.rs b/embassy-stm32/src/pac/stm32f469ie.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ie.rs
+++ b/embassy-stm32/src/pac/stm32f469ie.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ig.rs b/embassy-stm32/src/pac/stm32f469ig.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ig.rs
+++ b/embassy-stm32/src/pac/stm32f469ig.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ii.rs b/embassy-stm32/src/pac/stm32f469ii.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ii.rs
+++ b/embassy-stm32/src/pac/stm32f469ii.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ne.rs b/embassy-stm32/src/pac/stm32f469ne.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ne.rs
+++ b/embassy-stm32/src/pac/stm32f469ne.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ng.rs b/embassy-stm32/src/pac/stm32f469ng.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ng.rs
+++ b/embassy-stm32/src/pac/stm32f469ng.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ni.rs b/embassy-stm32/src/pac/stm32f469ni.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ni.rs
+++ b/embassy-stm32/src/pac/stm32f469ni.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ve.rs b/embassy-stm32/src/pac/stm32f469ve.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ve.rs
+++ b/embassy-stm32/src/pac/stm32f469ve.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469vg.rs b/embassy-stm32/src/pac/stm32f469vg.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469vg.rs
+++ b/embassy-stm32/src/pac/stm32f469vg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469vi.rs b/embassy-stm32/src/pac/stm32f469vi.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469vi.rs
+++ b/embassy-stm32/src/pac/stm32f469vi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469ze.rs b/embassy-stm32/src/pac/stm32f469ze.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469ze.rs
+++ b/embassy-stm32/src/pac/stm32f469ze.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469zg.rs b/embassy-stm32/src/pac/stm32f469zg.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469zg.rs
+++ b/embassy-stm32/src/pac/stm32f469zg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f469zi.rs b/embassy-stm32/src/pac/stm32f469zi.rs
index da697dcd9..77d327564 100644
--- a/embassy-stm32/src/pac/stm32f469zi.rs
+++ b/embassy-stm32/src/pac/stm32f469zi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479ag.rs b/embassy-stm32/src/pac/stm32f479ag.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479ag.rs
+++ b/embassy-stm32/src/pac/stm32f479ag.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479ai.rs b/embassy-stm32/src/pac/stm32f479ai.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479ai.rs
+++ b/embassy-stm32/src/pac/stm32f479ai.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479bg.rs b/embassy-stm32/src/pac/stm32f479bg.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479bg.rs
+++ b/embassy-stm32/src/pac/stm32f479bg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479bi.rs b/embassy-stm32/src/pac/stm32f479bi.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479bi.rs
+++ b/embassy-stm32/src/pac/stm32f479bi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479ig.rs b/embassy-stm32/src/pac/stm32f479ig.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479ig.rs
+++ b/embassy-stm32/src/pac/stm32f479ig.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479ii.rs b/embassy-stm32/src/pac/stm32f479ii.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479ii.rs
+++ b/embassy-stm32/src/pac/stm32f479ii.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479ng.rs b/embassy-stm32/src/pac/stm32f479ng.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479ng.rs
+++ b/embassy-stm32/src/pac/stm32f479ng.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479ni.rs b/embassy-stm32/src/pac/stm32f479ni.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479ni.rs
+++ b/embassy-stm32/src/pac/stm32f479ni.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479vg.rs b/embassy-stm32/src/pac/stm32f479vg.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479vg.rs
+++ b/embassy-stm32/src/pac/stm32f479vg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479vi.rs b/embassy-stm32/src/pac/stm32f479vi.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479vi.rs
+++ b/embassy-stm32/src/pac/stm32f479vi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479zg.rs b/embassy-stm32/src/pac/stm32f479zg.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479zg.rs
+++ b/embassy-stm32/src/pac/stm32f479zg.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32f479zi.rs b/embassy-stm32/src/pac/stm32f479zi.rs
index ac43a1fb5..47f8e0ffd 100644
--- a/embassy-stm32/src/pac/stm32f479zi.rs
+++ b/embassy-stm32/src/pac/stm32f479zi.rs
@@ -194,7 +194,7 @@ pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
 pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
 pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
 impl_usart!(USART1);
diff --git a/embassy-stm32/src/pac/stm32l412c8.rs b/embassy-stm32/src/pac/stm32l412c8.rs
index a32d8283d..1976a7823 100644
--- a/embassy-stm32/src/pac/stm32l412c8.rs
+++ b/embassy-stm32/src/pac/stm32l412c8.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l412cb.rs b/embassy-stm32/src/pac/stm32l412cb.rs
index a32d8283d..1976a7823 100644
--- a/embassy-stm32/src/pac/stm32l412cb.rs
+++ b/embassy-stm32/src/pac/stm32l412cb.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l412k8.rs b/embassy-stm32/src/pac/stm32l412k8.rs
index 19c45508a..884b1ef0e 100644
--- a/embassy-stm32/src/pac/stm32l412k8.rs
+++ b/embassy-stm32/src/pac/stm32l412k8.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l412kb.rs b/embassy-stm32/src/pac/stm32l412kb.rs
index 19c45508a..884b1ef0e 100644
--- a/embassy-stm32/src/pac/stm32l412kb.rs
+++ b/embassy-stm32/src/pac/stm32l412kb.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l412r8.rs b/embassy-stm32/src/pac/stm32l412r8.rs
index a32d8283d..1976a7823 100644
--- a/embassy-stm32/src/pac/stm32l412r8.rs
+++ b/embassy-stm32/src/pac/stm32l412r8.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l412rb.rs b/embassy-stm32/src/pac/stm32l412rb.rs
index a32d8283d..1976a7823 100644
--- a/embassy-stm32/src/pac/stm32l412rb.rs
+++ b/embassy-stm32/src/pac/stm32l412rb.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l412t8.rs b/embassy-stm32/src/pac/stm32l412t8.rs
index 19c45508a..884b1ef0e 100644
--- a/embassy-stm32/src/pac/stm32l412t8.rs
+++ b/embassy-stm32/src/pac/stm32l412t8.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l412tb.rs b/embassy-stm32/src/pac/stm32l412tb.rs
index 19c45508a..884b1ef0e 100644
--- a/embassy-stm32/src/pac/stm32l412tb.rs
+++ b/embassy-stm32/src/pac/stm32l412tb.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l422cb.rs b/embassy-stm32/src/pac/stm32l422cb.rs
index d56ce2c60..7b50a7139 100644
--- a/embassy-stm32/src/pac/stm32l422cb.rs
+++ b/embassy-stm32/src/pac/stm32l422cb.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l422kb.rs b/embassy-stm32/src/pac/stm32l422kb.rs
index 60ad006d5..92021a645 100644
--- a/embassy-stm32/src/pac/stm32l422kb.rs
+++ b/embassy-stm32/src/pac/stm32l422kb.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l422rb.rs b/embassy-stm32/src/pac/stm32l422rb.rs
index d56ce2c60..7b50a7139 100644
--- a/embassy-stm32/src/pac/stm32l422rb.rs
+++ b/embassy-stm32/src/pac/stm32l422rb.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l422tb.rs b/embassy-stm32/src/pac/stm32l422tb.rs
index 60ad006d5..92021a645 100644
--- a/embassy-stm32/src/pac/stm32l422tb.rs
+++ b/embassy-stm32/src/pac/stm32l422tb.rs
@@ -92,7 +92,7 @@ pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l431cb.rs b/embassy-stm32/src/pac/stm32l431cb.rs
index 607dda955..c3951c751 100644
--- a/embassy-stm32/src/pac/stm32l431cb.rs
+++ b/embassy-stm32/src/pac/stm32l431cb.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l431cc.rs b/embassy-stm32/src/pac/stm32l431cc.rs
index 607dda955..c3951c751 100644
--- a/embassy-stm32/src/pac/stm32l431cc.rs
+++ b/embassy-stm32/src/pac/stm32l431cc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l431kb.rs b/embassy-stm32/src/pac/stm32l431kb.rs
index 5e239a669..7d974d49d 100644
--- a/embassy-stm32/src/pac/stm32l431kb.rs
+++ b/embassy-stm32/src/pac/stm32l431kb.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l431kc.rs b/embassy-stm32/src/pac/stm32l431kc.rs
index 5e239a669..7d974d49d 100644
--- a/embassy-stm32/src/pac/stm32l431kc.rs
+++ b/embassy-stm32/src/pac/stm32l431kc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l431rb.rs b/embassy-stm32/src/pac/stm32l431rb.rs
index 607dda955..c3951c751 100644
--- a/embassy-stm32/src/pac/stm32l431rb.rs
+++ b/embassy-stm32/src/pac/stm32l431rb.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l431rc.rs b/embassy-stm32/src/pac/stm32l431rc.rs
index 607dda955..c3951c751 100644
--- a/embassy-stm32/src/pac/stm32l431rc.rs
+++ b/embassy-stm32/src/pac/stm32l431rc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l431vc.rs b/embassy-stm32/src/pac/stm32l431vc.rs
index 607dda955..c3951c751 100644
--- a/embassy-stm32/src/pac/stm32l431vc.rs
+++ b/embassy-stm32/src/pac/stm32l431vc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l432kb.rs b/embassy-stm32/src/pac/stm32l432kb.rs
index 62b022c86..e0e534faa 100644
--- a/embassy-stm32/src/pac/stm32l432kb.rs
+++ b/embassy-stm32/src/pac/stm32l432kb.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l432kc.rs b/embassy-stm32/src/pac/stm32l432kc.rs
index 62b022c86..e0e534faa 100644
--- a/embassy-stm32/src/pac/stm32l432kc.rs
+++ b/embassy-stm32/src/pac/stm32l432kc.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l433cb.rs b/embassy-stm32/src/pac/stm32l433cb.rs
index 2de328aaa..5e10d9721 100644
--- a/embassy-stm32/src/pac/stm32l433cb.rs
+++ b/embassy-stm32/src/pac/stm32l433cb.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l433cc.rs b/embassy-stm32/src/pac/stm32l433cc.rs
index 2de328aaa..5e10d9721 100644
--- a/embassy-stm32/src/pac/stm32l433cc.rs
+++ b/embassy-stm32/src/pac/stm32l433cc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l433rb.rs b/embassy-stm32/src/pac/stm32l433rb.rs
index 2de328aaa..5e10d9721 100644
--- a/embassy-stm32/src/pac/stm32l433rb.rs
+++ b/embassy-stm32/src/pac/stm32l433rb.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l433rc.rs b/embassy-stm32/src/pac/stm32l433rc.rs
index 2de328aaa..5e10d9721 100644
--- a/embassy-stm32/src/pac/stm32l433rc.rs
+++ b/embassy-stm32/src/pac/stm32l433rc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l433vc.rs b/embassy-stm32/src/pac/stm32l433vc.rs
index 2de328aaa..5e10d9721 100644
--- a/embassy-stm32/src/pac/stm32l433vc.rs
+++ b/embassy-stm32/src/pac/stm32l433vc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l442kc.rs b/embassy-stm32/src/pac/stm32l442kc.rs
index e6f1bd93e..2f1bead4c 100644
--- a/embassy-stm32/src/pac/stm32l442kc.rs
+++ b/embassy-stm32/src/pac/stm32l442kc.rs
@@ -75,7 +75,7 @@ pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _);
 pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l443cc.rs b/embassy-stm32/src/pac/stm32l443cc.rs
index 3bff6dc0b..e1860a9de 100644
--- a/embassy-stm32/src/pac/stm32l443cc.rs
+++ b/embassy-stm32/src/pac/stm32l443cc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l443rc.rs b/embassy-stm32/src/pac/stm32l443rc.rs
index 3bff6dc0b..e1860a9de 100644
--- a/embassy-stm32/src/pac/stm32l443rc.rs
+++ b/embassy-stm32/src/pac/stm32l443rc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l443vc.rs b/embassy-stm32/src/pac/stm32l443vc.rs
index 3bff6dc0b..e1860a9de 100644
--- a/embassy-stm32/src/pac/stm32l443vc.rs
+++ b/embassy-stm32/src/pac/stm32l443vc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l451cc.rs b/embassy-stm32/src/pac/stm32l451cc.rs
index ebe371279..29565d76d 100644
--- a/embassy-stm32/src/pac/stm32l451cc.rs
+++ b/embassy-stm32/src/pac/stm32l451cc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l451ce.rs b/embassy-stm32/src/pac/stm32l451ce.rs
index ebe371279..29565d76d 100644
--- a/embassy-stm32/src/pac/stm32l451ce.rs
+++ b/embassy-stm32/src/pac/stm32l451ce.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l451rc.rs b/embassy-stm32/src/pac/stm32l451rc.rs
index ebe371279..29565d76d 100644
--- a/embassy-stm32/src/pac/stm32l451rc.rs
+++ b/embassy-stm32/src/pac/stm32l451rc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l451re.rs b/embassy-stm32/src/pac/stm32l451re.rs
index ebe371279..29565d76d 100644
--- a/embassy-stm32/src/pac/stm32l451re.rs
+++ b/embassy-stm32/src/pac/stm32l451re.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l451vc.rs b/embassy-stm32/src/pac/stm32l451vc.rs
index ebe371279..29565d76d 100644
--- a/embassy-stm32/src/pac/stm32l451vc.rs
+++ b/embassy-stm32/src/pac/stm32l451vc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l451ve.rs b/embassy-stm32/src/pac/stm32l451ve.rs
index ebe371279..29565d76d 100644
--- a/embassy-stm32/src/pac/stm32l451ve.rs
+++ b/embassy-stm32/src/pac/stm32l451ve.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l452cc.rs b/embassy-stm32/src/pac/stm32l452cc.rs
index 9d55b6f78..e6faacf14 100644
--- a/embassy-stm32/src/pac/stm32l452cc.rs
+++ b/embassy-stm32/src/pac/stm32l452cc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l452ce.rs b/embassy-stm32/src/pac/stm32l452ce.rs
index 9d55b6f78..e6faacf14 100644
--- a/embassy-stm32/src/pac/stm32l452ce.rs
+++ b/embassy-stm32/src/pac/stm32l452ce.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l452rc.rs b/embassy-stm32/src/pac/stm32l452rc.rs
index 9d55b6f78..e6faacf14 100644
--- a/embassy-stm32/src/pac/stm32l452rc.rs
+++ b/embassy-stm32/src/pac/stm32l452rc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l452re.rs b/embassy-stm32/src/pac/stm32l452re.rs
index 9d55b6f78..e6faacf14 100644
--- a/embassy-stm32/src/pac/stm32l452re.rs
+++ b/embassy-stm32/src/pac/stm32l452re.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l452vc.rs b/embassy-stm32/src/pac/stm32l452vc.rs
index 9d55b6f78..e6faacf14 100644
--- a/embassy-stm32/src/pac/stm32l452vc.rs
+++ b/embassy-stm32/src/pac/stm32l452vc.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l452ve.rs b/embassy-stm32/src/pac/stm32l452ve.rs
index 9d55b6f78..e6faacf14 100644
--- a/embassy-stm32/src/pac/stm32l452ve.rs
+++ b/embassy-stm32/src/pac/stm32l452ve.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l462ce.rs b/embassy-stm32/src/pac/stm32l462ce.rs
index d9f0ea312..374f5bd5a 100644
--- a/embassy-stm32/src/pac/stm32l462ce.rs
+++ b/embassy-stm32/src/pac/stm32l462ce.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l462re.rs b/embassy-stm32/src/pac/stm32l462re.rs
index d9f0ea312..374f5bd5a 100644
--- a/embassy-stm32/src/pac/stm32l462re.rs
+++ b/embassy-stm32/src/pac/stm32l462re.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l462ve.rs b/embassy-stm32/src/pac/stm32l462ve.rs
index d9f0ea312..374f5bd5a 100644
--- a/embassy-stm32/src/pac/stm32l462ve.rs
+++ b/embassy-stm32/src/pac/stm32l462ve.rs
@@ -109,7 +109,7 @@ pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
 pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l471qe.rs b/embassy-stm32/src/pac/stm32l471qe.rs
index ad091268c..1d4b4e8b5 100644
--- a/embassy-stm32/src/pac/stm32l471qe.rs
+++ b/embassy-stm32/src/pac/stm32l471qe.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l471qg.rs b/embassy-stm32/src/pac/stm32l471qg.rs
index ad091268c..1d4b4e8b5 100644
--- a/embassy-stm32/src/pac/stm32l471qg.rs
+++ b/embassy-stm32/src/pac/stm32l471qg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l471re.rs b/embassy-stm32/src/pac/stm32l471re.rs
index ad091268c..1d4b4e8b5 100644
--- a/embassy-stm32/src/pac/stm32l471re.rs
+++ b/embassy-stm32/src/pac/stm32l471re.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l471rg.rs b/embassy-stm32/src/pac/stm32l471rg.rs
index ad091268c..1d4b4e8b5 100644
--- a/embassy-stm32/src/pac/stm32l471rg.rs
+++ b/embassy-stm32/src/pac/stm32l471rg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l471ve.rs b/embassy-stm32/src/pac/stm32l471ve.rs
index ad091268c..1d4b4e8b5 100644
--- a/embassy-stm32/src/pac/stm32l471ve.rs
+++ b/embassy-stm32/src/pac/stm32l471ve.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l471vg.rs b/embassy-stm32/src/pac/stm32l471vg.rs
index ad091268c..1d4b4e8b5 100644
--- a/embassy-stm32/src/pac/stm32l471vg.rs
+++ b/embassy-stm32/src/pac/stm32l471vg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l471ze.rs b/embassy-stm32/src/pac/stm32l471ze.rs
index ad091268c..1d4b4e8b5 100644
--- a/embassy-stm32/src/pac/stm32l471ze.rs
+++ b/embassy-stm32/src/pac/stm32l471ze.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l471zg.rs b/embassy-stm32/src/pac/stm32l471zg.rs
index ad091268c..1d4b4e8b5 100644
--- a/embassy-stm32/src/pac/stm32l471zg.rs
+++ b/embassy-stm32/src/pac/stm32l471zg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l475rc.rs b/embassy-stm32/src/pac/stm32l475rc.rs
index 7f016e2e2..7d5fbfb85 100644
--- a/embassy-stm32/src/pac/stm32l475rc.rs
+++ b/embassy-stm32/src/pac/stm32l475rc.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l475re.rs b/embassy-stm32/src/pac/stm32l475re.rs
index 7f016e2e2..7d5fbfb85 100644
--- a/embassy-stm32/src/pac/stm32l475re.rs
+++ b/embassy-stm32/src/pac/stm32l475re.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l475rg.rs b/embassy-stm32/src/pac/stm32l475rg.rs
index 7f016e2e2..7d5fbfb85 100644
--- a/embassy-stm32/src/pac/stm32l475rg.rs
+++ b/embassy-stm32/src/pac/stm32l475rg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l475vc.rs b/embassy-stm32/src/pac/stm32l475vc.rs
index 7f016e2e2..7d5fbfb85 100644
--- a/embassy-stm32/src/pac/stm32l475vc.rs
+++ b/embassy-stm32/src/pac/stm32l475vc.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l475ve.rs b/embassy-stm32/src/pac/stm32l475ve.rs
index 7f016e2e2..7d5fbfb85 100644
--- a/embassy-stm32/src/pac/stm32l475ve.rs
+++ b/embassy-stm32/src/pac/stm32l475ve.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l475vg.rs b/embassy-stm32/src/pac/stm32l475vg.rs
index 7f016e2e2..7d5fbfb85 100644
--- a/embassy-stm32/src/pac/stm32l475vg.rs
+++ b/embassy-stm32/src/pac/stm32l475vg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476je.rs b/embassy-stm32/src/pac/stm32l476je.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476je.rs
+++ b/embassy-stm32/src/pac/stm32l476je.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476jg.rs b/embassy-stm32/src/pac/stm32l476jg.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476jg.rs
+++ b/embassy-stm32/src/pac/stm32l476jg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476me.rs b/embassy-stm32/src/pac/stm32l476me.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476me.rs
+++ b/embassy-stm32/src/pac/stm32l476me.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476mg.rs b/embassy-stm32/src/pac/stm32l476mg.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476mg.rs
+++ b/embassy-stm32/src/pac/stm32l476mg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476qe.rs b/embassy-stm32/src/pac/stm32l476qe.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476qe.rs
+++ b/embassy-stm32/src/pac/stm32l476qe.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476qg.rs b/embassy-stm32/src/pac/stm32l476qg.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476qg.rs
+++ b/embassy-stm32/src/pac/stm32l476qg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476rc.rs b/embassy-stm32/src/pac/stm32l476rc.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476rc.rs
+++ b/embassy-stm32/src/pac/stm32l476rc.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476re.rs b/embassy-stm32/src/pac/stm32l476re.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476re.rs
+++ b/embassy-stm32/src/pac/stm32l476re.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476rg.rs b/embassy-stm32/src/pac/stm32l476rg.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476rg.rs
+++ b/embassy-stm32/src/pac/stm32l476rg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476vc.rs b/embassy-stm32/src/pac/stm32l476vc.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476vc.rs
+++ b/embassy-stm32/src/pac/stm32l476vc.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476ve.rs b/embassy-stm32/src/pac/stm32l476ve.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476ve.rs
+++ b/embassy-stm32/src/pac/stm32l476ve.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476vg.rs b/embassy-stm32/src/pac/stm32l476vg.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476vg.rs
+++ b/embassy-stm32/src/pac/stm32l476vg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476ze.rs b/embassy-stm32/src/pac/stm32l476ze.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476ze.rs
+++ b/embassy-stm32/src/pac/stm32l476ze.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l476zg.rs b/embassy-stm32/src/pac/stm32l476zg.rs
index 342acacfb..2f2bb90b3 100644
--- a/embassy-stm32/src/pac/stm32l476zg.rs
+++ b/embassy-stm32/src/pac/stm32l476zg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l485jc.rs b/embassy-stm32/src/pac/stm32l485jc.rs
index 28186ee2f..cdd6b31d8 100644
--- a/embassy-stm32/src/pac/stm32l485jc.rs
+++ b/embassy-stm32/src/pac/stm32l485jc.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l485je.rs b/embassy-stm32/src/pac/stm32l485je.rs
index 28186ee2f..cdd6b31d8 100644
--- a/embassy-stm32/src/pac/stm32l485je.rs
+++ b/embassy-stm32/src/pac/stm32l485je.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l486jg.rs b/embassy-stm32/src/pac/stm32l486jg.rs
index b98617afb..aad81718f 100644
--- a/embassy-stm32/src/pac/stm32l486jg.rs
+++ b/embassy-stm32/src/pac/stm32l486jg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l486qg.rs b/embassy-stm32/src/pac/stm32l486qg.rs
index b98617afb..aad81718f 100644
--- a/embassy-stm32/src/pac/stm32l486qg.rs
+++ b/embassy-stm32/src/pac/stm32l486qg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l486rg.rs b/embassy-stm32/src/pac/stm32l486rg.rs
index b98617afb..aad81718f 100644
--- a/embassy-stm32/src/pac/stm32l486rg.rs
+++ b/embassy-stm32/src/pac/stm32l486rg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l486vg.rs b/embassy-stm32/src/pac/stm32l486vg.rs
index b98617afb..aad81718f 100644
--- a/embassy-stm32/src/pac/stm32l486vg.rs
+++ b/embassy-stm32/src/pac/stm32l486vg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l486zg.rs b/embassy-stm32/src/pac/stm32l486zg.rs
index b98617afb..aad81718f 100644
--- a/embassy-stm32/src/pac/stm32l486zg.rs
+++ b/embassy-stm32/src/pac/stm32l486zg.rs
@@ -143,7 +143,7 @@ pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _);
 pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496ae.rs b/embassy-stm32/src/pac/stm32l496ae.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496ae.rs
+++ b/embassy-stm32/src/pac/stm32l496ae.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496ag.rs b/embassy-stm32/src/pac/stm32l496ag.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496ag.rs
+++ b/embassy-stm32/src/pac/stm32l496ag.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496qe.rs b/embassy-stm32/src/pac/stm32l496qe.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496qe.rs
+++ b/embassy-stm32/src/pac/stm32l496qe.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496qg.rs b/embassy-stm32/src/pac/stm32l496qg.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496qg.rs
+++ b/embassy-stm32/src/pac/stm32l496qg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496re.rs b/embassy-stm32/src/pac/stm32l496re.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496re.rs
+++ b/embassy-stm32/src/pac/stm32l496re.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496rg.rs b/embassy-stm32/src/pac/stm32l496rg.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496rg.rs
+++ b/embassy-stm32/src/pac/stm32l496rg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496ve.rs b/embassy-stm32/src/pac/stm32l496ve.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496ve.rs
+++ b/embassy-stm32/src/pac/stm32l496ve.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496vg.rs b/embassy-stm32/src/pac/stm32l496vg.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496vg.rs
+++ b/embassy-stm32/src/pac/stm32l496vg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496wg.rs b/embassy-stm32/src/pac/stm32l496wg.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496wg.rs
+++ b/embassy-stm32/src/pac/stm32l496wg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496ze.rs b/embassy-stm32/src/pac/stm32l496ze.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496ze.rs
+++ b/embassy-stm32/src/pac/stm32l496ze.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l496zg.rs b/embassy-stm32/src/pac/stm32l496zg.rs
index 50209fa20..b47a6359e 100644
--- a/embassy-stm32/src/pac/stm32l496zg.rs
+++ b/embassy-stm32/src/pac/stm32l496zg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l4a6ag.rs b/embassy-stm32/src/pac/stm32l4a6ag.rs
index d3ee277f0..bb345cad9 100644
--- a/embassy-stm32/src/pac/stm32l4a6ag.rs
+++ b/embassy-stm32/src/pac/stm32l4a6ag.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l4a6qg.rs b/embassy-stm32/src/pac/stm32l4a6qg.rs
index d3ee277f0..bb345cad9 100644
--- a/embassy-stm32/src/pac/stm32l4a6qg.rs
+++ b/embassy-stm32/src/pac/stm32l4a6qg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l4a6rg.rs b/embassy-stm32/src/pac/stm32l4a6rg.rs
index d3ee277f0..bb345cad9 100644
--- a/embassy-stm32/src/pac/stm32l4a6rg.rs
+++ b/embassy-stm32/src/pac/stm32l4a6rg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l4a6vg.rs b/embassy-stm32/src/pac/stm32l4a6vg.rs
index d3ee277f0..bb345cad9 100644
--- a/embassy-stm32/src/pac/stm32l4a6vg.rs
+++ b/embassy-stm32/src/pac/stm32l4a6vg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l4a6zg.rs b/embassy-stm32/src/pac/stm32l4a6zg.rs
index d3ee277f0..bb345cad9 100644
--- a/embassy-stm32/src/pac/stm32l4a6zg.rs
+++ b/embassy-stm32/src/pac/stm32l4a6zg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
 pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
diff --git a/embassy-stm32/src/pac/stm32l4p5ae.rs b/embassy-stm32/src/pac/stm32l4p5ae.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5ae.rs
+++ b/embassy-stm32/src/pac/stm32l4p5ae.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5ag.rs b/embassy-stm32/src/pac/stm32l4p5ag.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5ag.rs
+++ b/embassy-stm32/src/pac/stm32l4p5ag.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5ce.rs b/embassy-stm32/src/pac/stm32l4p5ce.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5ce.rs
+++ b/embassy-stm32/src/pac/stm32l4p5ce.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5cg.rs b/embassy-stm32/src/pac/stm32l4p5cg.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5cg.rs
+++ b/embassy-stm32/src/pac/stm32l4p5cg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5qe.rs b/embassy-stm32/src/pac/stm32l4p5qe.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5qe.rs
+++ b/embassy-stm32/src/pac/stm32l4p5qe.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5qg.rs b/embassy-stm32/src/pac/stm32l4p5qg.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5qg.rs
+++ b/embassy-stm32/src/pac/stm32l4p5qg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5re.rs b/embassy-stm32/src/pac/stm32l4p5re.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5re.rs
+++ b/embassy-stm32/src/pac/stm32l4p5re.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5rg.rs b/embassy-stm32/src/pac/stm32l4p5rg.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5rg.rs
+++ b/embassy-stm32/src/pac/stm32l4p5rg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5ve.rs b/embassy-stm32/src/pac/stm32l4p5ve.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5ve.rs
+++ b/embassy-stm32/src/pac/stm32l4p5ve.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5vg.rs b/embassy-stm32/src/pac/stm32l4p5vg.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5vg.rs
+++ b/embassy-stm32/src/pac/stm32l4p5vg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5ze.rs b/embassy-stm32/src/pac/stm32l4p5ze.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5ze.rs
+++ b/embassy-stm32/src/pac/stm32l4p5ze.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4p5zg.rs b/embassy-stm32/src/pac/stm32l4p5zg.rs
index b8c08080a..e057a6852 100644
--- a/embassy-stm32/src/pac/stm32l4p5zg.rs
+++ b/embassy-stm32/src/pac/stm32l4p5zg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4q5ag.rs b/embassy-stm32/src/pac/stm32l4q5ag.rs
index 02f751f10..7dcc4d6c6 100644
--- a/embassy-stm32/src/pac/stm32l4q5ag.rs
+++ b/embassy-stm32/src/pac/stm32l4q5ag.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4q5cg.rs b/embassy-stm32/src/pac/stm32l4q5cg.rs
index 02f751f10..7dcc4d6c6 100644
--- a/embassy-stm32/src/pac/stm32l4q5cg.rs
+++ b/embassy-stm32/src/pac/stm32l4q5cg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4q5qg.rs b/embassy-stm32/src/pac/stm32l4q5qg.rs
index 02f751f10..7dcc4d6c6 100644
--- a/embassy-stm32/src/pac/stm32l4q5qg.rs
+++ b/embassy-stm32/src/pac/stm32l4q5qg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4q5rg.rs b/embassy-stm32/src/pac/stm32l4q5rg.rs
index 02f751f10..7dcc4d6c6 100644
--- a/embassy-stm32/src/pac/stm32l4q5rg.rs
+++ b/embassy-stm32/src/pac/stm32l4q5rg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4q5vg.rs b/embassy-stm32/src/pac/stm32l4q5vg.rs
index 02f751f10..7dcc4d6c6 100644
--- a/embassy-stm32/src/pac/stm32l4q5vg.rs
+++ b/embassy-stm32/src/pac/stm32l4q5vg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4q5zg.rs b/embassy-stm32/src/pac/stm32l4q5zg.rs
index 02f751f10..7dcc4d6c6 100644
--- a/embassy-stm32/src/pac/stm32l4q5zg.rs
+++ b/embassy-stm32/src/pac/stm32l4q5zg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r5ag.rs b/embassy-stm32/src/pac/stm32l4r5ag.rs
index 6641e15eb..a9edcc96f 100644
--- a/embassy-stm32/src/pac/stm32l4r5ag.rs
+++ b/embassy-stm32/src/pac/stm32l4r5ag.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r5ai.rs b/embassy-stm32/src/pac/stm32l4r5ai.rs
index 6641e15eb..a9edcc96f 100644
--- a/embassy-stm32/src/pac/stm32l4r5ai.rs
+++ b/embassy-stm32/src/pac/stm32l4r5ai.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r5qg.rs b/embassy-stm32/src/pac/stm32l4r5qg.rs
index 6641e15eb..a9edcc96f 100644
--- a/embassy-stm32/src/pac/stm32l4r5qg.rs
+++ b/embassy-stm32/src/pac/stm32l4r5qg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r5qi.rs b/embassy-stm32/src/pac/stm32l4r5qi.rs
index 6641e15eb..a9edcc96f 100644
--- a/embassy-stm32/src/pac/stm32l4r5qi.rs
+++ b/embassy-stm32/src/pac/stm32l4r5qi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r5vg.rs b/embassy-stm32/src/pac/stm32l4r5vg.rs
index 6641e15eb..a9edcc96f 100644
--- a/embassy-stm32/src/pac/stm32l4r5vg.rs
+++ b/embassy-stm32/src/pac/stm32l4r5vg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r5vi.rs b/embassy-stm32/src/pac/stm32l4r5vi.rs
index 6641e15eb..a9edcc96f 100644
--- a/embassy-stm32/src/pac/stm32l4r5vi.rs
+++ b/embassy-stm32/src/pac/stm32l4r5vi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r5zg.rs b/embassy-stm32/src/pac/stm32l4r5zg.rs
index 6641e15eb..a9edcc96f 100644
--- a/embassy-stm32/src/pac/stm32l4r5zg.rs
+++ b/embassy-stm32/src/pac/stm32l4r5zg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r5zi.rs b/embassy-stm32/src/pac/stm32l4r5zi.rs
index 6641e15eb..a9edcc96f 100644
--- a/embassy-stm32/src/pac/stm32l4r5zi.rs
+++ b/embassy-stm32/src/pac/stm32l4r5zi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r7ai.rs b/embassy-stm32/src/pac/stm32l4r7ai.rs
index 7c318ec41..7118408a7 100644
--- a/embassy-stm32/src/pac/stm32l4r7ai.rs
+++ b/embassy-stm32/src/pac/stm32l4r7ai.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r7vi.rs b/embassy-stm32/src/pac/stm32l4r7vi.rs
index 7c318ec41..7118408a7 100644
--- a/embassy-stm32/src/pac/stm32l4r7vi.rs
+++ b/embassy-stm32/src/pac/stm32l4r7vi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r7zi.rs b/embassy-stm32/src/pac/stm32l4r7zi.rs
index 7c318ec41..7118408a7 100644
--- a/embassy-stm32/src/pac/stm32l4r7zi.rs
+++ b/embassy-stm32/src/pac/stm32l4r7zi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r9ag.rs b/embassy-stm32/src/pac/stm32l4r9ag.rs
index dec66c515..f2636f3dc 100644
--- a/embassy-stm32/src/pac/stm32l4r9ag.rs
+++ b/embassy-stm32/src/pac/stm32l4r9ag.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r9ai.rs b/embassy-stm32/src/pac/stm32l4r9ai.rs
index dec66c515..f2636f3dc 100644
--- a/embassy-stm32/src/pac/stm32l4r9ai.rs
+++ b/embassy-stm32/src/pac/stm32l4r9ai.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r9vg.rs b/embassy-stm32/src/pac/stm32l4r9vg.rs
index dec66c515..f2636f3dc 100644
--- a/embassy-stm32/src/pac/stm32l4r9vg.rs
+++ b/embassy-stm32/src/pac/stm32l4r9vg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r9vi.rs b/embassy-stm32/src/pac/stm32l4r9vi.rs
index dec66c515..f2636f3dc 100644
--- a/embassy-stm32/src/pac/stm32l4r9vi.rs
+++ b/embassy-stm32/src/pac/stm32l4r9vi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r9zg.rs b/embassy-stm32/src/pac/stm32l4r9zg.rs
index dec66c515..f2636f3dc 100644
--- a/embassy-stm32/src/pac/stm32l4r9zg.rs
+++ b/embassy-stm32/src/pac/stm32l4r9zg.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4r9zi.rs b/embassy-stm32/src/pac/stm32l4r9zi.rs
index dec66c515..f2636f3dc 100644
--- a/embassy-stm32/src/pac/stm32l4r9zi.rs
+++ b/embassy-stm32/src/pac/stm32l4r9zi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4s5ai.rs b/embassy-stm32/src/pac/stm32l4s5ai.rs
index 06f30e8fd..a86c017f6 100644
--- a/embassy-stm32/src/pac/stm32l4s5ai.rs
+++ b/embassy-stm32/src/pac/stm32l4s5ai.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4s5qi.rs b/embassy-stm32/src/pac/stm32l4s5qi.rs
index 06f30e8fd..a86c017f6 100644
--- a/embassy-stm32/src/pac/stm32l4s5qi.rs
+++ b/embassy-stm32/src/pac/stm32l4s5qi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4s5vi.rs b/embassy-stm32/src/pac/stm32l4s5vi.rs
index 06f30e8fd..a86c017f6 100644
--- a/embassy-stm32/src/pac/stm32l4s5vi.rs
+++ b/embassy-stm32/src/pac/stm32l4s5vi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4s5zi.rs b/embassy-stm32/src/pac/stm32l4s5zi.rs
index 06f30e8fd..a86c017f6 100644
--- a/embassy-stm32/src/pac/stm32l4s5zi.rs
+++ b/embassy-stm32/src/pac/stm32l4s5zi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4s7ai.rs b/embassy-stm32/src/pac/stm32l4s7ai.rs
index 55843121d..fbba75ae2 100644
--- a/embassy-stm32/src/pac/stm32l4s7ai.rs
+++ b/embassy-stm32/src/pac/stm32l4s7ai.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4s7vi.rs b/embassy-stm32/src/pac/stm32l4s7vi.rs
index 55843121d..fbba75ae2 100644
--- a/embassy-stm32/src/pac/stm32l4s7vi.rs
+++ b/embassy-stm32/src/pac/stm32l4s7vi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4s7zi.rs b/embassy-stm32/src/pac/stm32l4s7zi.rs
index 55843121d..fbba75ae2 100644
--- a/embassy-stm32/src/pac/stm32l4s7zi.rs
+++ b/embassy-stm32/src/pac/stm32l4s7zi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4s9ai.rs b/embassy-stm32/src/pac/stm32l4s9ai.rs
index 57715fbfa..c19cf10d7 100644
--- a/embassy-stm32/src/pac/stm32l4s9ai.rs
+++ b/embassy-stm32/src/pac/stm32l4s9ai.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4s9vi.rs b/embassy-stm32/src/pac/stm32l4s9vi.rs
index 57715fbfa..c19cf10d7 100644
--- a/embassy-stm32/src/pac/stm32l4s9vi.rs
+++ b/embassy-stm32/src/pac/stm32l4s9vi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/pac/stm32l4s9zi.rs b/embassy-stm32/src/pac/stm32l4s9zi.rs
index 57715fbfa..c19cf10d7 100644
--- a/embassy-stm32/src/pac/stm32l4s9zi.rs
+++ b/embassy-stm32/src/pac/stm32l4s9zi.rs
@@ -160,7 +160,7 @@ pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _);
 pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
 pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _);
 pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
-impl_rng!();
+impl_rng!(RNG);
 pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
 pub use regs::exti_v1 as exti;
 pub use regs::gpio_v2 as gpio;
diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs
index 1e7cce01b..9eedcb17d 100644
--- a/embassy-stm32/src/rng.rs
+++ b/embassy-stm32/src/rng.rs
@@ -29,7 +29,24 @@ pub struct Random<T: Instance> {
 impl<T: Instance> Random<T> {
     pub fn new(inner: impl Unborrow<Target=T>) -> Self {
         unborrow!(inner);
-        Self { inner }
+        let mut random = Self { inner };
+        random.reset();
+        random
+    }
+
+    pub fn reset(&mut self) {
+        unsafe {
+            T::regs().cr().modify(|reg| {
+                reg.set_rngen(true);
+                reg.set_ie(true);
+            });
+            T::regs().sr().modify(|reg| {
+                reg.set_seis(false);
+                reg.set_ceis(false);
+            });
+        }
+        // Reference manual says to discard the first.
+        let _ = self.next_u32();
     }
 }
 
@@ -87,7 +104,6 @@ impl<T: Instance> traits::rng::Rng for Random<T> {
                 reg.set_rngen(true);
             });
         }
-
         async move {
             for chunk in dest.chunks_mut(4) {
                 poll_fn(|cx| {
@@ -103,18 +119,10 @@ impl<T: Instance> traits::rng::Rng for Random<T> {
                     if bits.drdy() {
                         Poll::Ready(Ok(()))
                     } else if bits.seis() {
-                        unsafe {
-                            T::regs().sr().modify(|reg| {
-                                reg.set_seis(false);
-                            });
-                        }
+                        self.reset();
                         Poll::Ready(Err(Error::SeedError))
                     } else if bits.ceis() {
-                        unsafe {
-                            T::regs().sr().modify(|reg| {
-                                reg.set_ceis(false);
-                            });
-                        }
+                        self.reset();
                         Poll::Ready(Err(Error::ClockError))
                     } else {
                         Poll::Pending
@@ -141,7 +149,7 @@ pub(crate) mod sealed {
 pub trait Instance: sealed::Instance {}
 
 macro_rules! impl_rng {
-    () => {
+    ($inst:ident) => {
         impl crate::rng::sealed::Instance for peripherals::RNG {
             fn regs() -> crate::pac::chip::rng::Rng {
                 crate::pac::RNG