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authorelagil <[email protected]>2025-08-25 21:10:59 +0200
committerDario Nieuwenhuis <[email protected]>2025-09-05 14:43:29 +0200
commit7a62b8eee8f2f466fbe1878aab42d63aa171ddaa (patch)
tree78f091c274216a946a09349c096310a49fb3d2ae
parenta4d3b4b6ae3f3265ea372e446a6e7b5d3685ea3a (diff)
fix: build issues
-rw-r--r--embassy-stm32/src/dma/gpdma/mod.rs12
-rw-r--r--embassy-stm32/src/dma/gpdma/ringbuffered.rs18
2 files changed, 13 insertions, 17 deletions
diff --git a/embassy-stm32/src/dma/gpdma/mod.rs b/embassy-stm32/src/dma/gpdma/mod.rs
index 9868ce52d..2132f070a 100644
--- a/embassy-stm32/src/dma/gpdma/mod.rs
+++ b/embassy-stm32/src/dma/gpdma/mod.rs
@@ -382,23 +382,21 @@ impl AnyChannel {
382/// Linked-list DMA transfer. 382/// Linked-list DMA transfer.
383#[must_use = "futures do nothing unless you `.await` or poll them"] 383#[must_use = "futures do nothing unless you `.await` or poll them"]
384pub struct LinkedListTransfer<'a, const ITEM_COUNT: usize> { 384pub struct LinkedListTransfer<'a, const ITEM_COUNT: usize> {
385 channel: PeripheralRef<'a, AnyChannel>, 385 channel: Peri<'a, AnyChannel>,
386} 386}
387 387
388impl<'a, const ITEM_COUNT: usize> LinkedListTransfer<'a, ITEM_COUNT> { 388impl<'a, const ITEM_COUNT: usize> LinkedListTransfer<'a, ITEM_COUNT> {
389 /// Create a new linked-list transfer. 389 /// Create a new linked-list transfer.
390 pub unsafe fn new_linked_list<const N: usize>( 390 pub unsafe fn new_linked_list<const N: usize>(
391 channel: impl Peripheral<P = impl Channel> + 'a, 391 channel: Peri<'a, impl Channel>,
392 table: Table<ITEM_COUNT>, 392 table: Table<ITEM_COUNT>,
393 options: TransferOptions, 393 options: TransferOptions,
394 ) -> Self { 394 ) -> Self {
395 into_ref!(channel); 395 Self::new_inner_linked_list(channel.into(), table, options)
396
397 Self::new_inner_linked_list(channel.map_into(), table, options)
398 } 396 }
399 397
400 unsafe fn new_inner_linked_list( 398 unsafe fn new_inner_linked_list(
401 channel: PeripheralRef<'a, AnyChannel>, 399 channel: Peri<'a, AnyChannel>,
402 table: Table<ITEM_COUNT>, 400 table: Table<ITEM_COUNT>,
403 options: TransferOptions, 401 options: TransferOptions,
404 ) -> Self { 402 ) -> Self {
@@ -576,7 +574,7 @@ impl<'a> Transfer<'a> {
576 assert!(mem_len > 0 && mem_len <= 0xFFFF); 574 assert!(mem_len > 0 && mem_len <= 0xFFFF);
577 575
578 channel.configure( 576 channel.configure(
579 _request, 577 request,
580 dir, 578 dir,
581 peri_addr, 579 peri_addr,
582 mem_addr, 580 mem_addr,
diff --git a/embassy-stm32/src/dma/gpdma/ringbuffered.rs b/embassy-stm32/src/dma/gpdma/ringbuffered.rs
index a5d2c700c..88ec666dc 100644
--- a/embassy-stm32/src/dma/gpdma/ringbuffered.rs
+++ b/embassy-stm32/src/dma/gpdma/ringbuffered.rs
@@ -5,7 +5,7 @@ use core::future::poll_fn;
5use core::sync::atomic::{fence, Ordering}; 5use core::sync::atomic::{fence, Ordering};
6use core::task::Waker; 6use core::task::Waker;
7 7
8use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef}; 8use embassy_hal_internal::Peri;
9 9
10use super::{AnyChannel, TransferOptions, STATE}; 10use super::{AnyChannel, TransferOptions, STATE};
11use crate::dma::gpdma::linked_list::{LinearItem, RunMode, Table}; 11use crate::dma::gpdma::linked_list::{LinearItem, RunMode, Table};
@@ -13,7 +13,7 @@ use crate::dma::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaR
13use crate::dma::word::Word; 13use crate::dma::word::Word;
14use crate::dma::{Channel, Request}; 14use crate::dma::{Channel, Request};
15 15
16struct DmaCtrlImpl<'a>(PeripheralRef<'a, AnyChannel>); 16struct DmaCtrlImpl<'a>(Peri<'a, AnyChannel>);
17 17
18impl<'a> DmaCtrl for DmaCtrlImpl<'a> { 18impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
19 fn get_remaining_transfers(&self) -> usize { 19 fn get_remaining_transfers(&self) -> usize {
@@ -48,7 +48,7 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
48 48
49/// Ringbuffer for receiving data using GPDMA linked-list mode. 49/// Ringbuffer for receiving data using GPDMA linked-list mode.
50pub struct ReadableRingBuffer<'a, W: Word> { 50pub struct ReadableRingBuffer<'a, W: Word> {
51 channel: PeripheralRef<'a, AnyChannel>, 51 channel: Peri<'a, AnyChannel>,
52 ringbuf: ReadableDmaRingBuffer<'a, W>, 52 ringbuf: ReadableDmaRingBuffer<'a, W>,
53 table: Table<2>, 53 table: Table<2>,
54} 54}
@@ -58,14 +58,13 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
58 /// 58 ///
59 /// Transfer options are applied to the individual linked list items. 59 /// Transfer options are applied to the individual linked list items.
60 pub unsafe fn new( 60 pub unsafe fn new(
61 channel: impl Peripheral<P = impl Channel> + 'a, 61 channel: Peri<'a, impl Channel>,
62 request: Request, 62 request: Request,
63 peri_addr: *mut W, 63 peri_addr: *mut W,
64 buffer: &'a mut [W], 64 buffer: &'a mut [W],
65 _options: TransferOptions, 65 _options: TransferOptions,
66 ) -> Self { 66 ) -> Self {
67 into_ref!(channel); 67 let channel: Peri<'a, AnyChannel> = channel.into();
68 let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
69 68
70 // Buffer halves should be the same length. 69 // Buffer halves should be the same length.
71 let half_len = buffer.len() / 2; 70 let half_len = buffer.len() / 2;
@@ -195,7 +194,7 @@ impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
195 194
196/// Ringbuffer for writing data using DMA circular mode. 195/// Ringbuffer for writing data using DMA circular mode.
197pub struct WritableRingBuffer<'a, W: Word> { 196pub struct WritableRingBuffer<'a, W: Word> {
198 channel: PeripheralRef<'a, AnyChannel>, 197 channel: Peri<'a, AnyChannel>,
199 ringbuf: WritableDmaRingBuffer<'a, W>, 198 ringbuf: WritableDmaRingBuffer<'a, W>,
200 table: Table<2>, 199 table: Table<2>,
201} 200}
@@ -203,14 +202,13 @@ pub struct WritableRingBuffer<'a, W: Word> {
203impl<'a, W: Word> WritableRingBuffer<'a, W> { 202impl<'a, W: Word> WritableRingBuffer<'a, W> {
204 /// Create a new ring buffer. 203 /// Create a new ring buffer.
205 pub unsafe fn new( 204 pub unsafe fn new(
206 channel: impl Peripheral<P = impl Channel> + 'a, 205 channel: Peri<'a, impl Channel>,
207 request: Request, 206 request: Request,
208 peri_addr: *mut W, 207 peri_addr: *mut W,
209 buffer: &'a mut [W], 208 buffer: &'a mut [W],
210 _options: TransferOptions, 209 _options: TransferOptions,
211 ) -> Self { 210 ) -> Self {
212 into_ref!(channel); 211 let channel: Peri<'a, AnyChannel> = channel.into();
213 let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
214 212
215 // Buffer halves should be the same length. 213 // Buffer halves should be the same length.
216 let half_len = buffer.len() / 2; 214 let half_len = buffer.len() / 2;