fix: spi transfer bug and additions to test

Signed-off-by: Lachezar Lechev <[email protected]>

2 files changed, 28 insertions, 8 deletions

diff --git a/embassy-rp/src/spi.rs b/embassy-rp/src/spi.rs
index e6682ad6a..ebd621ecf 100644
--- a/embassy-rp/src/spi.rs
+++ b/embassy-rp/src/spi.rs
@@ -384,8 +384,8 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
     }
 
     async fn transfer_inner(&mut self, rx_ptr: *mut [u8], tx_ptr: *const [u8]) -> Result<(), Error> {
-        let (_, from_len) = crate::dma::slice_ptr_parts(tx_ptr);
-        let (_, to_len) = crate::dma::slice_ptr_parts_mut(rx_ptr);
+        let (_, tx_len) = crate::dma::slice_ptr_parts(tx_ptr);
+        let (_, rx_len) = crate::dma::slice_ptr_parts_mut(rx_ptr);
 
         unsafe {
             self.inner.regs().dmacr().write(|reg| {
@@ -402,8 +402,8 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
             unsafe {
                 crate::dma::write(&mut tx_ch, tx_ptr, p.dr().ptr() as *mut _, T::TX_DREQ).await;
 
-                if from_len > to_len {
-                    let write_bytes_len = from_len - to_len;
+                if rx_len > tx_len {
+                    let write_bytes_len = rx_len - tx_len;
                     // write dummy data
                     // this will disable incrementation of the buffers
                     crate::dma::write_repeated(tx_ch, p.dr().ptr() as *mut u8, write_bytes_len, T::TX_DREQ).await
@@ -420,7 +420,7 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
         join(tx_transfer, rx_transfer).await;
 
         // if tx > rx we should clear any overflow of the FIFO SPI buffer
-        if from_len > to_len {
+        if tx_len > rx_len {
             let p = self.inner.regs();
             unsafe {
                 while p.sr().read().bsy() {}
diff --git a/tests/rp/src/bin/spi_async.rs b/tests/rp/src/bin/spi_async.rs
index e3fe6e84c..2e22c9de7 100644
--- a/tests/rp/src/bin/spi_async.rs
+++ b/tests/rp/src/bin/spi_async.rs
@@ -33,9 +33,11 @@ async fn main(_spawner: Spawner) {
     {
         let tx_buf = [7_u8, 8, 9, 10, 11, 12];
 
-        let mut rx_buf = [0_u8, 3];
+        let mut rx_buf = [0_u8; 3];
         spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
         assert_eq!(rx_buf, tx_buf[..3]);
+
+        defmt::info!("tx > rx buffer - OK");
     }
 
     // we make sure to that clearing FIFO works after the uneven buffers
@@ -45,18 +47,36 @@ async fn main(_spawner: Spawner) {
         let tx_buf = [13_u8, 14, 15, 16, 17, 18];
         let mut rx_buf = [0_u8; 6];
         spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
-
         assert_eq!(rx_buf, tx_buf);
+
+        defmt::info!("buffer rx length == tx length - OK");
     }
 
     // rx > tx buffer
     {
         let tx_buf = [19_u8, 20, 21];
         let mut rx_buf = [0_u8; 6];
+
+        // we should have written dummy data to tx buffer to sync clock.
         spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
 
-        assert_eq!(rx_buf[..3], tx_buf, "only the first 3 TX bytes should have been received in the RX buffer");
+        assert_eq!(
+            rx_buf[..3],
+            tx_buf,
+            "only the first 3 TX bytes should have been received in the RX buffer"
+        );
         assert_eq!(rx_buf[3..], [0, 0, 0], "the rest of the RX bytes should be empty");
+        defmt::info!("buffer rx length > tx length - OK");
+    }
+
+    // equal rx & tx buffers
+    {
+        let tx_buf = [22_u8, 23, 24, 25, 26, 27];
+        let mut rx_buf = [0_u8; 6];
+        spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
+
+        assert_eq!(rx_buf, tx_buf);
+        defmt::info!("buffer rx length = tx length - OK");
     }
 
     info!("Test OK");