aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGrant Miller <[email protected]>2022-03-14 15:25:20 -0500
committerGrant Miller <[email protected]>2022-03-14 15:56:08 -0500
commit7cd6f00a902d719a463463d7766f70dd7b5f295b (patch)
tree64ac82980d6d503c3579a6d9da110094c4dbc3fb
parent444b37fcdf744128347fd685a14874f44e5e05af (diff)
Add `set_txdmaen` and `set_rxdmaen` functions
Diffstat
-rw-r--r--embassy-stm32/src/spi/mod.rs26
-rw-r--r--embassy-stm32/src/spi/v1.rs20
-rw-r--r--embassy-stm32/src/spi/v2.rs20
-rw-r--r--embassy-stm32/src/spi/v3.rs20
4 files changed, 41 insertions, 45 deletions
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 24efb09d2..3499c8d24 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -627,6 +627,32 @@ fn flush_rx_fifo(regs: Regs) {
627 } 627 }
628} 628}
629 629
630fn set_txdmaen(regs: Regs, val: bool) {
631 unsafe {
632 #[cfg(not(spi_v3))]
633 regs.cr2().modify(|reg| {
634 reg.set_txdmaen(val);
635 });
636 #[cfg(spi_v3)]
637 regs.cfg1().modify(|reg| {
638 reg.set_txdmaen(val);
639 });
640 }
641}
642
643fn set_rxdmaen(regs: Regs, val: bool) {
644 unsafe {
645 #[cfg(not(spi_v3))]
646 regs.cr2().modify(|reg| {
647 reg.set_rxdmaen(val);
648 });
649 #[cfg(spi_v3)]
650 regs.cfg1().modify(|reg| {
651 reg.set_rxdmaen(val);
652 });
653 }
654}
655
630fn finish_dma(regs: Regs) { 656fn finish_dma(regs: Regs) {
631 spin_until_idle(regs); 657 spin_until_idle(regs);
632 658
diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs
index 19562b8a0..853f639ad 100644
--- a/embassy-stm32/src/spi/v1.rs
+++ b/embassy-stm32/src/spi/v1.rs
@@ -27,9 +27,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
27 let tx_f = Transfer::new(&mut self.txdma); 27 let tx_f = Transfer::new(&mut self.txdma);
28 28
29 unsafe { 29 unsafe {
30 T::regs().cr2().modify(|reg| { 30 set_txdmaen(T::regs(), true);
31 reg.set_txdmaen(true);
32 });
33 T::regs().cr1().modify(|w| { 31 T::regs().cr1().modify(|w| {
34 w.set_spe(true); 32 w.set_spe(true);
35 }); 33 });
@@ -52,9 +50,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
52 T::regs().cr1().modify(|w| { 50 T::regs().cr1().modify(|w| {
53 w.set_spe(false); 51 w.set_spe(false);
54 }); 52 });
55 T::regs().cr2().modify(|reg| { 53 set_rxdmaen(T::regs(), true);
56 reg.set_rxdmaen(true);
57 });
58 } 54 }
59 55
60 let (_, clock_byte_count) = slice_ptr_parts_mut(read); 56 let (_, clock_byte_count) = slice_ptr_parts_mut(read);
@@ -76,9 +72,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
76 ); 72 );
77 73
78 unsafe { 74 unsafe {
79 T::regs().cr2().modify(|reg| { 75 set_txdmaen(T::regs(), true);
80 reg.set_txdmaen(true);
81 });
82 T::regs().cr1().modify(|w| { 76 T::regs().cr1().modify(|w| {
83 w.set_spe(true); 77 w.set_spe(true);
84 }); 78 });
@@ -109,9 +103,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
109 T::regs().cr1().modify(|w| { 103 T::regs().cr1().modify(|w| {
110 w.set_spe(false); 104 w.set_spe(false);
111 }); 105 });
112 T::regs().cr2().modify(|reg| { 106 set_rxdmaen(T::regs(), true);
113 reg.set_rxdmaen(true);
114 });
115 } 107 }
116 108
117 // TODO: This is unnecessary in some versions because 109 // TODO: This is unnecessary in some versions because
@@ -129,9 +121,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
129 let tx_f = Transfer::new(&mut self.txdma); 121 let tx_f = Transfer::new(&mut self.txdma);
130 122
131 unsafe { 123 unsafe {
132 T::regs().cr2().modify(|reg| { 124 set_txdmaen(T::regs(), true);
133 reg.set_txdmaen(true);
134 });
135 T::regs().cr1().modify(|w| { 125 T::regs().cr1().modify(|w| {
136 w.set_spe(true); 126 w.set_spe(true);
137 }); 127 });
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index 19562b8a0..853f639ad 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -27,9 +27,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
27 let tx_f = Transfer::new(&mut self.txdma); 27 let tx_f = Transfer::new(&mut self.txdma);
28 28
29 unsafe { 29 unsafe {
30 T::regs().cr2().modify(|reg| { 30 set_txdmaen(T::regs(), true);
31 reg.set_txdmaen(true);
32 });
33 T::regs().cr1().modify(|w| { 31 T::regs().cr1().modify(|w| {
34 w.set_spe(true); 32 w.set_spe(true);
35 }); 33 });
@@ -52,9 +50,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
52 T::regs().cr1().modify(|w| { 50 T::regs().cr1().modify(|w| {
53 w.set_spe(false); 51 w.set_spe(false);
54 }); 52 });
55 T::regs().cr2().modify(|reg| { 53 set_rxdmaen(T::regs(), true);
56 reg.set_rxdmaen(true);
57 });
58 } 54 }
59 55
60 let (_, clock_byte_count) = slice_ptr_parts_mut(read); 56 let (_, clock_byte_count) = slice_ptr_parts_mut(read);
@@ -76,9 +72,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
76 ); 72 );
77 73
78 unsafe { 74 unsafe {
79 T::regs().cr2().modify(|reg| { 75 set_txdmaen(T::regs(), true);
80 reg.set_txdmaen(true);
81 });
82 T::regs().cr1().modify(|w| { 76 T::regs().cr1().modify(|w| {
83 w.set_spe(true); 77 w.set_spe(true);
84 }); 78 });
@@ -109,9 +103,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
109 T::regs().cr1().modify(|w| { 103 T::regs().cr1().modify(|w| {
110 w.set_spe(false); 104 w.set_spe(false);
111 }); 105 });
112 T::regs().cr2().modify(|reg| { 106 set_rxdmaen(T::regs(), true);
113 reg.set_rxdmaen(true);
114 });
115 } 107 }
116 108
117 // TODO: This is unnecessary in some versions because 109 // TODO: This is unnecessary in some versions because
@@ -129,9 +121,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
129 let tx_f = Transfer::new(&mut self.txdma); 121 let tx_f = Transfer::new(&mut self.txdma);
130 122
131 unsafe { 123 unsafe {
132 T::regs().cr2().modify(|reg| { 124 set_txdmaen(T::regs(), true);
133 reg.set_txdmaen(true);
134 });
135 T::regs().cr1().modify(|w| { 125 T::regs().cr1().modify(|w| {
136 w.set_spe(true); 126 w.set_spe(true);
137 }); 127 });
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs
index 5c7472cc0..5a19355f9 100644
--- a/embassy-stm32/src/spi/v3.rs
+++ b/embassy-stm32/src/spi/v3.rs
@@ -27,9 +27,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
27 let tx_f = Transfer::new(&mut self.txdma); 27 let tx_f = Transfer::new(&mut self.txdma);
28 28
29 unsafe { 29 unsafe {
30 T::regs().cfg1().modify(|reg| { 30 set_txdmaen(T::regs(), true);
31 reg.set_txdmaen(true);
32 });
33 T::regs().cr1().modify(|w| { 31 T::regs().cr1().modify(|w| {
34 w.set_spe(true); 32 w.set_spe(true);
35 }); 33 });
@@ -55,9 +53,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
55 T::regs().cr1().modify(|w| { 53 T::regs().cr1().modify(|w| {
56 w.set_spe(false); 54 w.set_spe(false);
57 }); 55 });
58 T::regs().cfg1().modify(|reg| { 56 set_rxdmaen(T::regs(), true);
59 reg.set_rxdmaen(true);
60 });
61 } 57 }
62 58
63 let (_, clock_byte_count) = slice_ptr_parts_mut(read); 59 let (_, clock_byte_count) = slice_ptr_parts_mut(read);
@@ -79,9 +75,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
79 ); 75 );
80 76
81 unsafe { 77 unsafe {
82 T::regs().cfg1().modify(|reg| { 78 set_txdmaen(T::regs(), true);
83 reg.set_txdmaen(true);
84 });
85 T::regs().cr1().modify(|w| { 79 T::regs().cr1().modify(|w| {
86 w.set_spe(true); 80 w.set_spe(true);
87 }); 81 });
@@ -115,9 +109,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
115 T::regs().cr1().modify(|w| { 109 T::regs().cr1().modify(|w| {
116 w.set_spe(false); 110 w.set_spe(false);
117 }); 111 });
118 T::regs().cfg1().modify(|reg| { 112 set_rxdmaen(T::regs(), true);
119 reg.set_rxdmaen(true);
120 });
121 } 113 }
122 114
123 // TODO: This is unnecessary in some versions because 115 // TODO: This is unnecessary in some versions because
@@ -135,9 +127,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
135 let tx_f = Transfer::new(&mut self.txdma); 127 let tx_f = Transfer::new(&mut self.txdma);
136 128
137 unsafe { 129 unsafe {
138 T::regs().cfg1().modify(|reg| { 130 set_txdmaen(T::regs(), true);
139 reg.set_txdmaen(true);
140 });
141 T::regs().cr1().modify(|w| { 131 T::regs().cr1().modify(|w| {
142 w.set_spe(true); 132 w.set_spe(true);
143 }); 133 });
generated by cgit (git 2.34.1) at 2026-04-06 08:12:11 +0000