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authorJacob Rosenthal <[email protected]>2021-11-13 16:38:35 -0700
committerJacob Rosenthal <[email protected]>2021-11-13 16:42:17 -0700
commit7dfc0acb2fd4ecbebc8ae4a63fc94f1f484e66a9 (patch)
treea2681d9d1ec44ee7e6fbd6fbd812ce9631a4c7cf
parent2bcacd4f16276fccb88c7dc3b5e541581e60039b (diff)
nrf: pwm clarify stop and disable pin state
-rw-r--r--embassy-nrf/src/pwm.rs29
1 files changed, 10 insertions, 19 deletions
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index 87a2d5b65..206be5af4 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -308,19 +308,23 @@ impl<'d, T: Instance> SequencePwm<'d, T> {
308 Task::from_reg(&r.tasks_stop) 308 Task::from_reg(&r.tasks_stop)
309 } 309 }
310 310
311 /// Stop playback. 311 /// Stop playback. Does NOT clear the last duty cycle from the pin.
312 #[inline(always)] 312 #[inline(always)]
313 pub fn stop(&self) { 313 pub fn stop(&self) {
314 let r = T::regs(); 314 let r = T::regs();
315 315
316 r.enable.write(|w| w.enable().disabled());
317
318 r.shorts.reset(); 316 r.shorts.reset();
319 317
320 compiler_fence(Ordering::SeqCst); 318 compiler_fence(Ordering::SeqCst);
321 319
320 r.events_stopped.reset();
321
322 // tasks_stop() doesn't exist in all svds so write its bit instead 322 // tasks_stop() doesn't exist in all svds so write its bit instead
323 r.tasks_stop.write(|w| unsafe { w.bits(0x01) }); 323 r.tasks_stop.write(|w| unsafe { w.bits(0x01) });
324
325 while r.events_stopped.read().bits() == 0 {}
326
327 r.enable.write(|w| w.enable().disabled());
324 } 328 }
325} 329}
326 330
@@ -513,19 +517,6 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
513 pwm 517 pwm
514 } 518 }
515 519
516 /// Stop playback
517 #[inline(always)]
518 pub fn stop(&self) {
519 let r = T::regs();
520
521 r.shorts.reset();
522
523 compiler_fence(Ordering::SeqCst);
524
525 // tasks_stop() doesn't exist in all svds so write its bit instead
526 r.tasks_stop.write(|w| unsafe { w.bits(0x01) });
527 }
528
529 /// Enables the PWM generator. 520 /// Enables the PWM generator.
530 #[inline(always)] 521 #[inline(always)]
531 pub fn enable(&self) { 522 pub fn enable(&self) {
@@ -533,7 +524,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
533 r.enable.write(|w| w.enable().enabled()); 524 r.enable.write(|w| w.enable().enabled());
534 } 525 }
535 526
536 /// Disables the PWM generator. 527 /// Disables the PWM generator. Does NOT clear the last duty cycle from the pin.
537 #[inline(always)] 528 #[inline(always)]
538 pub fn disable(&self) { 529 pub fn disable(&self) {
539 let r = T::regs(); 530 let r = T::regs();
@@ -554,13 +545,14 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
554 // defensive before seqstart 545 // defensive before seqstart
555 compiler_fence(Ordering::SeqCst); 546 compiler_fence(Ordering::SeqCst);
556 547
548 r.events_seqend[0].reset();
549
557 // tasks_seqstart() doesn't exist in all svds so write its bit instead 550 // tasks_seqstart() doesn't exist in all svds so write its bit instead
558 r.tasks_seqstart[0].write(|w| unsafe { w.bits(1) }); 551 r.tasks_seqstart[0].write(|w| unsafe { w.bits(1) });
559 552
560 // defensive wait until waveform is loaded after seqstart so set_duty 553 // defensive wait until waveform is loaded after seqstart so set_duty
561 // can't be called again while dma is still reading 554 // can't be called again while dma is still reading
562 while r.events_seqend[0].read().bits() == 0 {} 555 while r.events_seqend[0].read().bits() == 0 {}
563 r.events_seqend[0].write(|w| w);
564 } 556 }
565 557
566 /// Sets the PWM clock prescaler. 558 /// Sets the PWM clock prescaler.
@@ -620,7 +612,6 @@ impl<'a, T: Instance> Drop for SimplePwm<'a, T> {
620 fn drop(&mut self) { 612 fn drop(&mut self) {
621 let r = T::regs(); 613 let r = T::regs();
622 614
623 self.stop();
624 self.disable(); 615 self.disable();
625 616
626 if let Some(pin) = &self.ch0 { 617 if let Some(pin) = &self.ch0 {