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authorThales Fragoso <[email protected]>2021-05-15 22:36:01 -0300
committerThales Fragoso <[email protected]>2021-05-21 20:11:27 -0300
commit7e388fcf5882011b00508a4e67f68d26c5137f7e (patch)
tree69388d19c12fa2b5612145bb726373fd0a49f364
parent3d520f8abe529cbfbbc4a4b575e15bae297a2dc8 (diff)
Add pac RCC for H7 (generated)
Diffstat
-rw-r--r--embassy-stm32/Cargo.toml120
-rw-r--r--embassy-stm32/src/pac/regs.rs17319
-rw-r--r--embassy-stm32/src/pac/stm32h742ag.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742ai.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742bg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742bi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742ig.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742ii.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742vg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742vi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742xg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742xi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742zg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h742zi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743ag.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743ai.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743bg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743bi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743ig.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743ii.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743vg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743vi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743xg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743xi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743zg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h743zi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h745bg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h745bi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h745ig.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h745ii.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h745xg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h745xi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h745zg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h745zi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h747ag.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h747ai.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h747bg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h747bi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h747ig.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h747ii.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h747xg.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h747xi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h747zi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h750ib.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h750vb.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h750xb.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h750zb.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h753ai.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h753bi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h753ii.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h753vi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h753xi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h753zi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h755bi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h755ii.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h755xi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h755zi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h757ai.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h757bi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h757ii.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h757xi.rs19
-rw-r--r--embassy-stm32/src/pac/stm32h757zi.rs19
m---------embassy-stm32/stm32-data0
63 files changed, 18528 insertions, 51 deletions
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 0fa08150e..b4e6d4edc 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -182,6 +182,7 @@ stm32f479vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_r
182stm32f479vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] 182stm32f479vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
183stm32f479zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] 183stm32f479zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
184stm32f479zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] 184stm32f479zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
185<<<<<<< HEAD
185stm32h723ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",] 186stm32h723ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
186stm32h723vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",] 187stm32h723vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
187stm32h723ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",] 188stm32h723ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_spi", "_spi_v3", "_stm32h7", "_syscfg", "_syscfg_h7",]
@@ -395,6 +396,121 @@ stm32l083rz = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_r
395stm32l083v8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_l0", "_rng", "_rng_v1", "_stm32l0", "_syscfg", "_syscfg_l0", "_usart", "_usart_v2",] 396stm32l083v8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_l0", "_rng", "_rng_v1", "_stm32l0", "_syscfg", "_syscfg_l0", "_usart", "_usart_v2",]
396stm32l083vb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_l0", "_rng", "_rng_v1", "_stm32l0", "_syscfg", "_syscfg_l0", "_usart", "_usart_v2",] 397stm32l083vb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_l0", "_rng", "_rng_v1", "_stm32l0", "_syscfg", "_syscfg_l0", "_usart", "_usart_v2",]
397stm32l083vz = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_l0", "_rng", "_rng_v1", "_stm32l0", "_syscfg", "_syscfg_l0", "_usart", "_usart_v2",] 398stm32l083vz = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_l0", "_rng", "_rng_v1", "_stm32l0", "_syscfg", "_syscfg_l0", "_usart", "_usart_v2",]
399=======
400stm32h723ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
401stm32h723vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
402stm32h723ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
403stm32h723zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
404stm32h725ae = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
405stm32h725ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
406stm32h725ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
407stm32h725ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
408stm32h725re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
409stm32h725rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
410stm32h725ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
411stm32h725vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
412stm32h725ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
413stm32h725zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
414stm32h730ab = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
415stm32h730ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
416stm32h730vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
417stm32h730zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
418stm32h733vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
419stm32h733zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
420stm32h735ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
421stm32h735ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
422stm32h735rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
423stm32h735vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
424stm32h735zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
425stm32h742ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
426stm32h742ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
427stm32h742bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
428stm32h742bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
429stm32h742ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
430stm32h742ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
431stm32h742vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
432stm32h742vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
433stm32h742xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
434stm32h742xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
435stm32h742zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
436stm32h742zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
437stm32h743ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
438stm32h743ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
439stm32h743bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
440stm32h743bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
441stm32h743ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
442stm32h743ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
443stm32h743vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
444stm32h743vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
445stm32h743xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
446stm32h743xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
447stm32h743zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
448stm32h743zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
449stm32h745bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
450stm32h745bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
451stm32h745ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
452stm32h745ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
453stm32h745xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
454stm32h745xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
455stm32h745zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
456stm32h745zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
457stm32h747ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
458stm32h747ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
459stm32h747bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
460stm32h747bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
461stm32h747ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
462stm32h747ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
463stm32h747xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
464stm32h747xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
465stm32h747zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
466stm32h750ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
467stm32h750vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
468stm32h750xb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
469stm32h750zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
470stm32h753ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
471stm32h753bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
472stm32h753ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
473stm32h753vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
474stm32h753xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
475stm32h753zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
476stm32h755bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
477stm32h755ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
478stm32h755xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
479stm32h755zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
480stm32h757ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
481stm32h757bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
482stm32h757ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
483stm32h757xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
484stm32h757zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rcc", "_rcc_h7", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
485stm32h7a3ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
486stm32h7a3ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
487stm32h7a3ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
488stm32h7a3ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
489stm32h7a3lg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
490stm32h7a3li = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
491stm32h7a3ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
492stm32h7a3ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
493stm32h7a3qi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
494stm32h7a3rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
495stm32h7a3ri = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
496stm32h7a3vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
497stm32h7a3vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
498stm32h7a3zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
499stm32h7a3zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
500stm32h7b0ab = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
501stm32h7b0ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
502stm32h7b0rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
503stm32h7b0vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
504stm32h7b0zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
505stm32h7b3ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
506stm32h7b3ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
507stm32h7b3li = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
508stm32h7b3ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
509stm32h7b3qi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
510stm32h7b3ri = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
511stm32h7b3vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
512stm32h7b3zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
513>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
398stm32l412c8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] 514stm32l412c8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
399stm32l412cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] 515stm32l412cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
400stm32l412k8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] 516stm32l412k8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
@@ -544,7 +660,11 @@ _exti_v1 = []
544_gpio = [] 660_gpio = []
545_gpio_v2 = [] 661_gpio_v2 = []
546_rcc = [] 662_rcc = []
663<<<<<<< HEAD
547_rcc_l0 = [] 664_rcc_l0 = []
665=======
666_rcc_h7 = []
667>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
548_rng = [ "rand_core",] 668_rng = [ "rand_core",]
549_rng_v1 = [] 669_rng_v1 = []
550_sdmmc = [ "sdio-host",] 670_sdmmc = [ "sdio-host",]
diff --git a/embassy-stm32/src/pac/regs.rs b/embassy-stm32/src/pac/regs.rs
index 34742e420..c91705e50 100644
--- a/embassy-stm32/src/pac/regs.rs
+++ b/embassy-stm32/src/pac/regs.rs
@@ -1,5 +1,6 @@
1#![no_std] 1#![no_std]
2#![doc = "Peripheral access API (generated using svd2rust v0.17.0 (22741fa 2021-04-20))"] 2#![doc = "Peripheral access API (generated using svd2rust v0.17.0 (22741fa 2021-04-20))"]
3<<<<<<< HEAD
3pub mod usart_v1 { 4pub mod usart_v1 {
4 use crate::generic::*; 5 use crate::generic::*;
5 #[doc = "Universal synchronous asynchronous receiver transmitter"] 6 #[doc = "Universal synchronous asynchronous receiver transmitter"]
@@ -1269,10 +1270,886 @@ pub mod dma_v1 {
1269 #[doc = "Circular buffer disabled"] 1270 #[doc = "Circular buffer disabled"]
1270 pub const DISABLED: Self = Self(0); 1271 pub const DISABLED: Self = Self(0);
1271 #[doc = "Circular buffer enabled"] 1272 #[doc = "Circular buffer enabled"]
1273=======
1274pub mod rcc_h7 {
1275 use crate::generic::*;
1276 #[doc = "Reset and clock control"]
1277 #[derive(Copy, Clone)]
1278 pub struct Rcc(pub *mut u8);
1279 unsafe impl Send for Rcc {}
1280 unsafe impl Sync for Rcc {}
1281 impl Rcc {
1282 #[doc = "clock control register"]
1283 pub fn cr(self) -> Reg<regs::Cr, RW> {
1284 unsafe { Reg::from_ptr(self.0.add(0usize)) }
1285 }
1286 #[doc = "RCC HSI configuration register"]
1287 pub fn hsicfgr(self) -> Reg<regs::Hsicfgr, RW> {
1288 unsafe { Reg::from_ptr(self.0.add(4usize)) }
1289 }
1290 #[doc = "RCC Internal Clock Source Calibration Register"]
1291 pub fn icscr(self) -> Reg<regs::Icscr, RW> {
1292 unsafe { Reg::from_ptr(self.0.add(4usize)) }
1293 }
1294 #[doc = "RCC Clock Recovery RC Register"]
1295 pub fn crrcr(self) -> Reg<regs::Crrcr, R> {
1296 unsafe { Reg::from_ptr(self.0.add(8usize)) }
1297 }
1298 #[doc = "RCC CSI configuration register"]
1299 pub fn csicfgr(self) -> Reg<regs::Csicfgr, RW> {
1300 unsafe { Reg::from_ptr(self.0.add(12usize)) }
1301 }
1302 #[doc = "RCC Clock Configuration Register"]
1303 pub fn cfgr(self) -> Reg<regs::Cfgr, RW> {
1304 unsafe { Reg::from_ptr(self.0.add(16usize)) }
1305 }
1306 #[doc = "RCC Domain 1 Clock Configuration Register"]
1307 pub fn d1cfgr(self) -> Reg<regs::D1cfgr, RW> {
1308 unsafe { Reg::from_ptr(self.0.add(24usize)) }
1309 }
1310 #[doc = "RCC Domain 2 Clock Configuration Register"]
1311 pub fn d2cfgr(self) -> Reg<regs::D2cfgr, RW> {
1312 unsafe { Reg::from_ptr(self.0.add(28usize)) }
1313 }
1314 #[doc = "RCC Domain 3 Clock Configuration Register"]
1315 pub fn d3cfgr(self) -> Reg<regs::D3cfgr, RW> {
1316 unsafe { Reg::from_ptr(self.0.add(32usize)) }
1317 }
1318 #[doc = "RCC PLLs Clock Source Selection Register"]
1319 pub fn pllckselr(self) -> Reg<regs::Pllckselr, RW> {
1320 unsafe { Reg::from_ptr(self.0.add(40usize)) }
1321 }
1322 #[doc = "RCC PLLs Configuration Register"]
1323 pub fn pllcfgr(self) -> Reg<regs::Pllcfgr, RW> {
1324 unsafe { Reg::from_ptr(self.0.add(44usize)) }
1325 }
1326 #[doc = "RCC PLL1 Dividers Configuration Register"]
1327 pub fn plldivr(self, n: usize) -> Reg<regs::Pll1divr, RW> {
1328 assert!(n < 3usize);
1329 unsafe { Reg::from_ptr(self.0.add(48usize + n * 8usize)) }
1330 }
1331 #[doc = "RCC PLL1 Fractional Divider Register"]
1332 pub fn pllfracr(self, n: usize) -> Reg<regs::Pll1fracr, RW> {
1333 assert!(n < 3usize);
1334 unsafe { Reg::from_ptr(self.0.add(52usize + n * 8usize)) }
1335 }
1336 #[doc = "RCC Domain 1 Kernel Clock Configuration Register"]
1337 pub fn d1ccipr(self) -> Reg<regs::D1ccipr, RW> {
1338 unsafe { Reg::from_ptr(self.0.add(76usize)) }
1339 }
1340 #[doc = "RCC Domain 2 Kernel Clock Configuration Register"]
1341 pub fn d2ccip1r(self) -> Reg<regs::D2ccip1r, RW> {
1342 unsafe { Reg::from_ptr(self.0.add(80usize)) }
1343 }
1344 #[doc = "RCC Domain 2 Kernel Clock Configuration Register"]
1345 pub fn d2ccip2r(self) -> Reg<regs::D2ccip2r, RW> {
1346 unsafe { Reg::from_ptr(self.0.add(84usize)) }
1347 }
1348 #[doc = "RCC Domain 3 Kernel Clock Configuration Register"]
1349 pub fn d3ccipr(self) -> Reg<regs::D3ccipr, RW> {
1350 unsafe { Reg::from_ptr(self.0.add(88usize)) }
1351 }
1352 #[doc = "RCC Clock Source Interrupt Enable Register"]
1353 pub fn cier(self) -> Reg<regs::Cier, RW> {
1354 unsafe { Reg::from_ptr(self.0.add(96usize)) }
1355 }
1356 #[doc = "RCC Clock Source Interrupt Flag Register"]
1357 pub fn cifr(self) -> Reg<regs::Cifr, R> {
1358 unsafe { Reg::from_ptr(self.0.add(100usize)) }
1359 }
1360 #[doc = "RCC Clock Source Interrupt Clear Register"]
1361 pub fn cicr(self) -> Reg<regs::Cicr, RW> {
1362 unsafe { Reg::from_ptr(self.0.add(104usize)) }
1363 }
1364 #[doc = "RCC Backup Domain Control Register"]
1365 pub fn bdcr(self) -> Reg<regs::Bdcr, RW> {
1366 unsafe { Reg::from_ptr(self.0.add(112usize)) }
1367 }
1368 #[doc = "RCC Clock Control and Status Register"]
1369 pub fn csr(self) -> Reg<regs::Csr, RW> {
1370 unsafe { Reg::from_ptr(self.0.add(116usize)) }
1371 }
1372 #[doc = "RCC AHB3 Reset Register"]
1373 pub fn ahb3rstr(self) -> Reg<regs::Ahb3rstr, RW> {
1374 unsafe { Reg::from_ptr(self.0.add(124usize)) }
1375 }
1376 #[doc = "RCC AHB1 Peripheral Reset Register"]
1377 pub fn ahb1rstr(self) -> Reg<regs::Ahb1rstr, RW> {
1378 unsafe { Reg::from_ptr(self.0.add(128usize)) }
1379 }
1380 #[doc = "RCC AHB2 Peripheral Reset Register"]
1381 pub fn ahb2rstr(self) -> Reg<regs::Ahb2rstr, RW> {
1382 unsafe { Reg::from_ptr(self.0.add(132usize)) }
1383 }
1384 #[doc = "RCC AHB4 Peripheral Reset Register"]
1385 pub fn ahb4rstr(self) -> Reg<regs::Ahb4rstr, RW> {
1386 unsafe { Reg::from_ptr(self.0.add(136usize)) }
1387 }
1388 #[doc = "RCC APB3 Peripheral Reset Register"]
1389 pub fn apb3rstr(self) -> Reg<regs::Apb3rstr, RW> {
1390 unsafe { Reg::from_ptr(self.0.add(140usize)) }
1391 }
1392 #[doc = "RCC APB1 Peripheral Reset Register"]
1393 pub fn apb1lrstr(self) -> Reg<regs::Apb1lrstr, RW> {
1394 unsafe { Reg::from_ptr(self.0.add(144usize)) }
1395 }
1396 #[doc = "RCC APB1 Peripheral Reset Register"]
1397 pub fn apb1hrstr(self) -> Reg<regs::Apb1hrstr, RW> {
1398 unsafe { Reg::from_ptr(self.0.add(148usize)) }
1399 }
1400 #[doc = "RCC APB2 Peripheral Reset Register"]
1401 pub fn apb2rstr(self) -> Reg<regs::Apb2rstr, RW> {
1402 unsafe { Reg::from_ptr(self.0.add(152usize)) }
1403 }
1404 #[doc = "RCC APB4 Peripheral Reset Register"]
1405 pub fn apb4rstr(self) -> Reg<regs::Apb4rstr, RW> {
1406 unsafe { Reg::from_ptr(self.0.add(156usize)) }
1407 }
1408 #[doc = "RCC Global Control Register"]
1409 pub fn gcr(self) -> Reg<regs::Gcr, RW> {
1410 unsafe { Reg::from_ptr(self.0.add(160usize)) }
1411 }
1412 #[doc = "RCC D3 Autonomous mode Register"]
1413 pub fn d3amr(self) -> Reg<regs::D3amr, RW> {
1414 unsafe { Reg::from_ptr(self.0.add(168usize)) }
1415 }
1416 #[doc = "RCC Reset Status Register"]
1417 pub fn rsr(self) -> Reg<regs::Rsr, RW> {
1418 unsafe { Reg::from_ptr(self.0.add(208usize)) }
1419 }
1420 #[doc = "RCC AHB3 Clock Register"]
1421 pub fn ahb3enr(self) -> Reg<regs::Ahb3enr, RW> {
1422 unsafe { Reg::from_ptr(self.0.add(212usize)) }
1423 }
1424 #[doc = "RCC AHB1 Clock Register"]
1425 pub fn ahb1enr(self) -> Reg<regs::Ahb1enr, RW> {
1426 unsafe { Reg::from_ptr(self.0.add(216usize)) }
1427 }
1428 #[doc = "RCC AHB2 Clock Register"]
1429 pub fn ahb2enr(self) -> Reg<regs::Ahb2enr, RW> {
1430 unsafe { Reg::from_ptr(self.0.add(220usize)) }
1431 }
1432 #[doc = "RCC AHB4 Clock Register"]
1433 pub fn ahb4enr(self) -> Reg<regs::Ahb4enr, RW> {
1434 unsafe { Reg::from_ptr(self.0.add(224usize)) }
1435 }
1436 #[doc = "RCC APB3 Clock Register"]
1437 pub fn apb3enr(self) -> Reg<regs::Apb3enr, RW> {
1438 unsafe { Reg::from_ptr(self.0.add(228usize)) }
1439 }
1440 #[doc = "RCC APB1 Clock Register"]
1441 pub fn apb1lenr(self) -> Reg<regs::Apb1lenr, RW> {
1442 unsafe { Reg::from_ptr(self.0.add(232usize)) }
1443 }
1444 #[doc = "RCC APB1 Clock Register"]
1445 pub fn apb1henr(self) -> Reg<regs::Apb1henr, RW> {
1446 unsafe { Reg::from_ptr(self.0.add(236usize)) }
1447 }
1448 #[doc = "RCC APB2 Clock Register"]
1449 pub fn apb2enr(self) -> Reg<regs::Apb2enr, RW> {
1450 unsafe { Reg::from_ptr(self.0.add(240usize)) }
1451 }
1452 #[doc = "RCC APB4 Clock Register"]
1453 pub fn apb4enr(self) -> Reg<regs::Apb4enr, RW> {
1454 unsafe { Reg::from_ptr(self.0.add(244usize)) }
1455 }
1456 #[doc = "RCC AHB3 Sleep Clock Register"]
1457 pub fn ahb3lpenr(self) -> Reg<regs::Ahb3lpenr, RW> {
1458 unsafe { Reg::from_ptr(self.0.add(252usize)) }
1459 }
1460 #[doc = "RCC AHB1 Sleep Clock Register"]
1461 pub fn ahb1lpenr(self) -> Reg<regs::Ahb1lpenr, RW> {
1462 unsafe { Reg::from_ptr(self.0.add(256usize)) }
1463 }
1464 #[doc = "RCC AHB2 Sleep Clock Register"]
1465 pub fn ahb2lpenr(self) -> Reg<regs::Ahb2lpenr, RW> {
1466 unsafe { Reg::from_ptr(self.0.add(260usize)) }
1467 }
1468 #[doc = "RCC AHB4 Sleep Clock Register"]
1469 pub fn ahb4lpenr(self) -> Reg<regs::Ahb4lpenr, RW> {
1470 unsafe { Reg::from_ptr(self.0.add(264usize)) }
1471 }
1472 #[doc = "RCC APB3 Sleep Clock Register"]
1473 pub fn apb3lpenr(self) -> Reg<regs::Apb3lpenr, RW> {
1474 unsafe { Reg::from_ptr(self.0.add(268usize)) }
1475 }
1476 #[doc = "RCC APB1 Low Sleep Clock Register"]
1477 pub fn apb1llpenr(self) -> Reg<regs::Apb1llpenr, RW> {
1478 unsafe { Reg::from_ptr(self.0.add(272usize)) }
1479 }
1480 #[doc = "RCC APB1 High Sleep Clock Register"]
1481 pub fn apb1hlpenr(self) -> Reg<regs::Apb1hlpenr, RW> {
1482 unsafe { Reg::from_ptr(self.0.add(276usize)) }
1483 }
1484 #[doc = "RCC APB2 Sleep Clock Register"]
1485 pub fn apb2lpenr(self) -> Reg<regs::Apb2lpenr, RW> {
1486 unsafe { Reg::from_ptr(self.0.add(280usize)) }
1487 }
1488 #[doc = "RCC APB4 Sleep Clock Register"]
1489 pub fn apb4lpenr(self) -> Reg<regs::Apb4lpenr, RW> {
1490 unsafe { Reg::from_ptr(self.0.add(284usize)) }
1491 }
1492 #[doc = "RCC Reset Status Register"]
1493 pub fn c1_rsr(self) -> Reg<regs::C1Rsr, RW> {
1494 unsafe { Reg::from_ptr(self.0.add(304usize)) }
1495 }
1496 #[doc = "RCC AHB3 Clock Register"]
1497 pub fn c1_ahb3enr(self) -> Reg<regs::C1Ahb3enr, RW> {
1498 unsafe { Reg::from_ptr(self.0.add(308usize)) }
1499 }
1500 #[doc = "RCC AHB1 Clock Register"]
1501 pub fn c1_ahb1enr(self) -> Reg<regs::C1Ahb1enr, RW> {
1502 unsafe { Reg::from_ptr(self.0.add(312usize)) }
1503 }
1504 #[doc = "RCC AHB2 Clock Register"]
1505 pub fn c1_ahb2enr(self) -> Reg<regs::C1Ahb2enr, RW> {
1506 unsafe { Reg::from_ptr(self.0.add(316usize)) }
1507 }
1508 #[doc = "RCC AHB4 Clock Register"]
1509 pub fn c1_ahb4enr(self) -> Reg<regs::C1Ahb4enr, RW> {
1510 unsafe { Reg::from_ptr(self.0.add(320usize)) }
1511 }
1512 #[doc = "RCC APB3 Clock Register"]
1513 pub fn c1_apb3enr(self) -> Reg<regs::C1Apb3enr, RW> {
1514 unsafe { Reg::from_ptr(self.0.add(324usize)) }
1515 }
1516 #[doc = "RCC APB1 Clock Register"]
1517 pub fn c1_apb1lenr(self) -> Reg<regs::C1Apb1lenr, RW> {
1518 unsafe { Reg::from_ptr(self.0.add(328usize)) }
1519 }
1520 #[doc = "RCC APB1 Clock Register"]
1521 pub fn c1_apb1henr(self) -> Reg<regs::C1Apb1henr, RW> {
1522 unsafe { Reg::from_ptr(self.0.add(332usize)) }
1523 }
1524 #[doc = "RCC APB2 Clock Register"]
1525 pub fn c1_apb2enr(self) -> Reg<regs::C1Apb2enr, RW> {
1526 unsafe { Reg::from_ptr(self.0.add(336usize)) }
1527 }
1528 #[doc = "RCC APB4 Clock Register"]
1529 pub fn c1_apb4enr(self) -> Reg<regs::C1Apb4enr, RW> {
1530 unsafe { Reg::from_ptr(self.0.add(340usize)) }
1531 }
1532 #[doc = "RCC AHB3 Sleep Clock Register"]
1533 pub fn c1_ahb3lpenr(self) -> Reg<regs::C1Ahb3lpenr, RW> {
1534 unsafe { Reg::from_ptr(self.0.add(348usize)) }
1535 }
1536 #[doc = "RCC AHB1 Sleep Clock Register"]
1537 pub fn c1_ahb1lpenr(self) -> Reg<regs::C1Ahb1lpenr, RW> {
1538 unsafe { Reg::from_ptr(self.0.add(352usize)) }
1539 }
1540 #[doc = "RCC AHB2 Sleep Clock Register"]
1541 pub fn c1_ahb2lpenr(self) -> Reg<regs::C1Ahb2lpenr, RW> {
1542 unsafe { Reg::from_ptr(self.0.add(356usize)) }
1543 }
1544 #[doc = "RCC AHB4 Sleep Clock Register"]
1545 pub fn c1_ahb4lpenr(self) -> Reg<regs::C1Ahb4lpenr, RW> {
1546 unsafe { Reg::from_ptr(self.0.add(360usize)) }
1547 }
1548 #[doc = "RCC APB3 Sleep Clock Register"]
1549 pub fn c1_apb3lpenr(self) -> Reg<regs::C1Apb3lpenr, RW> {
1550 unsafe { Reg::from_ptr(self.0.add(364usize)) }
1551 }
1552 #[doc = "RCC APB1 Low Sleep Clock Register"]
1553 pub fn c1_apb1llpenr(self) -> Reg<regs::C1Apb1llpenr, RW> {
1554 unsafe { Reg::from_ptr(self.0.add(368usize)) }
1555 }
1556 #[doc = "RCC APB1 High Sleep Clock Register"]
1557 pub fn c1_apb1hlpenr(self) -> Reg<regs::C1Apb1hlpenr, RW> {
1558 unsafe { Reg::from_ptr(self.0.add(372usize)) }
1559 }
1560 #[doc = "RCC APB2 Sleep Clock Register"]
1561 pub fn c1_apb2lpenr(self) -> Reg<regs::C1Apb2lpenr, RW> {
1562 unsafe { Reg::from_ptr(self.0.add(376usize)) }
1563 }
1564 #[doc = "RCC APB4 Sleep Clock Register"]
1565 pub fn c1_apb4lpenr(self) -> Reg<regs::C1Apb4lpenr, RW> {
1566 unsafe { Reg::from_ptr(self.0.add(380usize)) }
1567 }
1568 }
1569 pub mod vals {
1570 use crate::generic::*;
1571 #[repr(transparent)]
1572 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1573 pub struct Sai1sel(pub u8);
1574 impl Sai1sel {
1575 #[doc = "pll1_q selected as peripheral clock"]
1576 pub const PLL1_Q: Self = Self(0);
1577 #[doc = "pll2_p selected as peripheral clock"]
1578 pub const PLL2_P: Self = Self(0x01);
1579 #[doc = "pll3_p selected as peripheral clock"]
1580 pub const PLL3_P: Self = Self(0x02);
1581 #[doc = "I2S_CKIN selected as peripheral clock"]
1582 pub const I2S_CKIN: Self = Self(0x03);
1583 #[doc = "PER selected as peripheral clock"]
1584 pub const PER: Self = Self(0x04);
1585 }
1586 #[repr(transparent)]
1587 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1588 pub struct Swsr(pub u8);
1589 impl Swsr {
1590 #[doc = "HSI oscillator used as system clock"]
1591 pub const HSI: Self = Self(0);
1592 #[doc = "CSI oscillator used as system clock"]
1593 pub const CSI: Self = Self(0x01);
1594 #[doc = "HSE oscillator used as system clock"]
1595 pub const HSE: Self = Self(0x02);
1596 #[doc = "PLL1 used as system clock"]
1597 pub const PLL1: Self = Self(0x03);
1598 }
1599 #[repr(transparent)]
1600 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1601 pub struct Ww1rsc(pub u8);
1602 impl Ww1rsc {
1603 #[doc = "Clear WWDG1 scope control"]
1604 pub const CLEAR: Self = Self(0);
1605 #[doc = "Set WWDG1 scope control"]
1606 pub const SET: Self = Self(0x01);
1607 }
1608 #[repr(transparent)]
1609 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1610 pub struct C1Ahb3enrMdmaen(pub u8);
1611 impl C1Ahb3enrMdmaen {
1612 #[doc = "The selected clock is disabled"]
1613 pub const DISABLED: Self = Self(0);
1614 #[doc = "The selected clock is enabled"]
1615 pub const ENABLED: Self = Self(0x01);
1616 }
1617 #[repr(transparent)]
1618 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1619 pub struct Hsidiv(pub u8);
1620 impl Hsidiv {
1621 #[doc = "No division"]
1622 pub const DIV1: Self = Self(0);
1623 #[doc = "Division by 2"]
1624 pub const DIV2: Self = Self(0x01);
1625 #[doc = "Division by 4"]
1626 pub const DIV4: Self = Self(0x02);
1627 #[doc = "Division by 8"]
1628 pub const DIV8: Self = Self(0x03);
1629 }
1630 #[repr(transparent)]
1631 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1632 pub struct Ahb1enrDma1en(pub u8);
1633 impl Ahb1enrDma1en {
1634 #[doc = "The selected clock is disabled"]
1635 pub const DISABLED: Self = Self(0);
1636 #[doc = "The selected clock is enabled"]
1637 pub const ENABLED: Self = Self(0x01);
1638 }
1639 #[repr(transparent)]
1640 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1641 pub struct Ahb4lpenrGpioalpen(pub u8);
1642 impl Ahb4lpenrGpioalpen {
1643 #[doc = "The selected clock is disabled during csleep mode"]
1644 pub const DISABLED: Self = Self(0);
1645 #[doc = "The selected clock is enabled during csleep mode"]
1646 pub const ENABLED: Self = Self(0x01);
1647 }
1648 #[repr(transparent)]
1649 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1650 pub struct Ltdcrst(pub u8);
1651 impl Ltdcrst {
1652 #[doc = "Reset the selected module"]
1653 pub const RESET: Self = Self(0x01);
1654 }
1655 #[repr(transparent)]
1656 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1657 pub struct Apb4enrSyscfgen(pub u8);
1658 impl Apb4enrSyscfgen {
1659 #[doc = "The selected clock is disabled"]
1660 pub const DISABLED: Self = Self(0);
1661 #[doc = "The selected clock is enabled"]
1662 pub const ENABLED: Self = Self(0x01);
1663 }
1664 #[repr(transparent)]
1665 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1666 pub struct Divp1(pub u8);
1667 impl Divp1 {
1668 #[doc = "pll_p_ck = vco_ck"]
1669 pub const DIV1: Self = Self(0);
1670 #[doc = "pll_p_ck = vco_ck / 2"]
1671 pub const DIV2: Self = Self(0x01);
1672 #[doc = "pll_p_ck = vco_ck / 4"]
1673 pub const DIV4: Self = Self(0x03);
1674 #[doc = "pll_p_ck = vco_ck / 6"]
1675 pub const DIV6: Self = Self(0x05);
1676 #[doc = "pll_p_ck = vco_ck / 8"]
1677 pub const DIV8: Self = Self(0x07);
1678 #[doc = "pll_p_ck = vco_ck / 10"]
1679 pub const DIV10: Self = Self(0x09);
1680 #[doc = "pll_p_ck = vco_ck / 12"]
1681 pub const DIV12: Self = Self(0x0b);
1682 #[doc = "pll_p_ck = vco_ck / 14"]
1683 pub const DIV14: Self = Self(0x0d);
1684 #[doc = "pll_p_ck = vco_ck / 16"]
1685 pub const DIV16: Self = Self(0x0f);
1686 #[doc = "pll_p_ck = vco_ck / 18"]
1687 pub const DIV18: Self = Self(0x11);
1688 #[doc = "pll_p_ck = vco_ck / 20"]
1689 pub const DIV20: Self = Self(0x13);
1690 #[doc = "pll_p_ck = vco_ck / 22"]
1691 pub const DIV22: Self = Self(0x15);
1692 #[doc = "pll_p_ck = vco_ck / 24"]
1693 pub const DIV24: Self = Self(0x17);
1694 #[doc = "pll_p_ck = vco_ck / 26"]
1695 pub const DIV26: Self = Self(0x19);
1696 #[doc = "pll_p_ck = vco_ck / 28"]
1697 pub const DIV28: Self = Self(0x1b);
1698 #[doc = "pll_p_ck = vco_ck / 30"]
1699 pub const DIV30: Self = Self(0x1d);
1700 #[doc = "pll_p_ck = vco_ck / 32"]
1701 pub const DIV32: Self = Self(0x1f);
1702 #[doc = "pll_p_ck = vco_ck / 34"]
1703 pub const DIV34: Self = Self(0x21);
1704 #[doc = "pll_p_ck = vco_ck / 36"]
1705 pub const DIV36: Self = Self(0x23);
1706 #[doc = "pll_p_ck = vco_ck / 38"]
1707 pub const DIV38: Self = Self(0x25);
1708 #[doc = "pll_p_ck = vco_ck / 40"]
1709 pub const DIV40: Self = Self(0x27);
1710 #[doc = "pll_p_ck = vco_ck / 42"]
1711 pub const DIV42: Self = Self(0x29);
1712 #[doc = "pll_p_ck = vco_ck / 44"]
1713 pub const DIV44: Self = Self(0x2b);
1714 #[doc = "pll_p_ck = vco_ck / 46"]
1715 pub const DIV46: Self = Self(0x2d);
1716 #[doc = "pll_p_ck = vco_ck / 48"]
1717 pub const DIV48: Self = Self(0x2f);
1718 #[doc = "pll_p_ck = vco_ck / 50"]
1719 pub const DIV50: Self = Self(0x31);
1720 #[doc = "pll_p_ck = vco_ck / 52"]
1721 pub const DIV52: Self = Self(0x33);
1722 #[doc = "pll_p_ck = vco_ck / 54"]
1723 pub const DIV54: Self = Self(0x35);
1724 #[doc = "pll_p_ck = vco_ck / 56"]
1725 pub const DIV56: Self = Self(0x37);
1726 #[doc = "pll_p_ck = vco_ck / 58"]
1727 pub const DIV58: Self = Self(0x39);
1728 #[doc = "pll_p_ck = vco_ck / 60"]
1729 pub const DIV60: Self = Self(0x3b);
1730 #[doc = "pll_p_ck = vco_ck / 62"]
1731 pub const DIV62: Self = Self(0x3d);
1732 #[doc = "pll_p_ck = vco_ck / 64"]
1733 pub const DIV64: Self = Self(0x3f);
1734 #[doc = "pll_p_ck = vco_ck / 66"]
1735 pub const DIV66: Self = Self(0x41);
1736 #[doc = "pll_p_ck = vco_ck / 68"]
1737 pub const DIV68: Self = Self(0x43);
1738 #[doc = "pll_p_ck = vco_ck / 70"]
1739 pub const DIV70: Self = Self(0x45);
1740 #[doc = "pll_p_ck = vco_ck / 72"]
1741 pub const DIV72: Self = Self(0x47);
1742 #[doc = "pll_p_ck = vco_ck / 74"]
1743 pub const DIV74: Self = Self(0x49);
1744 #[doc = "pll_p_ck = vco_ck / 76"]
1745 pub const DIV76: Self = Self(0x4b);
1746 #[doc = "pll_p_ck = vco_ck / 78"]
1747 pub const DIV78: Self = Self(0x4d);
1748 #[doc = "pll_p_ck = vco_ck / 80"]
1749 pub const DIV80: Self = Self(0x4f);
1750 #[doc = "pll_p_ck = vco_ck / 82"]
1751 pub const DIV82: Self = Self(0x51);
1752 #[doc = "pll_p_ck = vco_ck / 84"]
1753 pub const DIV84: Self = Self(0x53);
1754 #[doc = "pll_p_ck = vco_ck / 86"]
1755 pub const DIV86: Self = Self(0x55);
1756 #[doc = "pll_p_ck = vco_ck / 88"]
1757 pub const DIV88: Self = Self(0x57);
1758 #[doc = "pll_p_ck = vco_ck / 90"]
1759 pub const DIV90: Self = Self(0x59);
1760 #[doc = "pll_p_ck = vco_ck / 92"]
1761 pub const DIV92: Self = Self(0x5b);
1762 #[doc = "pll_p_ck = vco_ck / 94"]
1763 pub const DIV94: Self = Self(0x5d);
1764 #[doc = "pll_p_ck = vco_ck / 96"]
1765 pub const DIV96: Self = Self(0x5f);
1766 #[doc = "pll_p_ck = vco_ck / 98"]
1767 pub const DIV98: Self = Self(0x61);
1768 #[doc = "pll_p_ck = vco_ck / 100"]
1769 pub const DIV100: Self = Self(0x63);
1770 #[doc = "pll_p_ck = vco_ck / 102"]
1771 pub const DIV102: Self = Self(0x65);
1772 #[doc = "pll_p_ck = vco_ck / 104"]
1773 pub const DIV104: Self = Self(0x67);
1774 #[doc = "pll_p_ck = vco_ck / 106"]
1775 pub const DIV106: Self = Self(0x69);
1776 #[doc = "pll_p_ck = vco_ck / 108"]
1777 pub const DIV108: Self = Self(0x6b);
1778 #[doc = "pll_p_ck = vco_ck / 110"]
1779 pub const DIV110: Self = Self(0x6d);
1780 #[doc = "pll_p_ck = vco_ck / 112"]
1781 pub const DIV112: Self = Self(0x6f);
1782 #[doc = "pll_p_ck = vco_ck / 114"]
1783 pub const DIV114: Self = Self(0x71);
1784 #[doc = "pll_p_ck = vco_ck / 116"]
1785 pub const DIV116: Self = Self(0x73);
1786 #[doc = "pll_p_ck = vco_ck / 118"]
1787 pub const DIV118: Self = Self(0x75);
1788 #[doc = "pll_p_ck = vco_ck / 120"]
1789 pub const DIV120: Self = Self(0x77);
1790 #[doc = "pll_p_ck = vco_ck / 122"]
1791 pub const DIV122: Self = Self(0x79);
1792 #[doc = "pll_p_ck = vco_ck / 124"]
1793 pub const DIV124: Self = Self(0x7b);
1794 #[doc = "pll_p_ck = vco_ck / 126"]
1795 pub const DIV126: Self = Self(0x7d);
1796 #[doc = "pll_p_ck = vco_ck / 128"]
1797 pub const DIV128: Self = Self(0x7f);
1798 }
1799 #[repr(transparent)]
1800 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1801 pub struct Hpre(pub u8);
1802 impl Hpre {
1803 #[doc = "sys_ck not divided"]
1804 pub const DIV1: Self = Self(0);
1805 #[doc = "sys_ck divided by 2"]
1806 pub const DIV2: Self = Self(0x08);
1807 #[doc = "sys_ck divided by 4"]
1808 pub const DIV4: Self = Self(0x09);
1809 #[doc = "sys_ck divided by 8"]
1810 pub const DIV8: Self = Self(0x0a);
1811 #[doc = "sys_ck divided by 16"]
1812 pub const DIV16: Self = Self(0x0b);
1813 #[doc = "sys_ck divided by 64"]
1814 pub const DIV64: Self = Self(0x0c);
1815 #[doc = "sys_ck divided by 128"]
1816 pub const DIV128: Self = Self(0x0d);
1817 #[doc = "sys_ck divided by 256"]
1818 pub const DIV256: Self = Self(0x0e);
1819 #[doc = "sys_ck divided by 512"]
1820 pub const DIV512: Self = Self(0x0f);
1821 }
1822 #[repr(transparent)]
1823 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1824 pub struct Timpre(pub u8);
1825 impl Timpre {
1826 #[doc = "Timer kernel clock equal to 2x pclk by default"]
1827 pub const DEFAULTX2: Self = Self(0);
1828 #[doc = "Timer kernel clock equal to 4x pclk by default"]
1829 pub const DEFAULTX4: Self = Self(0x01);
1830 }
1831 #[repr(transparent)]
1832 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1833 pub struct Apb3lpenrLtdclpen(pub u8);
1834 impl Apb3lpenrLtdclpen {
1835 #[doc = "The selected clock is disabled during csleep mode"]
1836 pub const DISABLED: Self = Self(0);
1837 #[doc = "The selected clock is enabled during csleep mode"]
1838 pub const ENABLED: Self = Self(0x01);
1839 }
1840 #[repr(transparent)]
1841 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1842 pub struct Pll1vcosel(pub u8);
1843 impl Pll1vcosel {
1844 #[doc = "VCO frequency range 192 to 836 MHz"]
1845 pub const WIDEVCO: Self = Self(0);
1846 #[doc = "VCO frequency range 150 to 420 MHz"]
1847 pub const MEDIUMVCO: Self = Self(0x01);
1848 }
1849 #[repr(transparent)]
1850 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1851 pub struct Ahb4enrGpioaen(pub u8);
1852 impl Ahb4enrGpioaen {
1853 #[doc = "The selected clock is disabled"]
1854 pub const DISABLED: Self = Self(0);
1855 #[doc = "The selected clock is enabled"]
1856 pub const ENABLED: Self = Self(0x01);
1857 }
1858 #[repr(transparent)]
1859 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1860 pub struct Rtcen(pub u8);
1861 impl Rtcen {
1862 #[doc = "RTC clock disabled"]
1863 pub const DISABLED: Self = Self(0);
1864 #[doc = "RTC clock enabled"]
1865 pub const ENABLED: Self = Self(0x01);
1866 }
1867 #[repr(transparent)]
1868 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1869 pub struct Bdrst(pub u8);
1870 impl Bdrst {
1871 #[doc = "Resets the entire VSW domain"]
1872 pub const RESET: Self = Self(0x01);
1873 }
1874 #[repr(transparent)]
1875 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1876 pub struct C1Ahb2lpenrDcmilpen(pub u8);
1877 impl C1Ahb2lpenrDcmilpen {
1878 #[doc = "The selected clock is disabled during csleep mode"]
1879 pub const DISABLED: Self = Self(0);
1880 #[doc = "The selected clock is enabled during csleep mode"]
1881 pub const ENABLED: Self = Self(0x01);
1882 }
1883 #[repr(transparent)]
1884 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1885 pub struct Sai4asel(pub u8);
1886 impl Sai4asel {
1887 #[doc = "pll1_q selected as peripheral clock"]
1888 pub const PLL1_Q: Self = Self(0);
1889 #[doc = "pll2_p selected as peripheral clock"]
1890 pub const PLL2_P: Self = Self(0x01);
1891 #[doc = "pll3_p selected as peripheral clock"]
1892 pub const PLL3_P: Self = Self(0x02);
1893 #[doc = "i2s_ckin selected as peripheral clock"]
1894 pub const I2S_CKIN: Self = Self(0x03);
1895 #[doc = "PER selected as peripheral clock"]
1896 pub const PER: Self = Self(0x04);
1897 }
1898 #[repr(transparent)]
1899 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1900 pub struct Cecsel(pub u8);
1901 impl Cecsel {
1902 #[doc = "LSE selected as peripheral clock"]
1903 pub const LSE: Self = Self(0);
1904 #[doc = "LSI selected as peripheral clock"]
1905 pub const LSI: Self = Self(0x01);
1906 #[doc = "csi_ker selected as peripheral clock"]
1907 pub const CSI_KER: Self = Self(0x02);
1908 }
1909 #[repr(transparent)]
1910 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1911 pub struct Hsirdyr(pub u8);
1912 impl Hsirdyr {
1913 #[doc = "Clock not ready"]
1914 pub const NOTREADY: Self = Self(0);
1915 #[doc = "Clock ready"]
1916 pub const READY: Self = Self(0x01);
1917 }
1918 #[repr(transparent)]
1919 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1920 pub struct D1ppre(pub u8);
1921 impl D1ppre {
1922 #[doc = "rcc_hclk not divided"]
1923 pub const DIV1: Self = Self(0);
1924 #[doc = "rcc_hclk divided by 2"]
1925 pub const DIV2: Self = Self(0x04);
1926 #[doc = "rcc_hclk divided by 4"]
1927 pub const DIV4: Self = Self(0x05);
1928 #[doc = "rcc_hclk divided by 8"]
1929 pub const DIV8: Self = Self(0x06);
1930 #[doc = "rcc_hclk divided by 16"]
1931 pub const DIV16: Self = Self(0x07);
1932 }
1933 #[repr(transparent)]
1934 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1935 pub struct Apb1llpenrTim2lpen(pub u8);
1936 impl Apb1llpenrTim2lpen {
1937 #[doc = "The selected clock is disabled during csleep mode"]
1938 pub const DISABLED: Self = Self(0);
1939 #[doc = "The selected clock is enabled during csleep mode"]
1272 pub const ENABLED: Self = Self(0x01); 1940 pub const ENABLED: Self = Self(0x01);
1273 } 1941 }
1274 #[repr(transparent)] 1942 #[repr(transparent)]
1275 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 1943 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1944 pub struct Apb1henrCrsen(pub u8);
1945 impl Apb1henrCrsen {
1946 #[doc = "The selected clock is disabled"]
1947 pub const DISABLED: Self = Self(0);
1948 #[doc = "The selected clock is enabled"]
1949 pub const ENABLED: Self = Self(0x01);
1950 }
1951 #[repr(transparent)]
1952 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1953 pub struct Lpuart1sel(pub u8);
1954 impl Lpuart1sel {
1955 #[doc = "rcc_pclk_d3 selected as peripheral clock"]
1956 pub const RCC_PCLK_D3: Self = Self(0);
1957 #[doc = "pll2_q selected as peripheral clock"]
1958 pub const PLL2_Q: Self = Self(0x01);
1959 #[doc = "pll3_q selected as peripheral clock"]
1960 pub const PLL3_Q: Self = Self(0x02);
1961 #[doc = "hsi_ker selected as peripheral clock"]
1962 pub const HSI_KER: Self = Self(0x03);
1963 #[doc = "csi_ker selected as peripheral clock"]
1964 pub const CSI_KER: Self = Self(0x04);
1965 #[doc = "LSE selected as peripheral clock"]
1966 pub const LSE: Self = Self(0x05);
1967 }
1968 #[repr(transparent)]
1969 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1970 pub struct Fdcansel(pub u8);
1971 impl Fdcansel {
1972 #[doc = "HSE selected as peripheral clock"]
1973 pub const HSE: Self = Self(0);
1974 #[doc = "pll1_q selected as peripheral clock"]
1975 pub const PLL1_Q: Self = Self(0x01);
1976 #[doc = "pll2_q selected as peripheral clock"]
1977 pub const PLL2_Q: Self = Self(0x02);
1978 }
1979 #[repr(transparent)]
1980 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1981 pub struct Hsidivfr(pub u8);
1982 impl Hsidivfr {
1983 #[doc = "New HSIDIV ratio has not yet propagated to hsi_ck"]
1984 pub const NOTPROPAGATED: Self = Self(0);
1985 #[doc = "HSIDIV ratio has propagated to hsi_ck"]
1986 pub const PROPAGATED: Self = Self(0x01);
1987 }
1988 #[repr(transparent)]
1989 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1990 pub struct Lserdyr(pub u8);
1991 impl Lserdyr {
1992 #[doc = "LSE oscillator not ready"]
1993 pub const NOTREADY: Self = Self(0);
1994 #[doc = "LSE oscillator ready"]
1995 pub const READY: Self = Self(0x01);
1996 }
1997 #[repr(transparent)]
1998 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
1999 pub struct C1Ahb3lpenrMdmalpen(pub u8);
2000 impl C1Ahb3lpenrMdmalpen {
2001 #[doc = "The selected clock is disabled during csleep mode"]
2002 pub const DISABLED: Self = Self(0);
2003 #[doc = "The selected clock is enabled during csleep mode"]
2004 pub const ENABLED: Self = Self(0x01);
2005 }
2006 #[repr(transparent)]
2007 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2008 pub struct RsrCpurstfr(pub u8);
2009 impl RsrCpurstfr {
2010 #[doc = "No reset occoured for block"]
2011 pub const NORESETOCCOURED: Self = Self(0);
2012 #[doc = "Reset occoured for block"]
2013 pub const RESETOCCOURRED: Self = Self(0x01);
2014 }
2015 #[repr(transparent)]
2016 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2017 pub struct C1Apb4lpenrSyscfglpen(pub u8);
2018 impl C1Apb4lpenrSyscfglpen {
2019 #[doc = "The selected clock is disabled during csleep mode"]
2020 pub const DISABLED: Self = Self(0);
2021 #[doc = "The selected clock is enabled during csleep mode"]
2022 pub const ENABLED: Self = Self(0x01);
2023 }
2024 #[repr(transparent)]
2025 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2026 pub struct C1Ahb2enrDcmien(pub u8);
2027 impl C1Ahb2enrDcmien {
2028 #[doc = "The selected clock is disabled"]
2029 pub const DISABLED: Self = Self(0);
2030 #[doc = "The selected clock is enabled"]
2031 pub const ENABLED: Self = Self(0x01);
2032 }
2033 #[repr(transparent)]
2034 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2035 pub struct C1Apb1lenrTim2en(pub u8);
2036 impl C1Apb1lenrTim2en {
2037 #[doc = "The selected clock is disabled"]
2038 pub const DISABLED: Self = Self(0);
2039 #[doc = "The selected clock is enabled"]
2040 pub const ENABLED: Self = Self(0x01);
2041 }
2042 #[repr(transparent)]
2043 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2044 pub struct C1Apb4enrSyscfgen(pub u8);
2045 impl C1Apb4enrSyscfgen {
2046 #[doc = "The selected clock is disabled"]
2047 pub const DISABLED: Self = Self(0);
2048 #[doc = "The selected clock is enabled"]
2049 pub const ENABLED: Self = Self(0x01);
2050 }
2051 #[repr(transparent)]
2052 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2053 pub struct Hsebyp(pub u8);
2054 impl Hsebyp {
2055 #[doc = "HSE crystal oscillator not bypassed"]
2056 pub const NOTBYPASSED: Self = Self(0);
2057 #[doc = "HSE crystal oscillator bypassed with external clock"]
2058 pub const BYPASSED: Self = Self(0x01);
2059 }
2060 #[repr(transparent)]
2061 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2062 pub struct Apb2enrTim1en(pub u8);
2063 impl Apb2enrTim1en {
2064 #[doc = "The selected clock is disabled"]
2065 pub const DISABLED: Self = Self(0);
2066 #[doc = "The selected clock is enabled"]
2067 pub const ENABLED: Self = Self(0x01);
2068 }
2069 #[repr(transparent)]
2070 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2071 pub struct Rngsel(pub u8);
2072 impl Rngsel {
2073 #[doc = "HSI48 selected as peripheral clock"]
2074 pub const HSI48: Self = Self(0);
2075 #[doc = "pll1_q selected as peripheral clock"]
2076 pub const PLL1_Q: Self = Self(0x01);
2077 #[doc = "LSE selected as peripheral clock"]
2078 pub const LSE: Self = Self(0x02);
2079 #[doc = "LSI selected as peripheral clock"]
2080 pub const LSI: Self = Self(0x03);
2081 }
2082 #[repr(transparent)]
2083 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2084 pub struct Gpioarst(pub u8);
2085 impl Gpioarst {
2086 #[doc = "Reset the selected module"]
2087 pub const RESET: Self = Self(0x01);
2088 }
2089 #[repr(transparent)]
2090 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2091 pub struct C1Apb3enrLtdcen(pub u8);
2092 impl C1Apb3enrLtdcen {
2093 #[doc = "The selected clock is disabled"]
2094 pub const DISABLED: Self = Self(0);
2095 #[doc = "The selected clock is enabled"]
2096 pub const ENABLED: Self = Self(0x01);
2097 }
2098 #[repr(transparent)]
2099 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2100 pub struct Lsedrv(pub u8);
2101 impl Lsedrv {
2102 #[doc = "Lowest LSE oscillator driving capability"]
2103 pub const LOWEST: Self = Self(0);
2104 #[doc = "Medium low LSE oscillator driving capability"]
2105 pub const MEDIUMLOW: Self = Self(0x01);
2106 #[doc = "Medium high LSE oscillator driving capability"]
2107 pub const MEDIUMHIGH: Self = Self(0x02);
2108 #[doc = "Highest LSE oscillator driving capability"]
2109 pub const HIGHEST: Self = Self(0x03);
2110 }
2111 #[repr(transparent)]
2112 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2113 pub struct Lsecsson(pub u8);
2114 impl Lsecsson {
2115 #[doc = "Clock security system on 32 kHz oscillator off"]
2116 pub const SECURITYOFF: Self = Self(0);
2117 #[doc = "Clock security system on 32 kHz oscillator on"]
2118 pub const SECURITYON: Self = Self(0x01);
2119 }
2120 #[repr(transparent)]
2121 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2122 pub struct C1Apb1llpenrTim2lpen(pub u8);
2123 impl C1Apb1llpenrTim2lpen {
2124 #[doc = "The selected clock is disabled during csleep mode"]
2125 pub const DISABLED: Self = Self(0);
2126 #[doc = "The selected clock is enabled during csleep mode"]
2127 pub const ENABLED: Self = Self(0x01);
2128 }
2129 #[repr(transparent)]
2130 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2131 pub struct Ckpersel(pub u8);
2132 impl Ckpersel {
2133 #[doc = "HSI selected as peripheral clock"]
2134 pub const HSI: Self = Self(0);
2135 #[doc = "CSI selected as peripheral clock"]
2136 pub const CSI: Self = Self(0x01);
2137 #[doc = "HSE selected as peripheral clock"]
2138 pub const HSE: Self = Self(0x02);
2139 }
2140 #[repr(transparent)]
2141 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2142 pub struct Ahb1lpenrDma1lpen(pub u8);
2143 impl Ahb1lpenrDma1lpen {
2144 #[doc = "The selected clock is disabled during csleep mode"]
2145 pub const DISABLED: Self = Self(0);
2146 #[doc = "The selected clock is enabled during csleep mode"]
2147>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
2148 pub const ENABLED: Self = Self(0x01);
2149 }
2150 #[repr(transparent)]
2151 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2152<<<<<<< HEAD
1276 pub struct Pl(pub u8); 2153 pub struct Pl(pub u8);
1277 impl Pl { 2154 impl Pl {
1278 #[doc = "Low priority"] 2155 #[doc = "Low priority"]
@@ -1734,9 +2611,764 @@ pub mod timer_v1 {
1734 } 2611 }
1735 #[doc = "Update DMA request enable"] 2612 #[doc = "Update DMA request enable"]
1736 pub const fn ude(&self) -> bool { 2613 pub const fn ude(&self) -> bool {
2614=======
2615 pub struct Lsecssdr(pub u8);
2616 impl Lsecssdr {
2617 #[doc = "No failure detected on 32 kHz oscillator"]
2618 pub const NOFAILURE: Self = Self(0);
2619 #[doc = "Failure detected on 32 kHz oscillator"]
2620 pub const FAILURE: Self = Self(0x01);
2621 }
2622 #[repr(transparent)]
2623 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2624 pub struct Syscfgrst(pub u8);
2625 impl Syscfgrst {
2626 #[doc = "Reset the selected module"]
2627 pub const RESET: Self = Self(0x01);
2628 }
2629 #[repr(transparent)]
2630 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2631 pub struct Pll1fracen(pub u8);
2632 impl Pll1fracen {
2633 #[doc = "Reset latch to tranfer FRACN to the Sigma-Delta modulator"]
2634 pub const RESET: Self = Self(0);
2635 #[doc = "Set latch to tranfer FRACN to the Sigma-Delta modulator"]
2636 pub const SET: Self = Self(0x01);
2637 }
2638 #[repr(transparent)]
2639 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2640 pub struct Mco2(pub u8);
2641 impl Mco2 {
2642 #[doc = "System clock selected for micro-controller clock output"]
2643 pub const SYSCLK: Self = Self(0);
2644 #[doc = "pll2_p selected for micro-controller clock output"]
2645 pub const PLL2_P: Self = Self(0x01);
2646 #[doc = "HSE selected for micro-controller clock output"]
2647 pub const HSE: Self = Self(0x02);
2648 #[doc = "pll1_p selected for micro-controller clock output"]
2649 pub const PLL1_P: Self = Self(0x03);
2650 #[doc = "CSI selected for micro-controller clock output"]
2651 pub const CSI: Self = Self(0x04);
2652 #[doc = "LSI selected for micro-controller clock output"]
2653 pub const LSI: Self = Self(0x05);
2654 }
2655 #[repr(transparent)]
2656 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2657 pub struct D3ppre(pub u8);
2658 impl D3ppre {
2659 #[doc = "rcc_hclk not divided"]
2660 pub const DIV1: Self = Self(0);
2661 #[doc = "rcc_hclk divided by 2"]
2662 pub const DIV2: Self = Self(0x04);
2663 #[doc = "rcc_hclk divided by 4"]
2664 pub const DIV4: Self = Self(0x05);
2665 #[doc = "rcc_hclk divided by 8"]
2666 pub const DIV8: Self = Self(0x06);
2667 #[doc = "rcc_hclk divided by 16"]
2668 pub const DIV16: Self = Self(0x07);
2669 }
2670 #[repr(transparent)]
2671 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2672 pub struct Apb1hlpenrCrslpen(pub u8);
2673 impl Apb1hlpenrCrslpen {
2674 #[doc = "The selected clock is disabled during csleep mode"]
2675 pub const DISABLED: Self = Self(0);
2676 #[doc = "The selected clock is enabled during csleep mode"]
2677 pub const ENABLED: Self = Self(0x01);
2678 }
2679 #[repr(transparent)]
2680 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2681 pub struct Fmcsel(pub u8);
2682 impl Fmcsel {
2683 #[doc = "rcc_hclk3 selected as peripheral clock"]
2684 pub const RCC_HCLK3: Self = Self(0);
2685 #[doc = "pll1_q selected as peripheral clock"]
2686 pub const PLL1_Q: Self = Self(0x01);
2687 #[doc = "pll2_r selected as peripheral clock"]
2688 pub const PLL2_R: Self = Self(0x02);
2689 #[doc = "PER selected as peripheral clock"]
2690 pub const PER: Self = Self(0x03);
2691 }
2692 #[repr(transparent)]
2693 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2694 pub struct Usart16sel(pub u8);
2695 impl Usart16sel {
2696 #[doc = "rcc_pclk2 selected as peripheral clock"]
2697 pub const RCC_PCLK2: Self = Self(0);
2698 #[doc = "pll2_q selected as peripheral clock"]
2699 pub const PLL2_Q: Self = Self(0x01);
2700 #[doc = "pll3_q selected as peripheral clock"]
2701 pub const PLL3_Q: Self = Self(0x02);
2702 #[doc = "hsi_ker selected as peripheral clock"]
2703 pub const HSI_KER: Self = Self(0x03);
2704 #[doc = "csi_ker selected as peripheral clock"]
2705 pub const CSI_KER: Self = Self(0x04);
2706 #[doc = "LSE selected as peripheral clock"]
2707 pub const LSE: Self = Self(0x05);
2708 }
2709 #[repr(transparent)]
2710 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2711 pub struct Tim2rst(pub u8);
2712 impl Tim2rst {
2713 #[doc = "Reset the selected module"]
2714 pub const RESET: Self = Self(0x01);
2715 }
2716 #[repr(transparent)]
2717 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2718 pub struct Ahb2lpenrDcmilpen(pub u8);
2719 impl Ahb2lpenrDcmilpen {
2720 #[doc = "The selected clock is disabled during csleep mode"]
2721 pub const DISABLED: Self = Self(0);
2722 #[doc = "The selected clock is enabled during csleep mode"]
2723 pub const ENABLED: Self = Self(0x01);
2724 }
2725 #[repr(transparent)]
2726 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2727 pub struct Lptim1sel(pub u8);
2728 impl Lptim1sel {
2729 #[doc = "rcc_pclk1 selected as peripheral clock"]
2730 pub const RCC_PCLK1: Self = Self(0);
2731 #[doc = "pll2_p selected as peripheral clock"]
2732 pub const PLL2_P: Self = Self(0x01);
2733 #[doc = "pll3_r selected as peripheral clock"]
2734 pub const PLL3_R: Self = Self(0x02);
2735 #[doc = "LSE selected as peripheral clock"]
2736 pub const LSE: Self = Self(0x03);
2737 #[doc = "LSI selected as peripheral clock"]
2738 pub const LSI: Self = Self(0x04);
2739 #[doc = "PER selected as peripheral clock"]
2740 pub const PER: Self = Self(0x05);
2741 }
2742 #[repr(transparent)]
2743 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2744 pub struct Lptim2sel(pub u8);
2745 impl Lptim2sel {
2746 #[doc = "rcc_pclk4 selected as peripheral clock"]
2747 pub const RCC_PCLK4: Self = Self(0);
2748 #[doc = "pll2_p selected as peripheral clock"]
2749 pub const PLL2_P: Self = Self(0x01);
2750 #[doc = "pll3_r selected as peripheral clock"]
2751 pub const PLL3_R: Self = Self(0x02);
2752 #[doc = "LSE selected as peripheral clock"]
2753 pub const LSE: Self = Self(0x03);
2754 #[doc = "LSI selected as peripheral clock"]
2755 pub const LSI: Self = Self(0x04);
2756 #[doc = "PER selected as peripheral clock"]
2757 pub const PER: Self = Self(0x05);
2758 }
2759 #[repr(transparent)]
2760 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2761 pub struct Lsirdyie(pub u8);
2762 impl Lsirdyie {
2763 #[doc = "Interrupt disabled"]
2764 pub const DISABLED: Self = Self(0);
2765 #[doc = "Interrupt enabled"]
2766 pub const ENABLED: Self = Self(0x01);
2767 }
2768 #[repr(transparent)]
2769 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2770 pub struct C1Apb1hlpenrCrslpen(pub u8);
2771 impl C1Apb1hlpenrCrslpen {
2772 #[doc = "The selected clock is disabled during csleep mode"]
2773 pub const DISABLED: Self = Self(0);
2774 #[doc = "The selected clock is enabled during csleep mode"]
2775 pub const ENABLED: Self = Self(0x01);
2776 }
2777 #[repr(transparent)]
2778 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2779 pub struct C1Ahb1lpenrDma1lpen(pub u8);
2780 impl C1Ahb1lpenrDma1lpen {
2781 #[doc = "The selected clock is disabled during csleep mode"]
2782 pub const DISABLED: Self = Self(0);
2783 #[doc = "The selected clock is enabled during csleep mode"]
2784 pub const ENABLED: Self = Self(0x01);
2785 }
2786 #[repr(transparent)]
2787 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2788 pub struct Apb2lpenrTim1lpen(pub u8);
2789 impl Apb2lpenrTim1lpen {
2790 #[doc = "The selected clock is disabled during csleep mode"]
2791 pub const DISABLED: Self = Self(0);
2792 #[doc = "The selected clock is enabled during csleep mode"]
2793 pub const ENABLED: Self = Self(0x01);
2794 }
2795 #[repr(transparent)]
2796 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2797 pub struct Spi6sel(pub u8);
2798 impl Spi6sel {
2799 #[doc = "rcc_pclk4 selected as peripheral clock"]
2800 pub const RCC_PCLK4: Self = Self(0);
2801 #[doc = "pll2_q selected as peripheral clock"]
2802 pub const PLL2_Q: Self = Self(0x01);
2803 #[doc = "pll3_q selected as peripheral clock"]
2804 pub const PLL3_Q: Self = Self(0x02);
2805 #[doc = "hsi_ker selected as peripheral clock"]
2806 pub const HSI_KER: Self = Self(0x03);
2807 #[doc = "csi_ker selected as peripheral clock"]
2808 pub const CSI_KER: Self = Self(0x04);
2809 #[doc = "HSE selected as peripheral clock"]
2810 pub const HSE: Self = Self(0x05);
2811 }
2812 #[repr(transparent)]
2813 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2814 pub struct Bdmaamen(pub u8);
2815 impl Bdmaamen {
2816 #[doc = "Clock disabled in autonomous mode"]
2817 pub const DISABLED: Self = Self(0);
2818 #[doc = "Clock enabled in autonomous mode"]
2819 pub const ENABLED: Self = Self(0x01);
2820 }
2821 #[repr(transparent)]
2822 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2823 pub struct Lseon(pub u8);
2824 impl Lseon {
2825 #[doc = "LSE oscillator Off"]
2826 pub const OFF: Self = Self(0);
2827 #[doc = "LSE oscillator On"]
2828 pub const ON: Self = Self(0x01);
2829 }
2830 #[repr(transparent)]
2831 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2832 pub struct Apb1lenrTim2en(pub u8);
2833 impl Apb1lenrTim2en {
2834 #[doc = "The selected clock is disabled"]
2835 pub const DISABLED: Self = Self(0);
2836 #[doc = "The selected clock is enabled"]
2837 pub const ENABLED: Self = Self(0x01);
2838 }
2839 #[repr(transparent)]
2840 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2841 pub struct Lsebyp(pub u8);
2842 impl Lsebyp {
2843 #[doc = "LSE crystal oscillator not bypassed"]
2844 pub const NOTBYPASSED: Self = Self(0);
2845 #[doc = "LSE crystal oscillator bypassed with external clock"]
2846 pub const BYPASSED: Self = Self(0x01);
2847 }
2848 #[repr(transparent)]
2849 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2850 pub struct Sdmmcsel(pub u8);
2851 impl Sdmmcsel {
2852 #[doc = "pll1_q selected as peripheral clock"]
2853 pub const PLL1_Q: Self = Self(0);
2854 #[doc = "pll2_r selected as peripheral clock"]
2855 pub const PLL2_R: Self = Self(0x01);
2856 }
2857 #[repr(transparent)]
2858 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2859 pub struct C1RsrRmvf(pub u8);
2860 impl C1RsrRmvf {
2861 #[doc = "Not clearing the the reset flags"]
2862 pub const NOTACTIVE: Self = Self(0);
2863 #[doc = "Clear the reset flags"]
2864 pub const CLEAR: Self = Self(0x01);
2865 }
2866 #[repr(transparent)]
2867 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2868 pub struct Pllsrc(pub u8);
2869 impl Pllsrc {
2870 #[doc = "HSI selected as PLL clock"]
2871 pub const HSI: Self = Self(0);
2872 #[doc = "CSI selected as PLL clock"]
2873 pub const CSI: Self = Self(0x01);
2874 #[doc = "HSE selected as PLL clock"]
2875 pub const HSE: Self = Self(0x02);
2876 #[doc = "No clock sent to DIVMx dividers and PLLs"]
2877 pub const NONE: Self = Self(0x03);
2878 }
2879 #[repr(transparent)]
2880 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2881 pub struct Dfsdm1sel(pub u8);
2882 impl Dfsdm1sel {
2883 #[doc = "rcc_pclk2 selected as peripheral clock"]
2884 pub const RCC_PCLK2: Self = Self(0);
2885 #[doc = "System clock selected as peripheral clock"]
2886 pub const SYS: Self = Self(0x01);
2887 }
2888 #[repr(transparent)]
2889 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2890 pub struct C1Ahb4enrGpioaen(pub u8);
2891 impl C1Ahb4enrGpioaen {
2892 #[doc = "The selected clock is disabled"]
2893 pub const DISABLED: Self = Self(0);
2894 #[doc = "The selected clock is enabled"]
2895 pub const ENABLED: Self = Self(0x01);
2896 }
2897 #[repr(transparent)]
2898 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2899 pub struct Crsrst(pub u8);
2900 impl Crsrst {
2901 #[doc = "Reset the selected module"]
2902 pub const RESET: Self = Self(0x01);
2903 }
2904 #[repr(transparent)]
2905 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2906 pub struct Camitfrst(pub u8);
2907 impl Camitfrst {
2908 #[doc = "Reset the selected module"]
2909 pub const RESET: Self = Self(0x01);
2910 }
2911 #[repr(transparent)]
2912 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2913 pub struct Apb4lpenrSyscfglpen(pub u8);
2914 impl Apb4lpenrSyscfglpen {
2915 #[doc = "The selected clock is disabled during csleep mode"]
2916 pub const DISABLED: Self = Self(0);
2917 #[doc = "The selected clock is enabled during csleep mode"]
2918 pub const ENABLED: Self = Self(0x01);
2919 }
2920 #[repr(transparent)]
2921 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2922 pub struct Lsirdyr(pub u8);
2923 impl Lsirdyr {
2924 #[doc = "LSI oscillator not ready"]
2925 pub const NOTREADY: Self = Self(0);
2926 #[doc = "LSI oscillator ready"]
2927 pub const READY: Self = Self(0x01);
2928 }
2929 #[repr(transparent)]
2930 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2931 pub struct Dma1rst(pub u8);
2932 impl Dma1rst {
2933 #[doc = "Reset the selected module"]
2934 pub const RESET: Self = Self(0x01);
2935 }
2936 #[repr(transparent)]
2937 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2938 pub struct Swpsel(pub u8);
2939 impl Swpsel {
2940 #[doc = "pclk selected as peripheral clock"]
2941 pub const PCLK: Self = Self(0);
2942 #[doc = "hsi_ker selected as peripheral clock"]
2943 pub const HSI_KER: Self = Self(0x01);
2944 }
2945 #[repr(transparent)]
2946 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2947 pub struct C1RsrCpurstfr(pub u8);
2948 impl C1RsrCpurstfr {
2949 #[doc = "No reset occoured for block"]
2950 pub const NORESETOCCOURED: Self = Self(0);
2951 #[doc = "Reset occoured for block"]
2952 pub const RESETOCCOURRED: Self = Self(0x01);
2953 }
2954 #[repr(transparent)]
2955 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2956 pub struct I2c123sel(pub u8);
2957 impl I2c123sel {
2958 #[doc = "rcc_pclk1 selected as peripheral clock"]
2959 pub const RCC_PCLK1: Self = Self(0);
2960 #[doc = "pll3_r selected as peripheral clock"]
2961 pub const PLL3_R: Self = Self(0x01);
2962 #[doc = "hsi_ker selected as peripheral clock"]
2963 pub const HSI_KER: Self = Self(0x02);
2964 #[doc = "csi_ker selected as peripheral clock"]
2965 pub const CSI_KER: Self = Self(0x03);
2966 }
2967 #[repr(transparent)]
2968 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2969 pub struct Ahb3enrMdmaen(pub u8);
2970 impl Ahb3enrMdmaen {
2971 #[doc = "The selected clock is disabled"]
2972 pub const DISABLED: Self = Self(0);
2973 #[doc = "The selected clock is enabled"]
2974 pub const ENABLED: Self = Self(0x01);
2975 }
2976 #[repr(transparent)]
2977 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2978 pub struct Usbsel(pub u8);
2979 impl Usbsel {
2980 #[doc = "Disable the kernel clock"]
2981 pub const DISABLE: Self = Self(0);
2982 #[doc = "pll1_q selected as peripheral clock"]
2983 pub const PLL1_Q: Self = Self(0x01);
2984 #[doc = "pll3_q selected as peripheral clock"]
2985 pub const PLL3_Q: Self = Self(0x02);
2986 #[doc = "HSI48 selected as peripheral clock"]
2987 pub const HSI48: Self = Self(0x03);
2988 }
2989 #[repr(transparent)]
2990 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
2991 pub struct Ahb2enrDcmien(pub u8);
2992 impl Ahb2enrDcmien {
2993 #[doc = "The selected clock is disabled"]
2994 pub const DISABLED: Self = Self(0);
2995 #[doc = "The selected clock is enabled"]
2996 pub const ENABLED: Self = Self(0x01);
2997 }
2998 #[repr(transparent)]
2999 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3000 pub struct Divp1en(pub u8);
3001 impl Divp1en {
3002 #[doc = "Clock ouput is disabled"]
3003 pub const DISABLED: Self = Self(0);
3004 #[doc = "Clock output is enabled"]
3005 pub const ENABLED: Self = Self(0x01);
3006 }
3007 #[repr(transparent)]
3008 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3009 pub struct Spdifsel(pub u8);
3010 impl Spdifsel {
3011 #[doc = "pll1_q selected as peripheral clock"]
3012 pub const PLL1_Q: Self = Self(0);
3013 #[doc = "pll2_r selected as peripheral clock"]
3014 pub const PLL2_R: Self = Self(0x01);
3015 #[doc = "pll3_r selected as peripheral clock"]
3016 pub const PLL3_R: Self = Self(0x02);
3017 #[doc = "hsi_ker selected as peripheral clock"]
3018 pub const HSI_KER: Self = Self(0x03);
3019 }
3020 #[repr(transparent)]
3021 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3022 pub struct C1Apb3lpenrLtdclpen(pub u8);
3023 impl C1Apb3lpenrLtdclpen {
3024 #[doc = "The selected clock is disabled during csleep mode"]
3025 pub const DISABLED: Self = Self(0);
3026 #[doc = "The selected clock is enabled during csleep mode"]
3027 pub const ENABLED: Self = Self(0x01);
3028 }
3029 #[repr(transparent)]
3030 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3031 pub struct Sw(pub u8);
3032 impl Sw {
3033 #[doc = "HSI selected as system clock"]
3034 pub const HSI: Self = Self(0);
3035 #[doc = "CSI selected as system clock"]
3036 pub const CSI: Self = Self(0x01);
3037 #[doc = "HSE selected as system clock"]
3038 pub const HSE: Self = Self(0x02);
3039 #[doc = "PLL1 selected as system clock"]
3040 pub const PLL1: Self = Self(0x03);
3041 }
3042 #[repr(transparent)]
3043 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3044 pub struct I2c4sel(pub u8);
3045 impl I2c4sel {
3046 #[doc = "rcc_pclk4 selected as peripheral clock"]
3047 pub const RCC_PCLK4: Self = Self(0);
3048 #[doc = "pll3_r selected as peripheral clock"]
3049 pub const PLL3_R: Self = Self(0x01);
3050 #[doc = "hsi_ker selected as peripheral clock"]
3051 pub const HSI_KER: Self = Self(0x02);
3052 #[doc = "csi_ker selected as peripheral clock"]
3053 pub const CSI_KER: Self = Self(0x03);
3054 }
3055 #[repr(transparent)]
3056 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3057 pub struct Pll1rge(pub u8);
3058 impl Pll1rge {
3059 #[doc = "Frequency is between 1 and 2 MHz"]
3060 pub const RANGE1: Self = Self(0);
3061 #[doc = "Frequency is between 2 and 4 MHz"]
3062 pub const RANGE2: Self = Self(0x01);
3063 #[doc = "Frequency is between 4 and 8 MHz"]
3064 pub const RANGE4: Self = Self(0x02);
3065 #[doc = "Frequency is between 8 and 16 MHz"]
3066 pub const RANGE8: Self = Self(0x03);
3067 }
3068 #[repr(transparent)]
3069 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3070 pub struct C1Apb1henrCrsen(pub u8);
3071 impl C1Apb1henrCrsen {
3072 #[doc = "The selected clock is disabled"]
3073 pub const DISABLED: Self = Self(0);
3074 #[doc = "The selected clock is enabled"]
3075 pub const ENABLED: Self = Self(0x01);
3076 }
3077 #[repr(transparent)]
3078 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3079 pub struct Stopwuck(pub u8);
3080 impl Stopwuck {
3081 #[doc = "HSI selected as wake up clock from system Stop"]
3082 pub const HSI: Self = Self(0);
3083 #[doc = "CSI selected as wake up clock from system Stop"]
3084 pub const CSI: Self = Self(0x01);
3085 }
3086 #[repr(transparent)]
3087 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3088 pub struct Mco1(pub u8);
3089 impl Mco1 {
3090 #[doc = "HSI selected for micro-controller clock output"]
3091 pub const HSI: Self = Self(0);
3092 #[doc = "LSE selected for micro-controller clock output"]
3093 pub const LSE: Self = Self(0x01);
3094 #[doc = "HSE selected for micro-controller clock output"]
3095 pub const HSE: Self = Self(0x02);
3096 #[doc = "pll1_q selected for micro-controller clock output"]
3097 pub const PLL1_Q: Self = Self(0x03);
3098 #[doc = "HSI48 selected for micro-controller clock output"]
3099 pub const HSI48: Self = Self(0x04);
3100 }
3101 #[repr(transparent)]
3102 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3103 pub struct Lsion(pub u8);
3104 impl Lsion {
3105 #[doc = "LSI oscillator Off"]
3106 pub const OFF: Self = Self(0);
3107 #[doc = "LSI oscillator On"]
3108 pub const ON: Self = Self(0x01);
3109 }
3110 #[repr(transparent)]
3111 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3112 pub struct Tim1rst(pub u8);
3113 impl Tim1rst {
3114 #[doc = "Reset the selected module"]
3115 pub const RESET: Self = Self(0x01);
3116 }
3117 #[repr(transparent)]
3118 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3119 pub struct C1Ahb1enrDma1en(pub u8);
3120 impl C1Ahb1enrDma1en {
3121 #[doc = "The selected clock is disabled"]
3122 pub const DISABLED: Self = Self(0);
3123 #[doc = "The selected clock is enabled"]
3124 pub const ENABLED: Self = Self(0x01);
3125 }
3126 #[repr(transparent)]
3127 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3128 pub struct Lsirdyc(pub u8);
3129 impl Lsirdyc {
3130 #[doc = "Clear interrupt flag"]
3131 pub const CLEAR: Self = Self(0x01);
3132 }
3133 #[repr(transparent)]
3134 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3135 pub struct Rtcsel(pub u8);
3136 impl Rtcsel {
3137 #[doc = "No clock"]
3138 pub const NOCLOCK: Self = Self(0);
3139 #[doc = "LSE oscillator clock used as RTC clock"]
3140 pub const LSE: Self = Self(0x01);
3141 #[doc = "LSI oscillator clock used as RTC clock"]
3142 pub const LSI: Self = Self(0x02);
3143 #[doc = "HSE oscillator clock divided by a prescaler used as RTC clock"]
3144 pub const HSE: Self = Self(0x03);
3145 }
3146 #[repr(transparent)]
3147 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3148 pub struct Apb3enrLtdcen(pub u8);
3149 impl Apb3enrLtdcen {
3150 #[doc = "The selected clock is disabled"]
3151 pub const DISABLED: Self = Self(0);
3152 #[doc = "The selected clock is enabled"]
3153 pub const ENABLED: Self = Self(0x01);
3154 }
3155 #[repr(transparent)]
3156 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3157 pub struct Usart234578sel(pub u8);
3158 impl Usart234578sel {
3159 #[doc = "rcc_pclk1 selected as peripheral clock"]
3160 pub const RCC_PCLK1: Self = Self(0);
3161 #[doc = "pll2_q selected as peripheral clock"]
3162 pub const PLL2_Q: Self = Self(0x01);
3163 #[doc = "pll3_q selected as peripheral clock"]
3164 pub const PLL3_Q: Self = Self(0x02);
3165 #[doc = "hsi_ker selected as peripheral clock"]
3166 pub const HSI_KER: Self = Self(0x03);
3167 #[doc = "csi_ker selected as peripheral clock"]
3168 pub const CSI_KER: Self = Self(0x04);
3169 #[doc = "LSE selected as peripheral clock"]
3170 pub const LSE: Self = Self(0x05);
3171 }
3172 #[repr(transparent)]
3173 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3174 pub struct C1Apb2enrTim1en(pub u8);
3175 impl C1Apb2enrTim1en {
3176 #[doc = "The selected clock is disabled"]
3177 pub const DISABLED: Self = Self(0);
3178 #[doc = "The selected clock is enabled"]
3179 pub const ENABLED: Self = Self(0x01);
3180 }
3181 #[repr(transparent)]
3182 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3183 pub struct Ahb3lpenrMdmalpen(pub u8);
3184 impl Ahb3lpenrMdmalpen {
3185 #[doc = "The selected clock is disabled during csleep mode"]
3186 pub const DISABLED: Self = Self(0);
3187 #[doc = "The selected clock is enabled during csleep mode"]
3188 pub const ENABLED: Self = Self(0x01);
3189 }
3190 #[repr(transparent)]
3191 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3192 pub struct Hrtimsel(pub u8);
3193 impl Hrtimsel {
3194 #[doc = "The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck)"]
3195 pub const TIMY_KER: Self = Self(0);
3196 #[doc = "The HRTIM prescaler clock source is the CPU clock (c_ck)"]
3197 pub const C_CK: Self = Self(0x01);
3198 }
3199 #[repr(transparent)]
3200 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3201 pub struct Hsion(pub u8);
3202 impl Hsion {
3203 #[doc = "Clock Off"]
3204 pub const OFF: Self = Self(0);
3205 #[doc = "Clock On"]
3206 pub const ON: Self = Self(0x01);
3207 }
3208 #[repr(transparent)]
3209 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3210 pub struct Spi45sel(pub u8);
3211 impl Spi45sel {
3212 #[doc = "APB clock selected as peripheral clock"]
3213 pub const APB: Self = Self(0);
3214 #[doc = "pll2_q selected as peripheral clock"]
3215 pub const PLL2_Q: Self = Self(0x01);
3216 #[doc = "pll3_q selected as peripheral clock"]
3217 pub const PLL3_Q: Self = Self(0x02);
3218 #[doc = "hsi_ker selected as peripheral clock"]
3219 pub const HSI_KER: Self = Self(0x03);
3220 #[doc = "csi_ker selected as peripheral clock"]
3221 pub const CSI_KER: Self = Self(0x04);
3222 #[doc = "HSE selected as peripheral clock"]
3223 pub const HSE: Self = Self(0x05);
3224 }
3225 #[repr(transparent)]
3226 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3227 pub struct Adcsel(pub u8);
3228 impl Adcsel {
3229 #[doc = "pll2_p selected as peripheral clock"]
3230 pub const PLL2_P: Self = Self(0);
3231 #[doc = "pll3_r selected as peripheral clock"]
3232 pub const PLL3_R: Self = Self(0x01);
3233 #[doc = "PER selected as peripheral clock"]
3234 pub const PER: Self = Self(0x02);
3235 }
3236 #[repr(transparent)]
3237 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3238 pub struct D2ppre1(pub u8);
3239 impl D2ppre1 {
3240 #[doc = "rcc_hclk not divided"]
3241 pub const DIV1: Self = Self(0);
3242 #[doc = "rcc_hclk divided by 2"]
3243 pub const DIV2: Self = Self(0x04);
3244 #[doc = "rcc_hclk divided by 4"]
3245 pub const DIV4: Self = Self(0x05);
3246 #[doc = "rcc_hclk divided by 8"]
3247 pub const DIV8: Self = Self(0x06);
3248 #[doc = "rcc_hclk divided by 16"]
3249 pub const DIV16: Self = Self(0x07);
3250 }
3251 #[repr(transparent)]
3252 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3253 pub struct C1Apb2lpenrTim1lpen(pub u8);
3254 impl C1Apb2lpenrTim1lpen {
3255 #[doc = "The selected clock is disabled during csleep mode"]
3256 pub const DISABLED: Self = Self(0);
3257 #[doc = "The selected clock is enabled during csleep mode"]
3258 pub const ENABLED: Self = Self(0x01);
3259 }
3260 #[repr(transparent)]
3261 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3262 pub struct RsrRmvf(pub u8);
3263 impl RsrRmvf {
3264 #[doc = "Not clearing the the reset flags"]
3265 pub const NOTACTIVE: Self = Self(0);
3266 #[doc = "Clear the reset flags"]
3267 pub const CLEAR: Self = Self(0x01);
3268 }
3269 #[repr(transparent)]
3270 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3271 pub struct C1Ahb4lpenrGpioalpen(pub u8);
3272 impl C1Ahb4lpenrGpioalpen {
3273 #[doc = "The selected clock is disabled during csleep mode"]
3274 pub const DISABLED: Self = Self(0);
3275 #[doc = "The selected clock is enabled during csleep mode"]
3276 pub const ENABLED: Self = Self(0x01);
3277 }
3278 #[repr(transparent)]
3279 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
3280 pub struct Mdmarst(pub u8);
3281 impl Mdmarst {
3282 #[doc = "Reset the selected module"]
3283 pub const RESET: Self = Self(0x01);
3284 }
3285 }
3286 pub mod regs {
3287 use crate::generic::*;
3288 #[doc = "RCC AHB4 Sleep Clock Register"]
3289 #[repr(transparent)]
3290 #[derive(Copy, Clone, Eq, PartialEq)]
3291 pub struct Ahb4lpenr(pub u32);
3292 impl Ahb4lpenr {
3293 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3294 pub const fn gpioalpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
3295 let val = (self.0 >> 0usize) & 0x01;
3296 super::vals::Ahb4lpenrGpioalpen(val as u8)
3297 }
3298 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3299 pub fn set_gpioalpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
3300 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
3301 }
3302 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3303 pub const fn gpioblpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
3304 let val = (self.0 >> 1usize) & 0x01;
3305 super::vals::Ahb4lpenrGpioalpen(val as u8)
3306 }
3307 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3308 pub fn set_gpioblpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
3309 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
3310 }
3311 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3312 pub const fn gpioclpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
3313 let val = (self.0 >> 2usize) & 0x01;
3314 super::vals::Ahb4lpenrGpioalpen(val as u8)
3315 }
3316 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3317 pub fn set_gpioclpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
3318 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
3319 }
3320 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3321 pub const fn gpiodlpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
3322 let val = (self.0 >> 3usize) & 0x01;
3323 super::vals::Ahb4lpenrGpioalpen(val as u8)
3324 }
3325 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3326 pub fn set_gpiodlpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
3327 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
3328 }
3329 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3330 pub const fn gpioelpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
3331 let val = (self.0 >> 4usize) & 0x01;
3332 super::vals::Ahb4lpenrGpioalpen(val as u8)
3333 }
3334 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3335 pub fn set_gpioelpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
3336 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
3337 }
3338 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3339 pub const fn gpioflpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
3340 let val = (self.0 >> 5usize) & 0x01;
3341 super::vals::Ahb4lpenrGpioalpen(val as u8)
3342 }
3343 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3344 pub fn set_gpioflpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
3345 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
3346 }
3347 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3348 pub const fn gpioglpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
3349 let val = (self.0 >> 6usize) & 0x01;
3350 super::vals::Ahb4lpenrGpioalpen(val as u8)
3351 }
3352 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3353 pub fn set_gpioglpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
3354 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
3355 }
3356 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3357 pub const fn gpiohlpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
3358 let val = (self.0 >> 7usize) & 0x01;
3359 super::vals::Ahb4lpenrGpioalpen(val as u8)
3360 }
3361 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3362 pub fn set_gpiohlpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
3363 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
3364 }
3365 #[doc = "GPIO peripheral clock enable during CSleep mode"]
3366 pub const fn gpioilpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
3367>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
1737 let val = (self.0 >> 8usize) & 0x01; 3368 let val = (self.0 >> 8usize) & 0x01;
1738 val != 0 3369 super::vals::Ahb4lpenrGpioalpen(val as u8)
1739 } 3370 }
3371<<<<<<< HEAD
1740 #[doc = "Update DMA request enable"] 3372 #[doc = "Update DMA request enable"]
1741 pub fn set_ude(&mut self, val: bool) { 3373 pub fn set_ude(&mut self, val: bool) {
1742 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); 3374 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
@@ -9311,9 +10943,2339 @@ pub mod spi_v3 {
9311 impl Ier { 10943 impl Ier {
9312 #[doc = "RXP Interrupt Enable"] 10944 #[doc = "RXP Interrupt Enable"]
9313 pub const fn rxpie(&self) -> bool { 10945 pub const fn rxpie(&self) -> bool {
10946=======
10947 #[doc = "GPIO peripheral clock enable during CSleep mode"]
10948 pub fn set_gpioilpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
10949 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
10950 }
10951 #[doc = "GPIO peripheral clock enable during CSleep mode"]
10952 pub const fn gpiojlpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
10953 let val = (self.0 >> 9usize) & 0x01;
10954 super::vals::Ahb4lpenrGpioalpen(val as u8)
10955 }
10956 #[doc = "GPIO peripheral clock enable during CSleep mode"]
10957 pub fn set_gpiojlpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
10958 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
10959 }
10960 #[doc = "GPIO peripheral clock enable during CSleep mode"]
10961 pub const fn gpioklpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
10962 let val = (self.0 >> 10usize) & 0x01;
10963 super::vals::Ahb4lpenrGpioalpen(val as u8)
10964 }
10965 #[doc = "GPIO peripheral clock enable during CSleep mode"]
10966 pub fn set_gpioklpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
10967 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
10968 }
10969 #[doc = "CRC peripheral clock enable during CSleep mode"]
10970 pub const fn crclpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
10971 let val = (self.0 >> 19usize) & 0x01;
10972 super::vals::Ahb4lpenrGpioalpen(val as u8)
10973 }
10974 #[doc = "CRC peripheral clock enable during CSleep mode"]
10975 pub fn set_crclpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
10976 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
10977 }
10978 #[doc = "BDMA Clock Enable During CSleep Mode"]
10979 pub const fn bdmalpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
10980 let val = (self.0 >> 21usize) & 0x01;
10981 super::vals::Ahb4lpenrGpioalpen(val as u8)
10982 }
10983 #[doc = "BDMA Clock Enable During CSleep Mode"]
10984 pub fn set_bdmalpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
10985 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
10986 }
10987 #[doc = "ADC3 Peripheral Clocks Enable During CSleep Mode"]
10988 pub const fn adc3lpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
10989 let val = (self.0 >> 24usize) & 0x01;
10990 super::vals::Ahb4lpenrGpioalpen(val as u8)
10991 }
10992 #[doc = "ADC3 Peripheral Clocks Enable During CSleep Mode"]
10993 pub fn set_adc3lpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
10994 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
10995 }
10996 #[doc = "Backup RAM Clock Enable During CSleep Mode"]
10997 pub const fn bkpramlpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
10998 let val = (self.0 >> 28usize) & 0x01;
10999 super::vals::Ahb4lpenrGpioalpen(val as u8)
11000 }
11001 #[doc = "Backup RAM Clock Enable During CSleep Mode"]
11002 pub fn set_bkpramlpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
11003 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
11004 }
11005 #[doc = "SRAM4 Clock Enable During CSleep Mode"]
11006 pub const fn sram4lpen(&self) -> super::vals::Ahb4lpenrGpioalpen {
11007 let val = (self.0 >> 29usize) & 0x01;
11008 super::vals::Ahb4lpenrGpioalpen(val as u8)
11009 }
11010 #[doc = "SRAM4 Clock Enable During CSleep Mode"]
11011 pub fn set_sram4lpen(&mut self, val: super::vals::Ahb4lpenrGpioalpen) {
11012 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
11013 }
11014 }
11015 impl Default for Ahb4lpenr {
11016 fn default() -> Ahb4lpenr {
11017 Ahb4lpenr(0)
11018 }
11019 }
11020 #[doc = "RCC AHB3 Clock Register"]
11021 #[repr(transparent)]
11022 #[derive(Copy, Clone, Eq, PartialEq)]
11023 pub struct Ahb3enr(pub u32);
11024 impl Ahb3enr {
11025 #[doc = "MDMA Peripheral Clock Enable"]
11026 pub const fn mdmaen(&self) -> super::vals::Ahb3enrMdmaen {
11027 let val = (self.0 >> 0usize) & 0x01;
11028 super::vals::Ahb3enrMdmaen(val as u8)
11029 }
11030 #[doc = "MDMA Peripheral Clock Enable"]
11031 pub fn set_mdmaen(&mut self, val: super::vals::Ahb3enrMdmaen) {
11032 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
11033 }
11034 #[doc = "DMA2D Peripheral Clock Enable"]
11035 pub const fn dma2den(&self) -> super::vals::Ahb3enrMdmaen {
11036 let val = (self.0 >> 4usize) & 0x01;
11037 super::vals::Ahb3enrMdmaen(val as u8)
11038 }
11039 #[doc = "DMA2D Peripheral Clock Enable"]
11040 pub fn set_dma2den(&mut self, val: super::vals::Ahb3enrMdmaen) {
11041 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
11042 }
11043 #[doc = "JPGDEC Peripheral Clock Enable"]
11044 pub const fn jpgdecen(&self) -> super::vals::Ahb3enrMdmaen {
11045 let val = (self.0 >> 5usize) & 0x01;
11046 super::vals::Ahb3enrMdmaen(val as u8)
11047 }
11048 #[doc = "JPGDEC Peripheral Clock Enable"]
11049 pub fn set_jpgdecen(&mut self, val: super::vals::Ahb3enrMdmaen) {
11050 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
11051 }
11052 #[doc = "FMC Peripheral Clocks Enable"]
11053 pub const fn fmcen(&self) -> super::vals::Ahb3enrMdmaen {
11054 let val = (self.0 >> 12usize) & 0x01;
11055 super::vals::Ahb3enrMdmaen(val as u8)
11056 }
11057 #[doc = "FMC Peripheral Clocks Enable"]
11058 pub fn set_fmcen(&mut self, val: super::vals::Ahb3enrMdmaen) {
11059 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
11060 }
11061 #[doc = "QUADSPI and QUADSPI Delay Clock Enable"]
11062 pub const fn qspien(&self) -> super::vals::Ahb3enrMdmaen {
11063 let val = (self.0 >> 14usize) & 0x01;
11064 super::vals::Ahb3enrMdmaen(val as u8)
11065 }
11066 #[doc = "QUADSPI and QUADSPI Delay Clock Enable"]
11067 pub fn set_qspien(&mut self, val: super::vals::Ahb3enrMdmaen) {
11068 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
11069 }
11070 #[doc = "SDMMC1 and SDMMC1 Delay Clock Enable"]
11071 pub const fn sdmmc1en(&self) -> super::vals::Ahb3enrMdmaen {
11072 let val = (self.0 >> 16usize) & 0x01;
11073 super::vals::Ahb3enrMdmaen(val as u8)
11074 }
11075 #[doc = "SDMMC1 and SDMMC1 Delay Clock Enable"]
11076 pub fn set_sdmmc1en(&mut self, val: super::vals::Ahb3enrMdmaen) {
11077 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
11078 }
11079 }
11080 impl Default for Ahb3enr {
11081 fn default() -> Ahb3enr {
11082 Ahb3enr(0)
11083 }
11084 }
11085 #[doc = "RCC CSI configuration register"]
11086 #[repr(transparent)]
11087 #[derive(Copy, Clone, Eq, PartialEq)]
11088 pub struct Csicfgr(pub u32);
11089 impl Csicfgr {
11090 #[doc = "CSI clock calibration"]
11091 pub const fn csical(&self) -> u16 {
11092 let val = (self.0 >> 0usize) & 0x01ff;
11093 val as u16
11094 }
11095 #[doc = "CSI clock calibration"]
11096 pub fn set_csical(&mut self, val: u16) {
11097 self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
11098 }
11099 #[doc = "CSI clock trimming"]
11100 pub const fn csitrim(&self) -> u8 {
11101 let val = (self.0 >> 24usize) & 0x3f;
11102 val as u8
11103 }
11104 #[doc = "CSI clock trimming"]
11105 pub fn set_csitrim(&mut self, val: u8) {
11106 self.0 = (self.0 & !(0x3f << 24usize)) | (((val as u32) & 0x3f) << 24usize);
11107 }
11108 }
11109 impl Default for Csicfgr {
11110 fn default() -> Csicfgr {
11111 Csicfgr(0)
11112 }
11113 }
11114 #[doc = "RCC AHB2 Sleep Clock Register"]
11115 #[repr(transparent)]
11116 #[derive(Copy, Clone, Eq, PartialEq)]
11117 pub struct C1Ahb2lpenr(pub u32);
11118 impl C1Ahb2lpenr {
11119 #[doc = "DCMI peripheral clock enable during csleep mode"]
11120 pub const fn dcmilpen(&self) -> super::vals::C1Ahb2lpenrDcmilpen {
11121 let val = (self.0 >> 0usize) & 0x01;
11122 super::vals::C1Ahb2lpenrDcmilpen(val as u8)
11123 }
11124 #[doc = "DCMI peripheral clock enable during csleep mode"]
11125 pub fn set_dcmilpen(&mut self, val: super::vals::C1Ahb2lpenrDcmilpen) {
11126 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
11127 }
11128 #[doc = "CRYPT peripheral clock enable during CSleep mode"]
11129 pub const fn cryptlpen(&self) -> super::vals::C1Ahb2lpenrDcmilpen {
11130 let val = (self.0 >> 4usize) & 0x01;
11131 super::vals::C1Ahb2lpenrDcmilpen(val as u8)
11132 }
11133 #[doc = "CRYPT peripheral clock enable during CSleep mode"]
11134 pub fn set_cryptlpen(&mut self, val: super::vals::C1Ahb2lpenrDcmilpen) {
11135 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
11136 }
11137 #[doc = "HASH peripheral clock enable during CSleep mode"]
11138 pub const fn hashlpen(&self) -> super::vals::C1Ahb2lpenrDcmilpen {
11139 let val = (self.0 >> 5usize) & 0x01;
11140 super::vals::C1Ahb2lpenrDcmilpen(val as u8)
11141 }
11142 #[doc = "HASH peripheral clock enable during CSleep mode"]
11143 pub fn set_hashlpen(&mut self, val: super::vals::C1Ahb2lpenrDcmilpen) {
11144 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
11145 }
11146 #[doc = "RNG peripheral clock enable during CSleep mode"]
11147 pub const fn rnglpen(&self) -> super::vals::C1Ahb2lpenrDcmilpen {
11148 let val = (self.0 >> 6usize) & 0x01;
11149 super::vals::C1Ahb2lpenrDcmilpen(val as u8)
11150 }
11151 #[doc = "RNG peripheral clock enable during CSleep mode"]
11152 pub fn set_rnglpen(&mut self, val: super::vals::C1Ahb2lpenrDcmilpen) {
11153 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
11154 }
11155 #[doc = "SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode"]
11156 pub const fn sdmmc2lpen(&self) -> super::vals::C1Ahb2lpenrDcmilpen {
11157 let val = (self.0 >> 9usize) & 0x01;
11158 super::vals::C1Ahb2lpenrDcmilpen(val as u8)
11159 }
11160 #[doc = "SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode"]
11161 pub fn set_sdmmc2lpen(&mut self, val: super::vals::C1Ahb2lpenrDcmilpen) {
11162 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
11163 }
11164 #[doc = "SRAM1 Clock Enable During CSleep Mode"]
11165 pub const fn sram1lpen(&self) -> super::vals::C1Ahb2lpenrDcmilpen {
11166 let val = (self.0 >> 29usize) & 0x01;
11167 super::vals::C1Ahb2lpenrDcmilpen(val as u8)
11168 }
11169 #[doc = "SRAM1 Clock Enable During CSleep Mode"]
11170 pub fn set_sram1lpen(&mut self, val: super::vals::C1Ahb2lpenrDcmilpen) {
11171 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
11172 }
11173 #[doc = "SRAM2 Clock Enable During CSleep Mode"]
11174 pub const fn sram2lpen(&self) -> super::vals::C1Ahb2lpenrDcmilpen {
11175 let val = (self.0 >> 30usize) & 0x01;
11176 super::vals::C1Ahb2lpenrDcmilpen(val as u8)
11177 }
11178 #[doc = "SRAM2 Clock Enable During CSleep Mode"]
11179 pub fn set_sram2lpen(&mut self, val: super::vals::C1Ahb2lpenrDcmilpen) {
11180 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
11181 }
11182 #[doc = "SRAM3 Clock Enable During CSleep Mode"]
11183 pub const fn sram3lpen(&self) -> super::vals::C1Ahb2lpenrDcmilpen {
11184 let val = (self.0 >> 31usize) & 0x01;
11185 super::vals::C1Ahb2lpenrDcmilpen(val as u8)
11186 }
11187 #[doc = "SRAM3 Clock Enable During CSleep Mode"]
11188 pub fn set_sram3lpen(&mut self, val: super::vals::C1Ahb2lpenrDcmilpen) {
11189 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
11190 }
11191 }
11192 impl Default for C1Ahb2lpenr {
11193 fn default() -> C1Ahb2lpenr {
11194 C1Ahb2lpenr(0)
11195 }
11196 }
11197 #[doc = "RCC APB2 Peripheral Reset Register"]
11198 #[repr(transparent)]
11199 #[derive(Copy, Clone, Eq, PartialEq)]
11200 pub struct Apb2rstr(pub u32);
11201 impl Apb2rstr {
11202 #[doc = "TIM1 block reset"]
11203 pub const fn tim1rst(&self) -> super::vals::Tim1rst {
9314 let val = (self.0 >> 0usize) & 0x01; 11204 let val = (self.0 >> 0usize) & 0x01;
11205 super::vals::Tim1rst(val as u8)
11206 }
11207 #[doc = "TIM1 block reset"]
11208 pub fn set_tim1rst(&mut self, val: super::vals::Tim1rst) {
11209 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
11210 }
11211 #[doc = "TIM8 block reset"]
11212 pub const fn tim8rst(&self) -> super::vals::Tim1rst {
11213 let val = (self.0 >> 1usize) & 0x01;
11214 super::vals::Tim1rst(val as u8)
11215 }
11216 #[doc = "TIM8 block reset"]
11217 pub fn set_tim8rst(&mut self, val: super::vals::Tim1rst) {
11218 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
11219 }
11220 #[doc = "USART1 block reset"]
11221 pub const fn usart1rst(&self) -> super::vals::Tim1rst {
11222 let val = (self.0 >> 4usize) & 0x01;
11223 super::vals::Tim1rst(val as u8)
11224 }
11225 #[doc = "USART1 block reset"]
11226 pub fn set_usart1rst(&mut self, val: super::vals::Tim1rst) {
11227 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
11228 }
11229 #[doc = "USART6 block reset"]
11230 pub const fn usart6rst(&self) -> super::vals::Tim1rst {
11231 let val = (self.0 >> 5usize) & 0x01;
11232 super::vals::Tim1rst(val as u8)
11233 }
11234 #[doc = "USART6 block reset"]
11235 pub fn set_usart6rst(&mut self, val: super::vals::Tim1rst) {
11236 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
11237 }
11238 #[doc = "SPI1 block reset"]
11239 pub const fn spi1rst(&self) -> super::vals::Tim1rst {
11240 let val = (self.0 >> 12usize) & 0x01;
11241 super::vals::Tim1rst(val as u8)
11242 }
11243 #[doc = "SPI1 block reset"]
11244 pub fn set_spi1rst(&mut self, val: super::vals::Tim1rst) {
11245 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
11246 }
11247 #[doc = "SPI4 block reset"]
11248 pub const fn spi4rst(&self) -> super::vals::Tim1rst {
11249 let val = (self.0 >> 13usize) & 0x01;
11250 super::vals::Tim1rst(val as u8)
11251 }
11252 #[doc = "SPI4 block reset"]
11253 pub fn set_spi4rst(&mut self, val: super::vals::Tim1rst) {
11254 self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize);
11255 }
11256 #[doc = "TIM15 block reset"]
11257 pub const fn tim15rst(&self) -> super::vals::Tim1rst {
11258 let val = (self.0 >> 16usize) & 0x01;
11259 super::vals::Tim1rst(val as u8)
11260 }
11261 #[doc = "TIM15 block reset"]
11262 pub fn set_tim15rst(&mut self, val: super::vals::Tim1rst) {
11263 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
11264 }
11265 #[doc = "TIM16 block reset"]
11266 pub const fn tim16rst(&self) -> super::vals::Tim1rst {
11267 let val = (self.0 >> 17usize) & 0x01;
11268 super::vals::Tim1rst(val as u8)
11269 }
11270 #[doc = "TIM16 block reset"]
11271 pub fn set_tim16rst(&mut self, val: super::vals::Tim1rst) {
11272 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
11273 }
11274 #[doc = "TIM17 block reset"]
11275 pub const fn tim17rst(&self) -> super::vals::Tim1rst {
11276 let val = (self.0 >> 18usize) & 0x01;
11277 super::vals::Tim1rst(val as u8)
11278 }
11279 #[doc = "TIM17 block reset"]
11280 pub fn set_tim17rst(&mut self, val: super::vals::Tim1rst) {
11281 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
11282 }
11283 #[doc = "SPI5 block reset"]
11284 pub const fn spi5rst(&self) -> super::vals::Tim1rst {
11285 let val = (self.0 >> 20usize) & 0x01;
11286 super::vals::Tim1rst(val as u8)
11287 }
11288 #[doc = "SPI5 block reset"]
11289 pub fn set_spi5rst(&mut self, val: super::vals::Tim1rst) {
11290 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.0 as u32) & 0x01) << 20usize);
11291 }
11292 #[doc = "SAI1 block reset"]
11293 pub const fn sai1rst(&self) -> super::vals::Tim1rst {
11294 let val = (self.0 >> 22usize) & 0x01;
11295 super::vals::Tim1rst(val as u8)
11296 }
11297 #[doc = "SAI1 block reset"]
11298 pub fn set_sai1rst(&mut self, val: super::vals::Tim1rst) {
11299 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
11300 }
11301 #[doc = "SAI2 block reset"]
11302 pub const fn sai2rst(&self) -> super::vals::Tim1rst {
11303 let val = (self.0 >> 23usize) & 0x01;
11304 super::vals::Tim1rst(val as u8)
11305 }
11306 #[doc = "SAI2 block reset"]
11307 pub fn set_sai2rst(&mut self, val: super::vals::Tim1rst) {
11308 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
11309 }
11310 #[doc = "SAI3 block reset"]
11311 pub const fn sai3rst(&self) -> super::vals::Tim1rst {
11312 let val = (self.0 >> 24usize) & 0x01;
11313 super::vals::Tim1rst(val as u8)
11314 }
11315 #[doc = "SAI3 block reset"]
11316 pub fn set_sai3rst(&mut self, val: super::vals::Tim1rst) {
11317 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
11318 }
11319 #[doc = "DFSDM1 block reset"]
11320 pub const fn dfsdm1rst(&self) -> super::vals::Tim1rst {
11321 let val = (self.0 >> 28usize) & 0x01;
11322 super::vals::Tim1rst(val as u8)
11323 }
11324 #[doc = "DFSDM1 block reset"]
11325 pub fn set_dfsdm1rst(&mut self, val: super::vals::Tim1rst) {
11326 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
11327 }
11328 #[doc = "HRTIM block reset"]
11329 pub const fn hrtimrst(&self) -> super::vals::Tim1rst {
11330 let val = (self.0 >> 29usize) & 0x01;
11331 super::vals::Tim1rst(val as u8)
11332 }
11333 #[doc = "HRTIM block reset"]
11334 pub fn set_hrtimrst(&mut self, val: super::vals::Tim1rst) {
11335 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
11336 }
11337 }
11338 impl Default for Apb2rstr {
11339 fn default() -> Apb2rstr {
11340 Apb2rstr(0)
11341 }
11342 }
11343 #[doc = "RCC Reset Status Register"]
11344 #[repr(transparent)]
11345 #[derive(Copy, Clone, Eq, PartialEq)]
11346 pub struct Rsr(pub u32);
11347 impl Rsr {
11348 #[doc = "Remove reset flag"]
11349 pub const fn rmvf(&self) -> super::vals::RsrRmvf {
11350 let val = (self.0 >> 16usize) & 0x01;
11351 super::vals::RsrRmvf(val as u8)
11352 }
11353 #[doc = "Remove reset flag"]
11354 pub fn set_rmvf(&mut self, val: super::vals::RsrRmvf) {
11355 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
11356 }
11357 #[doc = "CPU reset flag"]
11358 pub const fn cpurstf(&self) -> bool {
11359 let val = (self.0 >> 17usize) & 0x01;
11360 val != 0
11361 }
11362 #[doc = "CPU reset flag"]
11363 pub fn set_cpurstf(&mut self, val: bool) {
11364 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
11365 }
11366 #[doc = "D1 domain power switch reset flag"]
11367 pub const fn d1rstf(&self) -> bool {
11368 let val = (self.0 >> 19usize) & 0x01;
11369 val != 0
11370 }
11371 #[doc = "D1 domain power switch reset flag"]
11372 pub fn set_d1rstf(&mut self, val: bool) {
11373 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
11374 }
11375 #[doc = "D2 domain power switch reset flag"]
11376 pub const fn d2rstf(&self) -> bool {
11377 let val = (self.0 >> 20usize) & 0x01;
11378 val != 0
11379 }
11380 #[doc = "D2 domain power switch reset flag"]
11381 pub fn set_d2rstf(&mut self, val: bool) {
11382 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
11383 }
11384 #[doc = "BOR reset flag"]
11385 pub const fn borrstf(&self) -> bool {
11386 let val = (self.0 >> 21usize) & 0x01;
11387 val != 0
11388 }
11389 #[doc = "BOR reset flag"]
11390 pub fn set_borrstf(&mut self, val: bool) {
11391 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
11392 }
11393 #[doc = "Pin reset flag (NRST)"]
11394 pub const fn pinrstf(&self) -> bool {
11395 let val = (self.0 >> 22usize) & 0x01;
11396 val != 0
11397 }
11398 #[doc = "Pin reset flag (NRST)"]
11399 pub fn set_pinrstf(&mut self, val: bool) {
11400 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
11401 }
11402 #[doc = "POR/PDR reset flag"]
11403 pub const fn porrstf(&self) -> bool {
11404 let val = (self.0 >> 23usize) & 0x01;
11405 val != 0
11406 }
11407 #[doc = "POR/PDR reset flag"]
11408 pub fn set_porrstf(&mut self, val: bool) {
11409 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
11410 }
11411 #[doc = "System reset from CPU reset flag"]
11412 pub const fn sftrstf(&self) -> bool {
11413 let val = (self.0 >> 24usize) & 0x01;
11414 val != 0
11415 }
11416 #[doc = "System reset from CPU reset flag"]
11417 pub fn set_sftrstf(&mut self, val: bool) {
11418 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
11419 }
11420 #[doc = "Independent Watchdog reset flag"]
11421 pub const fn iwdg1rstf(&self) -> bool {
11422 let val = (self.0 >> 26usize) & 0x01;
11423 val != 0
11424 }
11425 #[doc = "Independent Watchdog reset flag"]
11426 pub fn set_iwdg1rstf(&mut self, val: bool) {
11427 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
11428 }
11429 #[doc = "Window Watchdog reset flag"]
11430 pub const fn wwdg1rstf(&self) -> bool {
11431 let val = (self.0 >> 28usize) & 0x01;
11432 val != 0
11433 }
11434 #[doc = "Window Watchdog reset flag"]
11435 pub fn set_wwdg1rstf(&mut self, val: bool) {
11436 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
11437 }
11438 #[doc = "Reset due to illegal D1 DStandby or CPU CStop flag"]
11439 pub const fn lpwrrstf(&self) -> bool {
11440 let val = (self.0 >> 30usize) & 0x01;
11441 val != 0
11442 }
11443 #[doc = "Reset due to illegal D1 DStandby or CPU CStop flag"]
11444 pub fn set_lpwrrstf(&mut self, val: bool) {
11445 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
11446 }
11447 }
11448 impl Default for Rsr {
11449 fn default() -> Rsr {
11450 Rsr(0)
11451 }
11452 }
11453 #[doc = "RCC APB4 Sleep Clock Register"]
11454 #[repr(transparent)]
11455 #[derive(Copy, Clone, Eq, PartialEq)]
11456 pub struct Apb4lpenr(pub u32);
11457 impl Apb4lpenr {
11458 #[doc = "SYSCFG peripheral clock enable during CSleep mode"]
11459 pub const fn syscfglpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11460 let val = (self.0 >> 1usize) & 0x01;
11461 super::vals::Apb4lpenrSyscfglpen(val as u8)
11462 }
11463 #[doc = "SYSCFG peripheral clock enable during CSleep mode"]
11464 pub fn set_syscfglpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11465 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
11466 }
11467 #[doc = "LPUART1 Peripheral Clocks Enable During CSleep Mode"]
11468 pub const fn lpuart1lpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11469 let val = (self.0 >> 3usize) & 0x01;
11470 super::vals::Apb4lpenrSyscfglpen(val as u8)
11471 }
11472 #[doc = "LPUART1 Peripheral Clocks Enable During CSleep Mode"]
11473 pub fn set_lpuart1lpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11474 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
11475 }
11476 #[doc = "SPI6 Peripheral Clocks Enable During CSleep Mode"]
11477 pub const fn spi6lpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11478 let val = (self.0 >> 5usize) & 0x01;
11479 super::vals::Apb4lpenrSyscfglpen(val as u8)
11480 }
11481 #[doc = "SPI6 Peripheral Clocks Enable During CSleep Mode"]
11482 pub fn set_spi6lpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11483 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
11484 }
11485 #[doc = "I2C4 Peripheral Clocks Enable During CSleep Mode"]
11486 pub const fn i2c4lpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11487 let val = (self.0 >> 7usize) & 0x01;
11488 super::vals::Apb4lpenrSyscfglpen(val as u8)
11489 }
11490 #[doc = "I2C4 Peripheral Clocks Enable During CSleep Mode"]
11491 pub fn set_i2c4lpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11492 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
11493 }
11494 #[doc = "LPTIM2 Peripheral Clocks Enable During CSleep Mode"]
11495 pub const fn lptim2lpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11496 let val = (self.0 >> 9usize) & 0x01;
11497 super::vals::Apb4lpenrSyscfglpen(val as u8)
11498 }
11499 #[doc = "LPTIM2 Peripheral Clocks Enable During CSleep Mode"]
11500 pub fn set_lptim2lpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11501 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
11502 }
11503 #[doc = "LPTIM3 Peripheral Clocks Enable During CSleep Mode"]
11504 pub const fn lptim3lpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11505 let val = (self.0 >> 10usize) & 0x01;
11506 super::vals::Apb4lpenrSyscfglpen(val as u8)
11507 }
11508 #[doc = "LPTIM3 Peripheral Clocks Enable During CSleep Mode"]
11509 pub fn set_lptim3lpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11510 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
11511 }
11512 #[doc = "LPTIM4 Peripheral Clocks Enable During CSleep Mode"]
11513 pub const fn lptim4lpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11514 let val = (self.0 >> 11usize) & 0x01;
11515 super::vals::Apb4lpenrSyscfglpen(val as u8)
11516 }
11517 #[doc = "LPTIM4 Peripheral Clocks Enable During CSleep Mode"]
11518 pub fn set_lptim4lpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11519 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
11520 }
11521 #[doc = "LPTIM5 Peripheral Clocks Enable During CSleep Mode"]
11522 pub const fn lptim5lpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11523 let val = (self.0 >> 12usize) & 0x01;
11524 super::vals::Apb4lpenrSyscfglpen(val as u8)
11525 }
11526 #[doc = "LPTIM5 Peripheral Clocks Enable During CSleep Mode"]
11527 pub fn set_lptim5lpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11528 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
11529 }
11530 #[doc = "COMP1/2 peripheral clock enable during CSleep mode"]
11531 pub const fn comp12lpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11532 let val = (self.0 >> 14usize) & 0x01;
11533 super::vals::Apb4lpenrSyscfglpen(val as u8)
11534 }
11535 #[doc = "COMP1/2 peripheral clock enable during CSleep mode"]
11536 pub fn set_comp12lpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11537 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
11538 }
11539 #[doc = "VREF peripheral clock enable during CSleep mode"]
11540 pub const fn vreflpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11541 let val = (self.0 >> 15usize) & 0x01;
11542 super::vals::Apb4lpenrSyscfglpen(val as u8)
11543 }
11544 #[doc = "VREF peripheral clock enable during CSleep mode"]
11545 pub fn set_vreflpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11546 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
11547 }
11548 #[doc = "RTC APB Clock Enable During CSleep Mode"]
11549 pub const fn rtcapblpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11550 let val = (self.0 >> 16usize) & 0x01;
11551 super::vals::Apb4lpenrSyscfglpen(val as u8)
11552 }
11553 #[doc = "RTC APB Clock Enable During CSleep Mode"]
11554 pub fn set_rtcapblpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11555 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
11556 }
11557 #[doc = "SAI4 Peripheral Clocks Enable During CSleep Mode"]
11558 pub const fn sai4lpen(&self) -> super::vals::Apb4lpenrSyscfglpen {
11559 let val = (self.0 >> 21usize) & 0x01;
11560 super::vals::Apb4lpenrSyscfglpen(val as u8)
11561 }
11562 #[doc = "SAI4 Peripheral Clocks Enable During CSleep Mode"]
11563 pub fn set_sai4lpen(&mut self, val: super::vals::Apb4lpenrSyscfglpen) {
11564 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
11565 }
11566 }
11567 impl Default for Apb4lpenr {
11568 fn default() -> Apb4lpenr {
11569 Apb4lpenr(0)
11570 }
11571 }
11572 #[doc = "RCC AHB3 Reset Register"]
11573 #[repr(transparent)]
11574 #[derive(Copy, Clone, Eq, PartialEq)]
11575 pub struct Ahb3rstr(pub u32);
11576 impl Ahb3rstr {
11577 #[doc = "MDMA block reset"]
11578 pub const fn mdmarst(&self) -> super::vals::Mdmarst {
11579 let val = (self.0 >> 0usize) & 0x01;
11580 super::vals::Mdmarst(val as u8)
11581 }
11582 #[doc = "MDMA block reset"]
11583 pub fn set_mdmarst(&mut self, val: super::vals::Mdmarst) {
11584 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
11585 }
11586 #[doc = "DMA2D block reset"]
11587 pub const fn dma2drst(&self) -> super::vals::Mdmarst {
11588 let val = (self.0 >> 4usize) & 0x01;
11589 super::vals::Mdmarst(val as u8)
11590 }
11591 #[doc = "DMA2D block reset"]
11592 pub fn set_dma2drst(&mut self, val: super::vals::Mdmarst) {
11593 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
11594 }
11595 #[doc = "JPGDEC block reset"]
11596 pub const fn jpgdecrst(&self) -> super::vals::Mdmarst {
11597 let val = (self.0 >> 5usize) & 0x01;
11598 super::vals::Mdmarst(val as u8)
11599 }
11600 #[doc = "JPGDEC block reset"]
11601 pub fn set_jpgdecrst(&mut self, val: super::vals::Mdmarst) {
11602 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
11603 }
11604 #[doc = "FMC block reset"]
11605 pub const fn fmcrst(&self) -> super::vals::Mdmarst {
11606 let val = (self.0 >> 12usize) & 0x01;
11607 super::vals::Mdmarst(val as u8)
11608 }
11609 #[doc = "FMC block reset"]
11610 pub fn set_fmcrst(&mut self, val: super::vals::Mdmarst) {
11611 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
11612 }
11613 #[doc = "QUADSPI and QUADSPI delay block reset"]
11614 pub const fn qspirst(&self) -> super::vals::Mdmarst {
11615 let val = (self.0 >> 14usize) & 0x01;
11616 super::vals::Mdmarst(val as u8)
11617 }
11618 #[doc = "QUADSPI and QUADSPI delay block reset"]
11619 pub fn set_qspirst(&mut self, val: super::vals::Mdmarst) {
11620 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
11621 }
11622 #[doc = "SDMMC1 and SDMMC1 delay block reset"]
11623 pub const fn sdmmc1rst(&self) -> super::vals::Mdmarst {
11624 let val = (self.0 >> 16usize) & 0x01;
11625 super::vals::Mdmarst(val as u8)
11626 }
11627 #[doc = "SDMMC1 and SDMMC1 delay block reset"]
11628 pub fn set_sdmmc1rst(&mut self, val: super::vals::Mdmarst) {
11629 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
11630 }
11631 #[doc = "CPU reset"]
11632 pub const fn cpurst(&self) -> super::vals::Mdmarst {
11633 let val = (self.0 >> 31usize) & 0x01;
11634 super::vals::Mdmarst(val as u8)
11635 }
11636 #[doc = "CPU reset"]
11637 pub fn set_cpurst(&mut self, val: super::vals::Mdmarst) {
11638 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
11639 }
11640 }
11641 impl Default for Ahb3rstr {
11642 fn default() -> Ahb3rstr {
11643 Ahb3rstr(0)
11644 }
11645 }
11646 #[doc = "RCC APB2 Clock Register"]
11647 #[repr(transparent)]
11648 #[derive(Copy, Clone, Eq, PartialEq)]
11649 pub struct Apb2enr(pub u32);
11650 impl Apb2enr {
11651 #[doc = "TIM1 peripheral clock enable"]
11652 pub const fn tim1en(&self) -> super::vals::Apb2enrTim1en {
11653 let val = (self.0 >> 0usize) & 0x01;
11654 super::vals::Apb2enrTim1en(val as u8)
11655 }
11656 #[doc = "TIM1 peripheral clock enable"]
11657 pub fn set_tim1en(&mut self, val: super::vals::Apb2enrTim1en) {
11658 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
11659 }
11660 #[doc = "TIM8 peripheral clock enable"]
11661 pub const fn tim8en(&self) -> super::vals::Apb2enrTim1en {
11662 let val = (self.0 >> 1usize) & 0x01;
11663 super::vals::Apb2enrTim1en(val as u8)
11664 }
11665 #[doc = "TIM8 peripheral clock enable"]
11666 pub fn set_tim8en(&mut self, val: super::vals::Apb2enrTim1en) {
11667 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
11668 }
11669 #[doc = "USART1 Peripheral Clocks Enable"]
11670 pub const fn usart1en(&self) -> super::vals::Apb2enrTim1en {
11671 let val = (self.0 >> 4usize) & 0x01;
11672 super::vals::Apb2enrTim1en(val as u8)
11673 }
11674 #[doc = "USART1 Peripheral Clocks Enable"]
11675 pub fn set_usart1en(&mut self, val: super::vals::Apb2enrTim1en) {
11676 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
11677 }
11678 #[doc = "USART6 Peripheral Clocks Enable"]
11679 pub const fn usart6en(&self) -> super::vals::Apb2enrTim1en {
11680 let val = (self.0 >> 5usize) & 0x01;
11681 super::vals::Apb2enrTim1en(val as u8)
11682 }
11683 #[doc = "USART6 Peripheral Clocks Enable"]
11684 pub fn set_usart6en(&mut self, val: super::vals::Apb2enrTim1en) {
11685 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
11686 }
11687 #[doc = "SPI1 Peripheral Clocks Enable"]
11688 pub const fn spi1en(&self) -> super::vals::Apb2enrTim1en {
11689 let val = (self.0 >> 12usize) & 0x01;
11690 super::vals::Apb2enrTim1en(val as u8)
11691 }
11692 #[doc = "SPI1 Peripheral Clocks Enable"]
11693 pub fn set_spi1en(&mut self, val: super::vals::Apb2enrTim1en) {
11694 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
11695 }
11696 #[doc = "SPI4 Peripheral Clocks Enable"]
11697 pub const fn spi4en(&self) -> super::vals::Apb2enrTim1en {
11698 let val = (self.0 >> 13usize) & 0x01;
11699 super::vals::Apb2enrTim1en(val as u8)
11700 }
11701 #[doc = "SPI4 Peripheral Clocks Enable"]
11702 pub fn set_spi4en(&mut self, val: super::vals::Apb2enrTim1en) {
11703 self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize);
11704 }
11705 #[doc = "TIM15 peripheral clock enable"]
11706 pub const fn tim15en(&self) -> super::vals::Apb2enrTim1en {
11707 let val = (self.0 >> 16usize) & 0x01;
11708 super::vals::Apb2enrTim1en(val as u8)
11709 }
11710 #[doc = "TIM15 peripheral clock enable"]
11711 pub fn set_tim15en(&mut self, val: super::vals::Apb2enrTim1en) {
11712 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
11713 }
11714 #[doc = "TIM16 peripheral clock enable"]
11715 pub const fn tim16en(&self) -> super::vals::Apb2enrTim1en {
11716 let val = (self.0 >> 17usize) & 0x01;
11717 super::vals::Apb2enrTim1en(val as u8)
11718 }
11719 #[doc = "TIM16 peripheral clock enable"]
11720 pub fn set_tim16en(&mut self, val: super::vals::Apb2enrTim1en) {
11721 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
11722 }
11723 #[doc = "TIM17 peripheral clock enable"]
11724 pub const fn tim17en(&self) -> super::vals::Apb2enrTim1en {
11725 let val = (self.0 >> 18usize) & 0x01;
11726 super::vals::Apb2enrTim1en(val as u8)
11727 }
11728 #[doc = "TIM17 peripheral clock enable"]
11729 pub fn set_tim17en(&mut self, val: super::vals::Apb2enrTim1en) {
11730 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
11731 }
11732 #[doc = "SPI5 Peripheral Clocks Enable"]
11733 pub const fn spi5en(&self) -> super::vals::Apb2enrTim1en {
11734 let val = (self.0 >> 20usize) & 0x01;
11735 super::vals::Apb2enrTim1en(val as u8)
11736 }
11737 #[doc = "SPI5 Peripheral Clocks Enable"]
11738 pub fn set_spi5en(&mut self, val: super::vals::Apb2enrTim1en) {
11739 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.0 as u32) & 0x01) << 20usize);
11740 }
11741 #[doc = "SAI1 Peripheral Clocks Enable"]
11742 pub const fn sai1en(&self) -> super::vals::Apb2enrTim1en {
11743 let val = (self.0 >> 22usize) & 0x01;
11744 super::vals::Apb2enrTim1en(val as u8)
11745 }
11746 #[doc = "SAI1 Peripheral Clocks Enable"]
11747 pub fn set_sai1en(&mut self, val: super::vals::Apb2enrTim1en) {
11748 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
11749 }
11750 #[doc = "SAI2 Peripheral Clocks Enable"]
11751 pub const fn sai2en(&self) -> super::vals::Apb2enrTim1en {
11752 let val = (self.0 >> 23usize) & 0x01;
11753 super::vals::Apb2enrTim1en(val as u8)
11754 }
11755 #[doc = "SAI2 Peripheral Clocks Enable"]
11756 pub fn set_sai2en(&mut self, val: super::vals::Apb2enrTim1en) {
11757 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
11758 }
11759 #[doc = "SAI3 Peripheral Clocks Enable"]
11760 pub const fn sai3en(&self) -> super::vals::Apb2enrTim1en {
11761 let val = (self.0 >> 24usize) & 0x01;
11762 super::vals::Apb2enrTim1en(val as u8)
11763 }
11764 #[doc = "SAI3 Peripheral Clocks Enable"]
11765 pub fn set_sai3en(&mut self, val: super::vals::Apb2enrTim1en) {
11766 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
11767 }
11768 #[doc = "DFSDM1 Peripheral Clocks Enable"]
11769 pub const fn dfsdm1en(&self) -> super::vals::Apb2enrTim1en {
11770 let val = (self.0 >> 28usize) & 0x01;
11771 super::vals::Apb2enrTim1en(val as u8)
11772 }
11773 #[doc = "DFSDM1 Peripheral Clocks Enable"]
11774 pub fn set_dfsdm1en(&mut self, val: super::vals::Apb2enrTim1en) {
11775 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
11776 }
11777 #[doc = "HRTIM peripheral clock enable"]
11778 pub const fn hrtimen(&self) -> super::vals::Apb2enrTim1en {
11779 let val = (self.0 >> 29usize) & 0x01;
11780 super::vals::Apb2enrTim1en(val as u8)
11781 }
11782 #[doc = "HRTIM peripheral clock enable"]
11783 pub fn set_hrtimen(&mut self, val: super::vals::Apb2enrTim1en) {
11784 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
11785 }
11786 }
11787 impl Default for Apb2enr {
11788 fn default() -> Apb2enr {
11789 Apb2enr(0)
11790 }
11791 }
11792 #[doc = "RCC APB1 Clock Register"]
11793 #[repr(transparent)]
11794 #[derive(Copy, Clone, Eq, PartialEq)]
11795 pub struct Apb1henr(pub u32);
11796 impl Apb1henr {
11797 #[doc = "Clock Recovery System peripheral clock enable"]
11798 pub const fn crsen(&self) -> super::vals::Apb1henrCrsen {
11799 let val = (self.0 >> 1usize) & 0x01;
11800 super::vals::Apb1henrCrsen(val as u8)
11801 }
11802 #[doc = "Clock Recovery System peripheral clock enable"]
11803 pub fn set_crsen(&mut self, val: super::vals::Apb1henrCrsen) {
11804 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
11805 }
11806 #[doc = "SWPMI Peripheral Clocks Enable"]
11807 pub const fn swpen(&self) -> super::vals::Apb1henrCrsen {
11808 let val = (self.0 >> 2usize) & 0x01;
11809 super::vals::Apb1henrCrsen(val as u8)
11810 }
11811 #[doc = "SWPMI Peripheral Clocks Enable"]
11812 pub fn set_swpen(&mut self, val: super::vals::Apb1henrCrsen) {
11813 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
11814 }
11815 #[doc = "OPAMP peripheral clock enable"]
11816 pub const fn opampen(&self) -> super::vals::Apb1henrCrsen {
11817 let val = (self.0 >> 4usize) & 0x01;
11818 super::vals::Apb1henrCrsen(val as u8)
11819 }
11820 #[doc = "OPAMP peripheral clock enable"]
11821 pub fn set_opampen(&mut self, val: super::vals::Apb1henrCrsen) {
11822 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
11823 }
11824 #[doc = "MDIOS peripheral clock enable"]
11825 pub const fn mdiosen(&self) -> super::vals::Apb1henrCrsen {
11826 let val = (self.0 >> 5usize) & 0x01;
11827 super::vals::Apb1henrCrsen(val as u8)
11828 }
11829 #[doc = "MDIOS peripheral clock enable"]
11830 pub fn set_mdiosen(&mut self, val: super::vals::Apb1henrCrsen) {
11831 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
11832 }
11833 #[doc = "FDCAN Peripheral Clocks Enable"]
11834 pub const fn fdcanen(&self) -> super::vals::Apb1henrCrsen {
11835 let val = (self.0 >> 8usize) & 0x01;
11836 super::vals::Apb1henrCrsen(val as u8)
11837 }
11838 #[doc = "FDCAN Peripheral Clocks Enable"]
11839 pub fn set_fdcanen(&mut self, val: super::vals::Apb1henrCrsen) {
11840 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
11841 }
11842 }
11843 impl Default for Apb1henr {
11844 fn default() -> Apb1henr {
11845 Apb1henr(0)
11846 }
11847 }
11848 #[doc = "RCC Clock Source Interrupt Clear Register"]
11849 #[repr(transparent)]
11850 #[derive(Copy, Clone, Eq, PartialEq)]
11851 pub struct Cicr(pub u32);
11852 impl Cicr {
11853 #[doc = "LSI ready Interrupt Clear"]
11854 pub const fn lsirdyc(&self) -> super::vals::Lsirdyc {
11855 let val = (self.0 >> 0usize) & 0x01;
11856 super::vals::Lsirdyc(val as u8)
11857 }
11858 #[doc = "LSI ready Interrupt Clear"]
11859 pub fn set_lsirdyc(&mut self, val: super::vals::Lsirdyc) {
11860 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
11861 }
11862 #[doc = "LSE ready Interrupt Clear"]
11863 pub const fn lserdyc(&self) -> super::vals::Lsirdyc {
11864 let val = (self.0 >> 1usize) & 0x01;
11865 super::vals::Lsirdyc(val as u8)
11866 }
11867 #[doc = "LSE ready Interrupt Clear"]
11868 pub fn set_lserdyc(&mut self, val: super::vals::Lsirdyc) {
11869 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
11870 }
11871 #[doc = "HSI ready Interrupt Clear"]
11872 pub const fn hsirdyc(&self) -> super::vals::Lsirdyc {
11873 let val = (self.0 >> 2usize) & 0x01;
11874 super::vals::Lsirdyc(val as u8)
11875 }
11876 #[doc = "HSI ready Interrupt Clear"]
11877 pub fn set_hsirdyc(&mut self, val: super::vals::Lsirdyc) {
11878 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
11879 }
11880 #[doc = "HSE ready Interrupt Clear"]
11881 pub const fn hserdyc(&self) -> super::vals::Lsirdyc {
11882 let val = (self.0 >> 3usize) & 0x01;
11883 super::vals::Lsirdyc(val as u8)
11884 }
11885 #[doc = "HSE ready Interrupt Clear"]
11886 pub fn set_hserdyc(&mut self, val: super::vals::Lsirdyc) {
11887 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
11888 }
11889 #[doc = "CSI ready Interrupt Clear"]
11890 pub const fn hse_ready_interrupt_clear(&self) -> bool {
11891 let val = (self.0 >> 4usize) & 0x01;
11892 val != 0
11893 }
11894 #[doc = "CSI ready Interrupt Clear"]
11895 pub fn set_hse_ready_interrupt_clear(&mut self, val: bool) {
11896 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
11897 }
11898 #[doc = "RC48 ready Interrupt Clear"]
11899 pub const fn hsi48rdyc(&self) -> super::vals::Lsirdyc {
11900 let val = (self.0 >> 5usize) & 0x01;
11901 super::vals::Lsirdyc(val as u8)
11902 }
11903 #[doc = "RC48 ready Interrupt Clear"]
11904 pub fn set_hsi48rdyc(&mut self, val: super::vals::Lsirdyc) {
11905 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
11906 }
11907 #[doc = "PLL1 ready Interrupt Clear"]
11908 pub fn pllrdyc(&self, n: usize) -> super::vals::Lsirdyc {
11909 assert!(n < 3usize);
11910 let offs = 6usize + n * 1usize;
11911 let val = (self.0 >> offs) & 0x01;
11912 super::vals::Lsirdyc(val as u8)
11913 }
11914 #[doc = "PLL1 ready Interrupt Clear"]
11915 pub fn set_pllrdyc(&mut self, n: usize, val: super::vals::Lsirdyc) {
11916 assert!(n < 3usize);
11917 let offs = 6usize + n * 1usize;
11918 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
11919 }
11920 #[doc = "LSE clock security system Interrupt Clear"]
11921 pub const fn lsecssc(&self) -> super::vals::Lsirdyc {
11922 let val = (self.0 >> 9usize) & 0x01;
11923 super::vals::Lsirdyc(val as u8)
11924 }
11925 #[doc = "LSE clock security system Interrupt Clear"]
11926 pub fn set_lsecssc(&mut self, val: super::vals::Lsirdyc) {
11927 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
11928 }
11929 #[doc = "HSE clock security system Interrupt Clear"]
11930 pub const fn hsecssc(&self) -> super::vals::Lsirdyc {
11931 let val = (self.0 >> 10usize) & 0x01;
11932 super::vals::Lsirdyc(val as u8)
11933 }
11934 #[doc = "HSE clock security system Interrupt Clear"]
11935 pub fn set_hsecssc(&mut self, val: super::vals::Lsirdyc) {
11936 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
11937 }
11938 }
11939 impl Default for Cicr {
11940 fn default() -> Cicr {
11941 Cicr(0)
11942 }
11943 }
11944 #[doc = "RCC APB2 Sleep Clock Register"]
11945 #[repr(transparent)]
11946 #[derive(Copy, Clone, Eq, PartialEq)]
11947 pub struct Apb2lpenr(pub u32);
11948 impl Apb2lpenr {
11949 #[doc = "TIM1 peripheral clock enable during CSleep mode"]
11950 pub const fn tim1lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
11951 let val = (self.0 >> 0usize) & 0x01;
11952 super::vals::Apb2lpenrTim1lpen(val as u8)
11953 }
11954 #[doc = "TIM1 peripheral clock enable during CSleep mode"]
11955 pub fn set_tim1lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
11956 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
11957 }
11958 #[doc = "TIM8 peripheral clock enable during CSleep mode"]
11959 pub const fn tim8lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
11960 let val = (self.0 >> 1usize) & 0x01;
11961 super::vals::Apb2lpenrTim1lpen(val as u8)
11962 }
11963 #[doc = "TIM8 peripheral clock enable during CSleep mode"]
11964 pub fn set_tim8lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
11965 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
11966 }
11967 #[doc = "USART1 Peripheral Clocks Enable During CSleep Mode"]
11968 pub const fn usart1lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
11969 let val = (self.0 >> 4usize) & 0x01;
11970 super::vals::Apb2lpenrTim1lpen(val as u8)
11971 }
11972 #[doc = "USART1 Peripheral Clocks Enable During CSleep Mode"]
11973 pub fn set_usart1lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
11974 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
11975 }
11976 #[doc = "USART6 Peripheral Clocks Enable During CSleep Mode"]
11977 pub const fn usart6lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
11978 let val = (self.0 >> 5usize) & 0x01;
11979 super::vals::Apb2lpenrTim1lpen(val as u8)
11980 }
11981 #[doc = "USART6 Peripheral Clocks Enable During CSleep Mode"]
11982 pub fn set_usart6lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
11983 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
11984 }
11985 #[doc = "SPI1 Peripheral Clocks Enable During CSleep Mode"]
11986 pub const fn spi1lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
11987 let val = (self.0 >> 12usize) & 0x01;
11988 super::vals::Apb2lpenrTim1lpen(val as u8)
11989 }
11990 #[doc = "SPI1 Peripheral Clocks Enable During CSleep Mode"]
11991 pub fn set_spi1lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
11992 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
11993 }
11994 #[doc = "SPI4 Peripheral Clocks Enable During CSleep Mode"]
11995 pub const fn spi4lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
11996 let val = (self.0 >> 13usize) & 0x01;
11997 super::vals::Apb2lpenrTim1lpen(val as u8)
11998 }
11999 #[doc = "SPI4 Peripheral Clocks Enable During CSleep Mode"]
12000 pub fn set_spi4lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
12001 self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize);
12002 }
12003 #[doc = "TIM15 peripheral clock enable during CSleep mode"]
12004 pub const fn tim15lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
12005 let val = (self.0 >> 16usize) & 0x01;
12006 super::vals::Apb2lpenrTim1lpen(val as u8)
12007 }
12008 #[doc = "TIM15 peripheral clock enable during CSleep mode"]
12009 pub fn set_tim15lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
12010 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
12011 }
12012 #[doc = "TIM16 peripheral clock enable during CSleep mode"]
12013 pub const fn tim16lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
12014 let val = (self.0 >> 17usize) & 0x01;
12015 super::vals::Apb2lpenrTim1lpen(val as u8)
12016 }
12017 #[doc = "TIM16 peripheral clock enable during CSleep mode"]
12018 pub fn set_tim16lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
12019 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
12020 }
12021 #[doc = "TIM17 peripheral clock enable during CSleep mode"]
12022 pub const fn tim17lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
12023 let val = (self.0 >> 18usize) & 0x01;
12024 super::vals::Apb2lpenrTim1lpen(val as u8)
12025 }
12026 #[doc = "TIM17 peripheral clock enable during CSleep mode"]
12027 pub fn set_tim17lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
12028 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
12029 }
12030 #[doc = "SPI5 Peripheral Clocks Enable During CSleep Mode"]
12031 pub const fn spi5lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
12032 let val = (self.0 >> 20usize) & 0x01;
12033 super::vals::Apb2lpenrTim1lpen(val as u8)
12034 }
12035 #[doc = "SPI5 Peripheral Clocks Enable During CSleep Mode"]
12036 pub fn set_spi5lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
12037 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.0 as u32) & 0x01) << 20usize);
12038 }
12039 #[doc = "SAI1 Peripheral Clocks Enable During CSleep Mode"]
12040 pub const fn sai1lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
12041 let val = (self.0 >> 22usize) & 0x01;
12042 super::vals::Apb2lpenrTim1lpen(val as u8)
12043 }
12044 #[doc = "SAI1 Peripheral Clocks Enable During CSleep Mode"]
12045 pub fn set_sai1lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
12046 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
12047 }
12048 #[doc = "SAI2 Peripheral Clocks Enable During CSleep Mode"]
12049 pub const fn sai2lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
12050 let val = (self.0 >> 23usize) & 0x01;
12051 super::vals::Apb2lpenrTim1lpen(val as u8)
12052 }
12053 #[doc = "SAI2 Peripheral Clocks Enable During CSleep Mode"]
12054 pub fn set_sai2lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
12055 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
12056 }
12057 #[doc = "SAI3 Peripheral Clocks Enable During CSleep Mode"]
12058 pub const fn sai3lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
12059 let val = (self.0 >> 24usize) & 0x01;
12060 super::vals::Apb2lpenrTim1lpen(val as u8)
12061 }
12062 #[doc = "SAI3 Peripheral Clocks Enable During CSleep Mode"]
12063 pub fn set_sai3lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
12064 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
12065 }
12066 #[doc = "DFSDM1 Peripheral Clocks Enable During CSleep Mode"]
12067 pub const fn dfsdm1lpen(&self) -> super::vals::Apb2lpenrTim1lpen {
12068 let val = (self.0 >> 28usize) & 0x01;
12069 super::vals::Apb2lpenrTim1lpen(val as u8)
12070 }
12071 #[doc = "DFSDM1 Peripheral Clocks Enable During CSleep Mode"]
12072 pub fn set_dfsdm1lpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
12073 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
12074 }
12075 #[doc = "HRTIM peripheral clock enable during CSleep mode"]
12076 pub const fn hrtimlpen(&self) -> super::vals::Apb2lpenrTim1lpen {
12077 let val = (self.0 >> 29usize) & 0x01;
12078 super::vals::Apb2lpenrTim1lpen(val as u8)
12079 }
12080 #[doc = "HRTIM peripheral clock enable during CSleep mode"]
12081 pub fn set_hrtimlpen(&mut self, val: super::vals::Apb2lpenrTim1lpen) {
12082 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
12083 }
12084 }
12085 impl Default for Apb2lpenr {
12086 fn default() -> Apb2lpenr {
12087 Apb2lpenr(0)
12088 }
12089 }
12090 #[doc = "RCC Global Control Register"]
12091 #[repr(transparent)]
12092 #[derive(Copy, Clone, Eq, PartialEq)]
12093 pub struct Gcr(pub u32);
12094 impl Gcr {
12095 #[doc = "WWDG1 reset scope control"]
12096 pub const fn ww1rsc(&self) -> super::vals::Ww1rsc {
12097 let val = (self.0 >> 0usize) & 0x01;
12098 super::vals::Ww1rsc(val as u8)
12099 }
12100 #[doc = "WWDG1 reset scope control"]
12101 pub fn set_ww1rsc(&mut self, val: super::vals::Ww1rsc) {
12102 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
12103 }
12104 }
12105 impl Default for Gcr {
12106 fn default() -> Gcr {
12107 Gcr(0)
12108 }
12109 }
12110 #[doc = "RCC APB1 Low Sleep Clock Register"]
12111 #[repr(transparent)]
12112 #[derive(Copy, Clone, Eq, PartialEq)]
12113 pub struct Apb1llpenr(pub u32);
12114 impl Apb1llpenr {
12115 #[doc = "TIM2 peripheral clock enable during CSleep mode"]
12116 pub const fn tim2lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12117 let val = (self.0 >> 0usize) & 0x01;
12118 super::vals::Apb1llpenrTim2lpen(val as u8)
12119 }
12120 #[doc = "TIM2 peripheral clock enable during CSleep mode"]
12121 pub fn set_tim2lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12122 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
12123 }
12124 #[doc = "TIM3 peripheral clock enable during CSleep mode"]
12125 pub const fn tim3lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12126 let val = (self.0 >> 1usize) & 0x01;
12127 super::vals::Apb1llpenrTim2lpen(val as u8)
12128 }
12129 #[doc = "TIM3 peripheral clock enable during CSleep mode"]
12130 pub fn set_tim3lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12131 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
12132 }
12133 #[doc = "TIM4 peripheral clock enable during CSleep mode"]
12134 pub const fn tim4lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12135 let val = (self.0 >> 2usize) & 0x01;
12136 super::vals::Apb1llpenrTim2lpen(val as u8)
12137 }
12138 #[doc = "TIM4 peripheral clock enable during CSleep mode"]
12139 pub fn set_tim4lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12140 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
12141 }
12142 #[doc = "TIM5 peripheral clock enable during CSleep mode"]
12143 pub const fn tim5lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12144 let val = (self.0 >> 3usize) & 0x01;
12145 super::vals::Apb1llpenrTim2lpen(val as u8)
12146 }
12147 #[doc = "TIM5 peripheral clock enable during CSleep mode"]
12148 pub fn set_tim5lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12149 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
12150 }
12151 #[doc = "TIM6 peripheral clock enable during CSleep mode"]
12152 pub const fn tim6lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12153 let val = (self.0 >> 4usize) & 0x01;
12154 super::vals::Apb1llpenrTim2lpen(val as u8)
12155 }
12156 #[doc = "TIM6 peripheral clock enable during CSleep mode"]
12157 pub fn set_tim6lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12158 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
12159 }
12160 #[doc = "TIM7 peripheral clock enable during CSleep mode"]
12161 pub const fn tim7lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12162 let val = (self.0 >> 5usize) & 0x01;
12163 super::vals::Apb1llpenrTim2lpen(val as u8)
12164 }
12165 #[doc = "TIM7 peripheral clock enable during CSleep mode"]
12166 pub fn set_tim7lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12167 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
12168 }
12169 #[doc = "TIM12 peripheral clock enable during CSleep mode"]
12170 pub const fn tim12lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12171 let val = (self.0 >> 6usize) & 0x01;
12172 super::vals::Apb1llpenrTim2lpen(val as u8)
12173 }
12174 #[doc = "TIM12 peripheral clock enable during CSleep mode"]
12175 pub fn set_tim12lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12176 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
12177 }
12178 #[doc = "TIM13 peripheral clock enable during CSleep mode"]
12179 pub const fn tim13lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12180 let val = (self.0 >> 7usize) & 0x01;
12181 super::vals::Apb1llpenrTim2lpen(val as u8)
12182 }
12183 #[doc = "TIM13 peripheral clock enable during CSleep mode"]
12184 pub fn set_tim13lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12185 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
12186 }
12187 #[doc = "TIM14 peripheral clock enable during CSleep mode"]
12188 pub const fn tim14lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12189 let val = (self.0 >> 8usize) & 0x01;
12190 super::vals::Apb1llpenrTim2lpen(val as u8)
12191 }
12192 #[doc = "TIM14 peripheral clock enable during CSleep mode"]
12193 pub fn set_tim14lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12194 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
12195 }
12196 #[doc = "LPTIM1 Peripheral Clocks Enable During CSleep Mode"]
12197 pub const fn lptim1lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12198 let val = (self.0 >> 9usize) & 0x01;
12199 super::vals::Apb1llpenrTim2lpen(val as u8)
12200 }
12201 #[doc = "LPTIM1 Peripheral Clocks Enable During CSleep Mode"]
12202 pub fn set_lptim1lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12203 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
12204 }
12205 #[doc = "SPI2 Peripheral Clocks Enable During CSleep Mode"]
12206 pub const fn spi2lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12207 let val = (self.0 >> 14usize) & 0x01;
12208 super::vals::Apb1llpenrTim2lpen(val as u8)
12209 }
12210 #[doc = "SPI2 Peripheral Clocks Enable During CSleep Mode"]
12211 pub fn set_spi2lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12212 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
12213 }
12214 #[doc = "SPI3 Peripheral Clocks Enable During CSleep Mode"]
12215 pub const fn spi3lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12216 let val = (self.0 >> 15usize) & 0x01;
12217 super::vals::Apb1llpenrTim2lpen(val as u8)
12218 }
12219 #[doc = "SPI3 Peripheral Clocks Enable During CSleep Mode"]
12220 pub fn set_spi3lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12221 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
12222 }
12223 #[doc = "SPDIFRX Peripheral Clocks Enable During CSleep Mode"]
12224 pub const fn spdifrxlpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12225 let val = (self.0 >> 16usize) & 0x01;
12226 super::vals::Apb1llpenrTim2lpen(val as u8)
12227 }
12228 #[doc = "SPDIFRX Peripheral Clocks Enable During CSleep Mode"]
12229 pub fn set_spdifrxlpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12230 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
12231 }
12232 #[doc = "USART2 Peripheral Clocks Enable During CSleep Mode"]
12233 pub const fn usart2lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12234 let val = (self.0 >> 17usize) & 0x01;
12235 super::vals::Apb1llpenrTim2lpen(val as u8)
12236 }
12237 #[doc = "USART2 Peripheral Clocks Enable During CSleep Mode"]
12238 pub fn set_usart2lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12239 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
12240 }
12241 #[doc = "USART3 Peripheral Clocks Enable During CSleep Mode"]
12242 pub const fn usart3lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12243 let val = (self.0 >> 18usize) & 0x01;
12244 super::vals::Apb1llpenrTim2lpen(val as u8)
12245 }
12246 #[doc = "USART3 Peripheral Clocks Enable During CSleep Mode"]
12247 pub fn set_usart3lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12248 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
12249 }
12250 #[doc = "UART4 Peripheral Clocks Enable During CSleep Mode"]
12251 pub const fn uart4lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12252 let val = (self.0 >> 19usize) & 0x01;
12253 super::vals::Apb1llpenrTim2lpen(val as u8)
12254 }
12255 #[doc = "UART4 Peripheral Clocks Enable During CSleep Mode"]
12256 pub fn set_uart4lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12257 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
12258 }
12259 #[doc = "UART5 Peripheral Clocks Enable During CSleep Mode"]
12260 pub const fn uart5lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12261 let val = (self.0 >> 20usize) & 0x01;
12262 super::vals::Apb1llpenrTim2lpen(val as u8)
12263 }
12264 #[doc = "UART5 Peripheral Clocks Enable During CSleep Mode"]
12265 pub fn set_uart5lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12266 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.0 as u32) & 0x01) << 20usize);
12267 }
12268 #[doc = "I2C1 Peripheral Clocks Enable During CSleep Mode"]
12269 pub const fn i2c1lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12270 let val = (self.0 >> 21usize) & 0x01;
12271 super::vals::Apb1llpenrTim2lpen(val as u8)
12272 }
12273 #[doc = "I2C1 Peripheral Clocks Enable During CSleep Mode"]
12274 pub fn set_i2c1lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12275 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
12276 }
12277 #[doc = "I2C2 Peripheral Clocks Enable During CSleep Mode"]
12278 pub const fn i2c2lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12279 let val = (self.0 >> 22usize) & 0x01;
12280 super::vals::Apb1llpenrTim2lpen(val as u8)
12281 }
12282 #[doc = "I2C2 Peripheral Clocks Enable During CSleep Mode"]
12283 pub fn set_i2c2lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12284 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
12285 }
12286 #[doc = "I2C3 Peripheral Clocks Enable During CSleep Mode"]
12287 pub const fn i2c3lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12288 let val = (self.0 >> 23usize) & 0x01;
12289 super::vals::Apb1llpenrTim2lpen(val as u8)
12290 }
12291 #[doc = "I2C3 Peripheral Clocks Enable During CSleep Mode"]
12292 pub fn set_i2c3lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12293 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
12294 }
12295 #[doc = "HDMI-CEC Peripheral Clocks Enable During CSleep Mode"]
12296 pub const fn ceclpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12297 let val = (self.0 >> 27usize) & 0x01;
12298 super::vals::Apb1llpenrTim2lpen(val as u8)
12299 }
12300 #[doc = "HDMI-CEC Peripheral Clocks Enable During CSleep Mode"]
12301 pub fn set_ceclpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12302 self.0 = (self.0 & !(0x01 << 27usize)) | (((val.0 as u32) & 0x01) << 27usize);
12303 }
12304 #[doc = "DAC1/2 peripheral clock enable during CSleep mode"]
12305 pub const fn dac12lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12306 let val = (self.0 >> 29usize) & 0x01;
12307 super::vals::Apb1llpenrTim2lpen(val as u8)
12308 }
12309 #[doc = "DAC1/2 peripheral clock enable during CSleep mode"]
12310 pub fn set_dac12lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12311 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
12312 }
12313 #[doc = "UART7 Peripheral Clocks Enable During CSleep Mode"]
12314 pub const fn uart7lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12315 let val = (self.0 >> 30usize) & 0x01;
12316 super::vals::Apb1llpenrTim2lpen(val as u8)
12317 }
12318 #[doc = "UART7 Peripheral Clocks Enable During CSleep Mode"]
12319 pub fn set_uart7lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12320 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
12321 }
12322 #[doc = "UART8 Peripheral Clocks Enable During CSleep Mode"]
12323 pub const fn uart8lpen(&self) -> super::vals::Apb1llpenrTim2lpen {
12324 let val = (self.0 >> 31usize) & 0x01;
12325 super::vals::Apb1llpenrTim2lpen(val as u8)
12326 }
12327 #[doc = "UART8 Peripheral Clocks Enable During CSleep Mode"]
12328 pub fn set_uart8lpen(&mut self, val: super::vals::Apb1llpenrTim2lpen) {
12329 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
12330 }
12331 }
12332 impl Default for Apb1llpenr {
12333 fn default() -> Apb1llpenr {
12334 Apb1llpenr(0)
12335 }
12336 }
12337 #[doc = "RCC Clock Recovery RC Register"]
12338 #[repr(transparent)]
12339 #[derive(Copy, Clone, Eq, PartialEq)]
12340 pub struct Crrcr(pub u32);
12341 impl Crrcr {
12342 #[doc = "Internal RC 48 MHz clock calibration"]
12343 pub const fn hsi48cal(&self) -> u16 {
12344 let val = (self.0 >> 0usize) & 0x03ff;
12345 val as u16
12346 }
12347 #[doc = "Internal RC 48 MHz clock calibration"]
12348 pub fn set_hsi48cal(&mut self, val: u16) {
12349 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
12350 }
12351 }
12352 impl Default for Crrcr {
12353 fn default() -> Crrcr {
12354 Crrcr(0)
12355 }
12356 }
12357 #[doc = "RCC Internal Clock Source Calibration Register"]
12358 #[repr(transparent)]
12359 #[derive(Copy, Clone, Eq, PartialEq)]
12360 pub struct Icscr(pub u32);
12361 impl Icscr {
12362 #[doc = "HSI clock calibration"]
12363 pub const fn hsical(&self) -> u16 {
12364 let val = (self.0 >> 0usize) & 0x0fff;
12365 val as u16
12366 }
12367 #[doc = "HSI clock calibration"]
12368 pub fn set_hsical(&mut self, val: u16) {
12369 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
12370 }
12371 #[doc = "HSI clock trimming"]
12372 pub const fn hsitrim(&self) -> u8 {
12373 let val = (self.0 >> 12usize) & 0x3f;
12374 val as u8
12375 }
12376 #[doc = "HSI clock trimming"]
12377 pub fn set_hsitrim(&mut self, val: u8) {
12378 self.0 = (self.0 & !(0x3f << 12usize)) | (((val as u32) & 0x3f) << 12usize);
12379 }
12380 #[doc = "CSI clock calibration"]
12381 pub const fn csical(&self) -> u8 {
12382 let val = (self.0 >> 18usize) & 0xff;
12383 val as u8
12384 }
12385 #[doc = "CSI clock calibration"]
12386 pub fn set_csical(&mut self, val: u8) {
12387 self.0 = (self.0 & !(0xff << 18usize)) | (((val as u32) & 0xff) << 18usize);
12388 }
12389 #[doc = "CSI clock trimming"]
12390 pub const fn csitrim(&self) -> u8 {
12391 let val = (self.0 >> 26usize) & 0x1f;
12392 val as u8
12393 }
12394 #[doc = "CSI clock trimming"]
12395 pub fn set_csitrim(&mut self, val: u8) {
12396 self.0 = (self.0 & !(0x1f << 26usize)) | (((val as u32) & 0x1f) << 26usize);
12397 }
12398 }
12399 impl Default for Icscr {
12400 fn default() -> Icscr {
12401 Icscr(0)
12402 }
12403 }
12404 #[doc = "RCC AHB2 Clock Register"]
12405 #[repr(transparent)]
12406 #[derive(Copy, Clone, Eq, PartialEq)]
12407 pub struct Ahb2enr(pub u32);
12408 impl Ahb2enr {
12409 #[doc = "DCMI peripheral clock"]
12410 pub const fn dcmien(&self) -> super::vals::Ahb2enrDcmien {
12411 let val = (self.0 >> 0usize) & 0x01;
12412 super::vals::Ahb2enrDcmien(val as u8)
12413 }
12414 #[doc = "DCMI peripheral clock"]
12415 pub fn set_dcmien(&mut self, val: super::vals::Ahb2enrDcmien) {
12416 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
12417 }
12418 #[doc = "CRYPT peripheral clock enable"]
12419 pub const fn crypten(&self) -> super::vals::Ahb2enrDcmien {
12420 let val = (self.0 >> 4usize) & 0x01;
12421 super::vals::Ahb2enrDcmien(val as u8)
12422 }
12423 #[doc = "CRYPT peripheral clock enable"]
12424 pub fn set_crypten(&mut self, val: super::vals::Ahb2enrDcmien) {
12425 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
12426 }
12427 #[doc = "HASH peripheral clock enable"]
12428 pub const fn hashen(&self) -> super::vals::Ahb2enrDcmien {
12429 let val = (self.0 >> 5usize) & 0x01;
12430 super::vals::Ahb2enrDcmien(val as u8)
12431 }
12432 #[doc = "HASH peripheral clock enable"]
12433 pub fn set_hashen(&mut self, val: super::vals::Ahb2enrDcmien) {
12434 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
12435 }
12436 #[doc = "RNG peripheral clocks enable"]
12437 pub const fn rngen(&self) -> super::vals::Ahb2enrDcmien {
12438 let val = (self.0 >> 6usize) & 0x01;
12439 super::vals::Ahb2enrDcmien(val as u8)
12440 }
12441 #[doc = "RNG peripheral clocks enable"]
12442 pub fn set_rngen(&mut self, val: super::vals::Ahb2enrDcmien) {
12443 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
12444 }
12445 #[doc = "SDMMC2 and SDMMC2 delay clock enable"]
12446 pub const fn sdmmc2en(&self) -> super::vals::Ahb2enrDcmien {
12447 let val = (self.0 >> 9usize) & 0x01;
12448 super::vals::Ahb2enrDcmien(val as u8)
12449 }
12450 #[doc = "SDMMC2 and SDMMC2 delay clock enable"]
12451 pub fn set_sdmmc2en(&mut self, val: super::vals::Ahb2enrDcmien) {
12452 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
12453 }
12454 #[doc = "SRAM1 block enable"]
12455 pub const fn sram1en(&self) -> super::vals::Ahb2enrDcmien {
12456 let val = (self.0 >> 29usize) & 0x01;
12457 super::vals::Ahb2enrDcmien(val as u8)
12458 }
12459 #[doc = "SRAM1 block enable"]
12460 pub fn set_sram1en(&mut self, val: super::vals::Ahb2enrDcmien) {
12461 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
12462 }
12463 #[doc = "SRAM2 block enable"]
12464 pub const fn sram2en(&self) -> super::vals::Ahb2enrDcmien {
12465 let val = (self.0 >> 30usize) & 0x01;
12466 super::vals::Ahb2enrDcmien(val as u8)
12467 }
12468 #[doc = "SRAM2 block enable"]
12469 pub fn set_sram2en(&mut self, val: super::vals::Ahb2enrDcmien) {
12470 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
12471 }
12472 #[doc = "SRAM3 block enable"]
12473 pub const fn sram3en(&self) -> super::vals::Ahb2enrDcmien {
12474 let val = (self.0 >> 31usize) & 0x01;
12475 super::vals::Ahb2enrDcmien(val as u8)
12476 }
12477 #[doc = "SRAM3 block enable"]
12478 pub fn set_sram3en(&mut self, val: super::vals::Ahb2enrDcmien) {
12479 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
12480 }
12481 }
12482 impl Default for Ahb2enr {
12483 fn default() -> Ahb2enr {
12484 Ahb2enr(0)
12485 }
12486 }
12487 #[doc = "RCC APB3 Peripheral Reset Register"]
12488 #[repr(transparent)]
12489 #[derive(Copy, Clone, Eq, PartialEq)]
12490 pub struct Apb3rstr(pub u32);
12491 impl Apb3rstr {
12492 #[doc = "LTDC block reset"]
12493 pub const fn ltdcrst(&self) -> super::vals::Ltdcrst {
12494 let val = (self.0 >> 3usize) & 0x01;
12495 super::vals::Ltdcrst(val as u8)
12496 }
12497 #[doc = "LTDC block reset"]
12498 pub fn set_ltdcrst(&mut self, val: super::vals::Ltdcrst) {
12499 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
12500 }
12501 }
12502 impl Default for Apb3rstr {
12503 fn default() -> Apb3rstr {
12504 Apb3rstr(0)
12505 }
12506 }
12507 #[doc = "clock control register"]
12508 #[repr(transparent)]
12509 #[derive(Copy, Clone, Eq, PartialEq)]
12510 pub struct Cr(pub u32);
12511 impl Cr {
12512 #[doc = "Internal high-speed clock enable"]
12513 pub const fn hsion(&self) -> super::vals::Hsion {
12514 let val = (self.0 >> 0usize) & 0x01;
12515 super::vals::Hsion(val as u8)
12516 }
12517 #[doc = "Internal high-speed clock enable"]
12518 pub fn set_hsion(&mut self, val: super::vals::Hsion) {
12519 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
12520 }
12521 #[doc = "High Speed Internal clock enable in Stop mode"]
12522 pub const fn hsikeron(&self) -> super::vals::Hsion {
12523 let val = (self.0 >> 1usize) & 0x01;
12524 super::vals::Hsion(val as u8)
12525 }
12526 #[doc = "High Speed Internal clock enable in Stop mode"]
12527 pub fn set_hsikeron(&mut self, val: super::vals::Hsion) {
12528 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
12529 }
12530 #[doc = "HSI clock ready flag"]
12531 pub const fn hsirdy(&self) -> bool {
12532 let val = (self.0 >> 2usize) & 0x01;
12533 val != 0
12534 }
12535 #[doc = "HSI clock ready flag"]
12536 pub fn set_hsirdy(&mut self, val: bool) {
12537 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
12538 }
12539 #[doc = "HSI clock divider"]
12540 pub const fn hsidiv(&self) -> super::vals::Hsidiv {
12541 let val = (self.0 >> 3usize) & 0x03;
12542 super::vals::Hsidiv(val as u8)
12543 }
12544 #[doc = "HSI clock divider"]
12545 pub fn set_hsidiv(&mut self, val: super::vals::Hsidiv) {
12546 self.0 = (self.0 & !(0x03 << 3usize)) | (((val.0 as u32) & 0x03) << 3usize);
12547 }
12548 #[doc = "HSI divider flag"]
12549 pub const fn hsidivf(&self) -> bool {
12550 let val = (self.0 >> 5usize) & 0x01;
12551 val != 0
12552 }
12553 #[doc = "HSI divider flag"]
12554 pub fn set_hsidivf(&mut self, val: bool) {
12555 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
12556 }
12557 #[doc = "CSI clock enable"]
12558 pub const fn csion(&self) -> super::vals::Hsion {
12559 let val = (self.0 >> 7usize) & 0x01;
12560 super::vals::Hsion(val as u8)
12561 }
12562 #[doc = "CSI clock enable"]
12563 pub fn set_csion(&mut self, val: super::vals::Hsion) {
12564 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
12565 }
12566 #[doc = "CSI clock ready flag"]
12567 pub const fn csirdy(&self) -> bool {
12568 let val = (self.0 >> 8usize) & 0x01;
12569 val != 0
12570 }
12571 #[doc = "CSI clock ready flag"]
12572 pub fn set_csirdy(&mut self, val: bool) {
12573 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
12574 }
12575 #[doc = "CSI clock enable in Stop mode"]
12576 pub const fn csikeron(&self) -> super::vals::Hsion {
12577 let val = (self.0 >> 9usize) & 0x01;
12578 super::vals::Hsion(val as u8)
12579 }
12580 #[doc = "CSI clock enable in Stop mode"]
12581 pub fn set_csikeron(&mut self, val: super::vals::Hsion) {
12582 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
12583 }
12584 #[doc = "RC48 clock enable"]
12585 pub const fn hsi48on(&self) -> super::vals::Hsion {
12586 let val = (self.0 >> 12usize) & 0x01;
12587 super::vals::Hsion(val as u8)
12588 }
12589 #[doc = "RC48 clock enable"]
12590 pub fn set_hsi48on(&mut self, val: super::vals::Hsion) {
12591 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
12592 }
12593 #[doc = "RC48 clock ready flag"]
12594 pub const fn hsi48rdy(&self) -> bool {
12595 let val = (self.0 >> 13usize) & 0x01;
12596 val != 0
12597 }
12598 #[doc = "RC48 clock ready flag"]
12599 pub fn set_hsi48rdy(&mut self, val: bool) {
12600 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
12601 }
12602 #[doc = "D1 domain clocks ready flag"]
12603 pub const fn d1ckrdy(&self) -> bool {
12604 let val = (self.0 >> 14usize) & 0x01;
12605 val != 0
12606 }
12607 #[doc = "D1 domain clocks ready flag"]
12608 pub fn set_d1ckrdy(&mut self, val: bool) {
12609 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
12610 }
12611 #[doc = "D2 domain clocks ready flag"]
12612 pub const fn d2ckrdy(&self) -> bool {
12613 let val = (self.0 >> 15usize) & 0x01;
12614 val != 0
12615 }
12616 #[doc = "D2 domain clocks ready flag"]
12617 pub fn set_d2ckrdy(&mut self, val: bool) {
12618 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
12619 }
12620 #[doc = "HSE clock enable"]
12621 pub const fn hseon(&self) -> super::vals::Hsion {
12622 let val = (self.0 >> 16usize) & 0x01;
12623 super::vals::Hsion(val as u8)
12624 }
12625 #[doc = "HSE clock enable"]
12626 pub fn set_hseon(&mut self, val: super::vals::Hsion) {
12627 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
12628 }
12629 #[doc = "HSE clock ready flag"]
12630 pub const fn hserdy(&self) -> bool {
12631 let val = (self.0 >> 17usize) & 0x01;
12632 val != 0
12633 }
12634 #[doc = "HSE clock ready flag"]
12635 pub fn set_hserdy(&mut self, val: bool) {
12636 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
12637 }
12638 #[doc = "HSE clock bypass"]
12639 pub const fn hsebyp(&self) -> super::vals::Hsebyp {
12640 let val = (self.0 >> 18usize) & 0x01;
12641 super::vals::Hsebyp(val as u8)
12642 }
12643 #[doc = "HSE clock bypass"]
12644 pub fn set_hsebyp(&mut self, val: super::vals::Hsebyp) {
12645 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
12646 }
12647 #[doc = "HSE Clock Security System enable"]
12648 pub const fn hsecsson(&self) -> super::vals::Hsion {
12649 let val = (self.0 >> 19usize) & 0x01;
12650 super::vals::Hsion(val as u8)
12651 }
12652 #[doc = "HSE Clock Security System enable"]
12653 pub fn set_hsecsson(&mut self, val: super::vals::Hsion) {
12654 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
12655 }
12656 #[doc = "PLL1 enable"]
12657 pub const fn pll1on(&self) -> super::vals::Hsion {
12658 let val = (self.0 >> 24usize) & 0x01;
12659 super::vals::Hsion(val as u8)
12660 }
12661 #[doc = "PLL1 enable"]
12662 pub fn set_pll1on(&mut self, val: super::vals::Hsion) {
12663 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
12664 }
12665 #[doc = "PLL1 clock ready flag"]
12666 pub const fn pll1rdy(&self) -> bool {
12667 let val = (self.0 >> 25usize) & 0x01;
12668 val != 0
12669 }
12670 #[doc = "PLL1 clock ready flag"]
12671 pub fn set_pll1rdy(&mut self, val: bool) {
12672 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
12673 }
12674 #[doc = "PLL2 enable"]
12675 pub const fn pll2on(&self) -> super::vals::Hsion {
12676 let val = (self.0 >> 26usize) & 0x01;
12677 super::vals::Hsion(val as u8)
12678 }
12679 #[doc = "PLL2 enable"]
12680 pub fn set_pll2on(&mut self, val: super::vals::Hsion) {
12681 self.0 = (self.0 & !(0x01 << 26usize)) | (((val.0 as u32) & 0x01) << 26usize);
12682 }
12683 #[doc = "PLL2 clock ready flag"]
12684 pub const fn pll2rdy(&self) -> bool {
12685 let val = (self.0 >> 27usize) & 0x01;
12686 val != 0
12687 }
12688 #[doc = "PLL2 clock ready flag"]
12689 pub fn set_pll2rdy(&mut self, val: bool) {
12690 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
12691 }
12692 #[doc = "PLL3 enable"]
12693 pub const fn pll3on(&self) -> super::vals::Hsion {
12694 let val = (self.0 >> 28usize) & 0x01;
12695 super::vals::Hsion(val as u8)
12696 }
12697 #[doc = "PLL3 enable"]
12698 pub fn set_pll3on(&mut self, val: super::vals::Hsion) {
12699 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
12700 }
12701 #[doc = "PLL3 clock ready flag"]
12702 pub const fn pll3rdy(&self) -> bool {
12703 let val = (self.0 >> 29usize) & 0x01;
12704 val != 0
12705 }
12706 #[doc = "PLL3 clock ready flag"]
12707 pub fn set_pll3rdy(&mut self, val: bool) {
12708 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
12709 }
12710 }
12711 impl Default for Cr {
12712 fn default() -> Cr {
12713 Cr(0)
12714 }
12715 }
12716 #[doc = "RCC PLL1 Fractional Divider Register"]
12717 #[repr(transparent)]
12718 #[derive(Copy, Clone, Eq, PartialEq)]
12719 pub struct Pll1fracr(pub u32);
12720 impl Pll1fracr {
12721 #[doc = "Fractional part of the multiplication factor for PLL1 VCO"]
12722 pub const fn fracn1(&self) -> u16 {
12723 let val = (self.0 >> 3usize) & 0x1fff;
12724 val as u16
12725 }
12726 #[doc = "Fractional part of the multiplication factor for PLL1 VCO"]
12727 pub fn set_fracn1(&mut self, val: u16) {
12728 self.0 = (self.0 & !(0x1fff << 3usize)) | (((val as u32) & 0x1fff) << 3usize);
12729 }
12730 }
12731 impl Default for Pll1fracr {
12732 fn default() -> Pll1fracr {
12733 Pll1fracr(0)
12734 }
12735 }
12736 #[doc = "RCC Reset Status Register"]
12737 #[repr(transparent)]
12738 #[derive(Copy, Clone, Eq, PartialEq)]
12739 pub struct C1Rsr(pub u32);
12740 impl C1Rsr {
12741 #[doc = "Remove reset flag"]
12742 pub const fn rmvf(&self) -> super::vals::C1RsrRmvf {
12743 let val = (self.0 >> 16usize) & 0x01;
12744 super::vals::C1RsrRmvf(val as u8)
12745 }
12746 #[doc = "Remove reset flag"]
12747 pub fn set_rmvf(&mut self, val: super::vals::C1RsrRmvf) {
12748 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
12749 }
12750 #[doc = "CPU reset flag"]
12751 pub const fn cpurstf(&self) -> bool {
12752 let val = (self.0 >> 17usize) & 0x01;
12753 val != 0
12754 }
12755 #[doc = "CPU reset flag"]
12756 pub fn set_cpurstf(&mut self, val: bool) {
12757 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
12758 }
12759 #[doc = "D1 domain power switch reset flag"]
12760 pub const fn d1rstf(&self) -> bool {
12761 let val = (self.0 >> 19usize) & 0x01;
12762 val != 0
12763 }
12764 #[doc = "D1 domain power switch reset flag"]
12765 pub fn set_d1rstf(&mut self, val: bool) {
12766 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
12767 }
12768 #[doc = "D2 domain power switch reset flag"]
12769 pub const fn d2rstf(&self) -> bool {
12770 let val = (self.0 >> 20usize) & 0x01;
12771 val != 0
12772 }
12773 #[doc = "D2 domain power switch reset flag"]
12774 pub fn set_d2rstf(&mut self, val: bool) {
12775 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
12776 }
12777 #[doc = "BOR reset flag"]
12778 pub const fn borrstf(&self) -> bool {
12779 let val = (self.0 >> 21usize) & 0x01;
12780 val != 0
12781 }
12782 #[doc = "BOR reset flag"]
12783 pub fn set_borrstf(&mut self, val: bool) {
12784 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
12785 }
12786 #[doc = "Pin reset flag (NRST)"]
12787 pub const fn pinrstf(&self) -> bool {
12788 let val = (self.0 >> 22usize) & 0x01;
12789 val != 0
12790 }
12791 #[doc = "Pin reset flag (NRST)"]
12792 pub fn set_pinrstf(&mut self, val: bool) {
12793 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
12794 }
12795 #[doc = "POR/PDR reset flag"]
12796 pub const fn porrstf(&self) -> bool {
12797 let val = (self.0 >> 23usize) & 0x01;
12798 val != 0
12799 }
12800 #[doc = "POR/PDR reset flag"]
12801 pub fn set_porrstf(&mut self, val: bool) {
12802 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
12803 }
12804 #[doc = "System reset from CPU reset flag"]
12805 pub const fn sftrstf(&self) -> bool {
12806 let val = (self.0 >> 24usize) & 0x01;
12807 val != 0
12808 }
12809 #[doc = "System reset from CPU reset flag"]
12810 pub fn set_sftrstf(&mut self, val: bool) {
12811 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
12812 }
12813 #[doc = "Independent Watchdog reset flag"]
12814 pub const fn iwdg1rstf(&self) -> bool {
12815 let val = (self.0 >> 26usize) & 0x01;
12816 val != 0
12817 }
12818 #[doc = "Independent Watchdog reset flag"]
12819 pub fn set_iwdg1rstf(&mut self, val: bool) {
12820 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
12821 }
12822 #[doc = "Window Watchdog reset flag"]
12823 pub const fn wwdg1rstf(&self) -> bool {
12824 let val = (self.0 >> 28usize) & 0x01;
12825 val != 0
12826 }
12827 #[doc = "Window Watchdog reset flag"]
12828 pub fn set_wwdg1rstf(&mut self, val: bool) {
12829 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
12830 }
12831 #[doc = "Reset due to illegal D1 DStandby or CPU CStop flag"]
12832 pub const fn lpwrrstf(&self) -> bool {
12833 let val = (self.0 >> 30usize) & 0x01;
9315 val != 0 12834 val != 0
9316 } 12835 }
12836 #[doc = "Reset due to illegal D1 DStandby or CPU CStop flag"]
12837 pub fn set_lpwrrstf(&mut self, val: bool) {
12838 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
12839 }
12840 }
12841 impl Default for C1Rsr {
12842 fn default() -> C1Rsr {
12843 C1Rsr(0)
12844 }
12845 }
12846 #[doc = "RCC APB4 Peripheral Reset Register"]
12847 #[repr(transparent)]
12848 #[derive(Copy, Clone, Eq, PartialEq)]
12849 pub struct Apb4rstr(pub u32);
12850 impl Apb4rstr {
12851 #[doc = "SYSCFG block reset"]
12852 pub const fn syscfgrst(&self) -> super::vals::Syscfgrst {
12853 let val = (self.0 >> 1usize) & 0x01;
12854 super::vals::Syscfgrst(val as u8)
12855 }
12856 #[doc = "SYSCFG block reset"]
12857 pub fn set_syscfgrst(&mut self, val: super::vals::Syscfgrst) {
12858 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
12859 }
12860 #[doc = "LPUART1 block reset"]
12861 pub const fn lpuart1rst(&self) -> super::vals::Syscfgrst {
12862 let val = (self.0 >> 3usize) & 0x01;
12863 super::vals::Syscfgrst(val as u8)
12864 }
12865 #[doc = "LPUART1 block reset"]
12866 pub fn set_lpuart1rst(&mut self, val: super::vals::Syscfgrst) {
12867 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
12868 }
12869 #[doc = "SPI6 block reset"]
12870 pub const fn spi6rst(&self) -> super::vals::Syscfgrst {
12871 let val = (self.0 >> 5usize) & 0x01;
12872 super::vals::Syscfgrst(val as u8)
12873 }
12874 #[doc = "SPI6 block reset"]
12875 pub fn set_spi6rst(&mut self, val: super::vals::Syscfgrst) {
12876 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
12877 }
12878 #[doc = "I2C4 block reset"]
12879 pub const fn i2c4rst(&self) -> super::vals::Syscfgrst {
12880 let val = (self.0 >> 7usize) & 0x01;
12881 super::vals::Syscfgrst(val as u8)
12882 }
12883 #[doc = "I2C4 block reset"]
12884 pub fn set_i2c4rst(&mut self, val: super::vals::Syscfgrst) {
12885 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
12886 }
12887 #[doc = "LPTIM2 block reset"]
12888 pub const fn lptim2rst(&self) -> super::vals::Syscfgrst {
12889 let val = (self.0 >> 9usize) & 0x01;
12890 super::vals::Syscfgrst(val as u8)
12891 }
12892 #[doc = "LPTIM2 block reset"]
12893 pub fn set_lptim2rst(&mut self, val: super::vals::Syscfgrst) {
12894 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
12895 }
12896 #[doc = "LPTIM3 block reset"]
12897 pub const fn lptim3rst(&self) -> super::vals::Syscfgrst {
12898 let val = (self.0 >> 10usize) & 0x01;
12899 super::vals::Syscfgrst(val as u8)
12900 }
12901 #[doc = "LPTIM3 block reset"]
12902 pub fn set_lptim3rst(&mut self, val: super::vals::Syscfgrst) {
12903 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
12904 }
12905 #[doc = "LPTIM4 block reset"]
12906 pub const fn lptim4rst(&self) -> super::vals::Syscfgrst {
12907 let val = (self.0 >> 11usize) & 0x01;
12908 super::vals::Syscfgrst(val as u8)
12909 }
12910 #[doc = "LPTIM4 block reset"]
12911 pub fn set_lptim4rst(&mut self, val: super::vals::Syscfgrst) {
12912 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
12913 }
12914 #[doc = "LPTIM5 block reset"]
12915 pub const fn lptim5rst(&self) -> super::vals::Syscfgrst {
12916 let val = (self.0 >> 12usize) & 0x01;
12917 super::vals::Syscfgrst(val as u8)
12918 }
12919 #[doc = "LPTIM5 block reset"]
12920 pub fn set_lptim5rst(&mut self, val: super::vals::Syscfgrst) {
12921 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
12922 }
12923 #[doc = "COMP12 Blocks Reset"]
12924 pub const fn comp12rst(&self) -> super::vals::Syscfgrst {
12925 let val = (self.0 >> 14usize) & 0x01;
12926 super::vals::Syscfgrst(val as u8)
12927 }
12928 #[doc = "COMP12 Blocks Reset"]
12929 pub fn set_comp12rst(&mut self, val: super::vals::Syscfgrst) {
12930 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
12931 }
12932 #[doc = "VREF block reset"]
12933 pub const fn vrefrst(&self) -> super::vals::Syscfgrst {
12934 let val = (self.0 >> 15usize) & 0x01;
12935 super::vals::Syscfgrst(val as u8)
12936 }
12937 #[doc = "VREF block reset"]
12938 pub fn set_vrefrst(&mut self, val: super::vals::Syscfgrst) {
12939 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
12940 }
12941 #[doc = "SAI4 block reset"]
12942 pub const fn sai4rst(&self) -> super::vals::Syscfgrst {
12943 let val = (self.0 >> 21usize) & 0x01;
12944 super::vals::Syscfgrst(val as u8)
12945 }
12946 #[doc = "SAI4 block reset"]
12947 pub fn set_sai4rst(&mut self, val: super::vals::Syscfgrst) {
12948 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
12949 }
12950 }
12951 impl Default for Apb4rstr {
12952 fn default() -> Apb4rstr {
12953 Apb4rstr(0)
12954 }
12955 }
12956 #[doc = "RCC PLLs Configuration Register"]
12957 #[repr(transparent)]
12958 #[derive(Copy, Clone, Eq, PartialEq)]
12959 pub struct Pllcfgr(pub u32);
12960 impl Pllcfgr {
12961 #[doc = "PLL1 fractional latch enable"]
12962 pub fn pllfracen(&self, n: usize) -> super::vals::Pll1fracen {
12963 assert!(n < 3usize);
12964 let offs = 0usize + n * 4usize;
12965 let val = (self.0 >> offs) & 0x01;
12966 super::vals::Pll1fracen(val as u8)
12967 }
12968 #[doc = "PLL1 fractional latch enable"]
12969 pub fn set_pllfracen(&mut self, n: usize, val: super::vals::Pll1fracen) {
12970 assert!(n < 3usize);
12971 let offs = 0usize + n * 4usize;
12972 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
12973 }
12974 #[doc = "PLL1 VCO selection"]
12975 pub fn pllvcosel(&self, n: usize) -> super::vals::Pll1vcosel {
12976 assert!(n < 3usize);
12977 let offs = 1usize + n * 4usize;
12978 let val = (self.0 >> offs) & 0x01;
12979 super::vals::Pll1vcosel(val as u8)
12980 }
12981 #[doc = "PLL1 VCO selection"]
12982 pub fn set_pllvcosel(&mut self, n: usize, val: super::vals::Pll1vcosel) {
12983 assert!(n < 3usize);
12984 let offs = 1usize + n * 4usize;
12985 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
12986 }
12987 #[doc = "PLL1 input frequency range"]
12988 pub fn pllrge(&self, n: usize) -> super::vals::Pll1rge {
12989 assert!(n < 3usize);
12990 let offs = 2usize + n * 4usize;
12991 let val = (self.0 >> offs) & 0x03;
12992 super::vals::Pll1rge(val as u8)
12993 }
12994 #[doc = "PLL1 input frequency range"]
12995 pub fn set_pllrge(&mut self, n: usize, val: super::vals::Pll1rge) {
12996 assert!(n < 3usize);
12997 let offs = 2usize + n * 4usize;
12998 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
12999 }
13000 #[doc = "PLL1 DIVP divider output enable"]
13001 pub fn divpen(&self, n: usize) -> super::vals::Divp1en {
13002 assert!(n < 3usize);
13003 let offs = 16usize + n * 3usize;
13004 let val = (self.0 >> offs) & 0x01;
13005 super::vals::Divp1en(val as u8)
13006 }
13007 #[doc = "PLL1 DIVP divider output enable"]
13008 pub fn set_divpen(&mut self, n: usize, val: super::vals::Divp1en) {
13009 assert!(n < 3usize);
13010 let offs = 16usize + n * 3usize;
13011 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
13012 }
13013 #[doc = "PLL1 DIVQ divider output enable"]
13014 pub fn divqen(&self, n: usize) -> super::vals::Divp1en {
13015 assert!(n < 3usize);
13016 let offs = 17usize + n * 3usize;
13017 let val = (self.0 >> offs) & 0x01;
13018 super::vals::Divp1en(val as u8)
13019 }
13020 #[doc = "PLL1 DIVQ divider output enable"]
13021 pub fn set_divqen(&mut self, n: usize, val: super::vals::Divp1en) {
13022 assert!(n < 3usize);
13023 let offs = 17usize + n * 3usize;
13024 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
13025 }
13026 #[doc = "PLL1 DIVR divider output enable"]
13027 pub fn divren(&self, n: usize) -> super::vals::Divp1en {
13028 assert!(n < 3usize);
13029 let offs = 18usize + n * 3usize;
13030 let val = (self.0 >> offs) & 0x01;
13031 super::vals::Divp1en(val as u8)
13032 }
13033 #[doc = "PLL1 DIVR divider output enable"]
13034 pub fn set_divren(&mut self, n: usize, val: super::vals::Divp1en) {
13035 assert!(n < 3usize);
13036 let offs = 18usize + n * 3usize;
13037 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
13038 }
13039 }
13040 impl Default for Pllcfgr {
13041 fn default() -> Pllcfgr {
13042 Pllcfgr(0)
13043 }
13044 }
13045 #[doc = "RCC PLL2 Dividers Configuration Register"]
13046 #[repr(transparent)]
13047 #[derive(Copy, Clone, Eq, PartialEq)]
13048 pub struct Pll2divr(pub u32);
13049 impl Pll2divr {
13050 #[doc = "Multiplication factor for PLL1 VCO"]
13051 pub const fn divn2(&self) -> u16 {
13052 let val = (self.0 >> 0usize) & 0x01ff;
13053 val as u16
13054 }
13055 #[doc = "Multiplication factor for PLL1 VCO"]
13056 pub fn set_divn2(&mut self, val: u16) {
13057 self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
13058 }
13059 #[doc = "PLL1 DIVP division factor"]
13060 pub const fn divp2(&self) -> u8 {
13061 let val = (self.0 >> 9usize) & 0x7f;
13062 val as u8
13063 }
13064 #[doc = "PLL1 DIVP division factor"]
13065 pub fn set_divp2(&mut self, val: u8) {
13066 self.0 = (self.0 & !(0x7f << 9usize)) | (((val as u32) & 0x7f) << 9usize);
13067 }
13068 #[doc = "PLL1 DIVQ division factor"]
13069 pub const fn divq2(&self) -> u8 {
13070 let val = (self.0 >> 16usize) & 0x7f;
13071 val as u8
13072 }
13073 #[doc = "PLL1 DIVQ division factor"]
13074 pub fn set_divq2(&mut self, val: u8) {
13075 self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
13076 }
13077 #[doc = "PLL1 DIVR division factor"]
13078 pub const fn divr2(&self) -> u8 {
13079 let val = (self.0 >> 24usize) & 0x7f;
13080 val as u8
13081 }
13082 #[doc = "PLL1 DIVR division factor"]
13083 pub fn set_divr2(&mut self, val: u8) {
13084 self.0 = (self.0 & !(0x7f << 24usize)) | (((val as u32) & 0x7f) << 24usize);
13085 }
13086 }
13087 impl Default for Pll2divr {
13088 fn default() -> Pll2divr {
13089 Pll2divr(0)
13090 }
13091 }
13092 #[doc = "RCC Domain 3 Clock Configuration Register"]
13093 #[repr(transparent)]
13094 #[derive(Copy, Clone, Eq, PartialEq)]
13095 pub struct D3cfgr(pub u32);
13096 impl D3cfgr {
13097 #[doc = "D3 domain APB4 prescaler"]
13098 pub const fn d3ppre(&self) -> super::vals::D3ppre {
13099 let val = (self.0 >> 4usize) & 0x07;
13100 super::vals::D3ppre(val as u8)
13101 }
13102 #[doc = "D3 domain APB4 prescaler"]
13103 pub fn set_d3ppre(&mut self, val: super::vals::D3ppre) {
13104 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
13105 }
13106 }
13107 impl Default for D3cfgr {
13108 fn default() -> D3cfgr {
13109 D3cfgr(0)
13110 }
13111 }
13112 #[doc = "RCC AHB4 Clock Register"]
13113 #[repr(transparent)]
13114 #[derive(Copy, Clone, Eq, PartialEq)]
13115 pub struct C1Ahb4enr(pub u32);
13116 impl C1Ahb4enr {
13117 #[doc = "0GPIO peripheral clock enable"]
13118 pub const fn gpioaen(&self) -> super::vals::C1Ahb4enrGpioaen {
13119 let val = (self.0 >> 0usize) & 0x01;
13120 super::vals::C1Ahb4enrGpioaen(val as u8)
13121 }
13122 #[doc = "0GPIO peripheral clock enable"]
13123 pub fn set_gpioaen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13124 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
13125 }
13126 #[doc = "0GPIO peripheral clock enable"]
13127 pub const fn gpioben(&self) -> super::vals::C1Ahb4enrGpioaen {
13128 let val = (self.0 >> 1usize) & 0x01;
13129 super::vals::C1Ahb4enrGpioaen(val as u8)
13130 }
13131 #[doc = "0GPIO peripheral clock enable"]
13132 pub fn set_gpioben(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13133 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
13134 }
13135 #[doc = "0GPIO peripheral clock enable"]
13136 pub const fn gpiocen(&self) -> super::vals::C1Ahb4enrGpioaen {
13137 let val = (self.0 >> 2usize) & 0x01;
13138 super::vals::C1Ahb4enrGpioaen(val as u8)
13139 }
13140 #[doc = "0GPIO peripheral clock enable"]
13141 pub fn set_gpiocen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13142 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
13143 }
13144 #[doc = "0GPIO peripheral clock enable"]
13145 pub const fn gpioden(&self) -> super::vals::C1Ahb4enrGpioaen {
13146 let val = (self.0 >> 3usize) & 0x01;
13147 super::vals::C1Ahb4enrGpioaen(val as u8)
13148 }
13149 #[doc = "0GPIO peripheral clock enable"]
13150 pub fn set_gpioden(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13151 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
13152 }
13153 #[doc = "0GPIO peripheral clock enable"]
13154 pub const fn gpioeen(&self) -> super::vals::C1Ahb4enrGpioaen {
13155 let val = (self.0 >> 4usize) & 0x01;
13156 super::vals::C1Ahb4enrGpioaen(val as u8)
13157 }
13158 #[doc = "0GPIO peripheral clock enable"]
13159 pub fn set_gpioeen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13160 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
13161 }
13162 #[doc = "0GPIO peripheral clock enable"]
13163 pub const fn gpiofen(&self) -> super::vals::C1Ahb4enrGpioaen {
13164 let val = (self.0 >> 5usize) & 0x01;
13165 super::vals::C1Ahb4enrGpioaen(val as u8)
13166 }
13167 #[doc = "0GPIO peripheral clock enable"]
13168 pub fn set_gpiofen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13169 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
13170 }
13171 #[doc = "0GPIO peripheral clock enable"]
13172 pub const fn gpiogen(&self) -> super::vals::C1Ahb4enrGpioaen {
13173 let val = (self.0 >> 6usize) & 0x01;
13174 super::vals::C1Ahb4enrGpioaen(val as u8)
13175 }
13176 #[doc = "0GPIO peripheral clock enable"]
13177 pub fn set_gpiogen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13178 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
13179 }
13180 #[doc = "0GPIO peripheral clock enable"]
13181 pub const fn gpiohen(&self) -> super::vals::C1Ahb4enrGpioaen {
13182 let val = (self.0 >> 7usize) & 0x01;
13183 super::vals::C1Ahb4enrGpioaen(val as u8)
13184 }
13185 #[doc = "0GPIO peripheral clock enable"]
13186 pub fn set_gpiohen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13187 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
13188 }
13189 #[doc = "0GPIO peripheral clock enable"]
13190 pub const fn gpioien(&self) -> super::vals::C1Ahb4enrGpioaen {
13191 let val = (self.0 >> 8usize) & 0x01;
13192 super::vals::C1Ahb4enrGpioaen(val as u8)
13193 }
13194 #[doc = "0GPIO peripheral clock enable"]
13195 pub fn set_gpioien(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13196 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
13197 }
13198 #[doc = "0GPIO peripheral clock enable"]
13199 pub const fn gpiojen(&self) -> super::vals::C1Ahb4enrGpioaen {
13200 let val = (self.0 >> 9usize) & 0x01;
13201 super::vals::C1Ahb4enrGpioaen(val as u8)
13202 }
13203 #[doc = "0GPIO peripheral clock enable"]
13204 pub fn set_gpiojen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13205 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
13206 }
13207 #[doc = "0GPIO peripheral clock enable"]
13208 pub const fn gpioken(&self) -> super::vals::C1Ahb4enrGpioaen {
13209 let val = (self.0 >> 10usize) & 0x01;
13210 super::vals::C1Ahb4enrGpioaen(val as u8)
13211 }
13212 #[doc = "0GPIO peripheral clock enable"]
13213 pub fn set_gpioken(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13214 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
13215 }
13216 #[doc = "CRC peripheral clock enable"]
13217 pub const fn crcen(&self) -> super::vals::C1Ahb4enrGpioaen {
13218 let val = (self.0 >> 19usize) & 0x01;
13219 super::vals::C1Ahb4enrGpioaen(val as u8)
13220 }
13221 #[doc = "CRC peripheral clock enable"]
13222 pub fn set_crcen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13223 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
13224 }
13225 #[doc = "BDMA and DMAMUX2 Clock Enable"]
13226 pub const fn bdmaen(&self) -> super::vals::C1Ahb4enrGpioaen {
13227 let val = (self.0 >> 21usize) & 0x01;
13228 super::vals::C1Ahb4enrGpioaen(val as u8)
13229 }
13230 #[doc = "BDMA and DMAMUX2 Clock Enable"]
13231 pub fn set_bdmaen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13232 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
13233 }
13234 #[doc = "ADC3 Peripheral Clocks Enable"]
13235 pub const fn adc3en(&self) -> super::vals::C1Ahb4enrGpioaen {
13236 let val = (self.0 >> 24usize) & 0x01;
13237 super::vals::C1Ahb4enrGpioaen(val as u8)
13238 }
13239 #[doc = "ADC3 Peripheral Clocks Enable"]
13240 pub fn set_adc3en(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13241 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
13242 }
13243 #[doc = "HSEM peripheral clock enable"]
13244 pub const fn hsemen(&self) -> super::vals::C1Ahb4enrGpioaen {
13245 let val = (self.0 >> 25usize) & 0x01;
13246 super::vals::C1Ahb4enrGpioaen(val as u8)
13247 }
13248 #[doc = "HSEM peripheral clock enable"]
13249 pub fn set_hsemen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13250 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.0 as u32) & 0x01) << 25usize);
13251 }
13252 #[doc = "Backup RAM Clock Enable"]
13253 pub const fn bkpramen(&self) -> super::vals::C1Ahb4enrGpioaen {
13254 let val = (self.0 >> 28usize) & 0x01;
13255 super::vals::C1Ahb4enrGpioaen(val as u8)
13256 }
13257 #[doc = "Backup RAM Clock Enable"]
13258 pub fn set_bkpramen(&mut self, val: super::vals::C1Ahb4enrGpioaen) {
13259 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
13260 }
13261 }
13262 impl Default for C1Ahb4enr {
13263 fn default() -> C1Ahb4enr {
13264 C1Ahb4enr(0)
13265 }
13266 }
13267 #[doc = "RCC AHB3 Sleep Clock Register"]
13268 #[repr(transparent)]
13269 #[derive(Copy, Clone, Eq, PartialEq)]
13270 pub struct C1Ahb3lpenr(pub u32);
13271 impl C1Ahb3lpenr {
13272 #[doc = "MDMA Clock Enable During CSleep Mode"]
13273 pub const fn mdmalpen(&self) -> super::vals::C1Ahb3lpenrMdmalpen {
13274>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
13275 let val = (self.0 >> 0usize) & 0x01;
13276 super::vals::C1Ahb3lpenrMdmalpen(val as u8)
13277 }
13278<<<<<<< HEAD
9317 #[doc = "RXP Interrupt Enable"] 13279 #[doc = "RXP Interrupt Enable"]
9318 pub fn set_rxpie(&mut self, val: bool) { 13280 pub fn set_rxpie(&mut self, val: bool) {
9319 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 13281 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
@@ -9421,9 +13383,119 @@ pub mod spi_v3 {
9421 impl Cr1 { 13383 impl Cr1 {
9422 #[doc = "Serial Peripheral Enable"] 13384 #[doc = "Serial Peripheral Enable"]
9423 pub const fn spe(&self) -> bool { 13385 pub const fn spe(&self) -> bool {
9424 let val = (self.0 >> 0usize) & 0x01; 13386=======
13387 #[doc = "MDMA Clock Enable During CSleep Mode"]
13388 pub fn set_mdmalpen(&mut self, val: super::vals::C1Ahb3lpenrMdmalpen) {
13389 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
13390 }
13391 #[doc = "DMA2D Clock Enable During CSleep Mode"]
13392 pub const fn dma2dlpen(&self) -> super::vals::C1Ahb3lpenrMdmalpen {
13393 let val = (self.0 >> 4usize) & 0x01;
13394 super::vals::C1Ahb3lpenrMdmalpen(val as u8)
13395 }
13396 #[doc = "DMA2D Clock Enable During CSleep Mode"]
13397 pub fn set_dma2dlpen(&mut self, val: super::vals::C1Ahb3lpenrMdmalpen) {
13398 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
13399 }
13400 #[doc = "JPGDEC Clock Enable During CSleep Mode"]
13401 pub const fn jpgdeclpen(&self) -> super::vals::C1Ahb3lpenrMdmalpen {
13402 let val = (self.0 >> 5usize) & 0x01;
13403 super::vals::C1Ahb3lpenrMdmalpen(val as u8)
13404 }
13405 #[doc = "JPGDEC Clock Enable During CSleep Mode"]
13406 pub fn set_jpgdeclpen(&mut self, val: super::vals::C1Ahb3lpenrMdmalpen) {
13407 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
13408 }
13409 #[doc = "Flash interface clock enable during csleep mode"]
13410 pub const fn flashpren(&self) -> bool {
13411 let val = (self.0 >> 8usize) & 0x01;
9425 val != 0 13412 val != 0
9426 } 13413 }
13414 #[doc = "Flash interface clock enable during csleep mode"]
13415 pub fn set_flashpren(&mut self, val: bool) {
13416 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
13417 }
13418 #[doc = "FMC Peripheral Clocks Enable During CSleep Mode"]
13419 pub const fn fmclpen(&self) -> super::vals::C1Ahb3lpenrMdmalpen {
13420 let val = (self.0 >> 12usize) & 0x01;
13421 super::vals::C1Ahb3lpenrMdmalpen(val as u8)
13422 }
13423 #[doc = "FMC Peripheral Clocks Enable During CSleep Mode"]
13424 pub fn set_fmclpen(&mut self, val: super::vals::C1Ahb3lpenrMdmalpen) {
13425 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
13426 }
13427 #[doc = "QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode"]
13428 pub const fn qspilpen(&self) -> super::vals::C1Ahb3lpenrMdmalpen {
13429 let val = (self.0 >> 14usize) & 0x01;
13430 super::vals::C1Ahb3lpenrMdmalpen(val as u8)
13431 }
13432 #[doc = "QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode"]
13433 pub fn set_qspilpen(&mut self, val: super::vals::C1Ahb3lpenrMdmalpen) {
13434 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
13435 }
13436 #[doc = "SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode"]
13437 pub const fn sdmmc1lpen(&self) -> super::vals::C1Ahb3lpenrMdmalpen {
13438 let val = (self.0 >> 16usize) & 0x01;
13439 super::vals::C1Ahb3lpenrMdmalpen(val as u8)
13440 }
13441 #[doc = "SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode"]
13442 pub fn set_sdmmc1lpen(&mut self, val: super::vals::C1Ahb3lpenrMdmalpen) {
13443 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
13444 }
13445 #[doc = "D1DTCM1 Block Clock Enable During CSleep mode"]
13446 pub const fn d1dtcm1lpen(&self) -> super::vals::C1Ahb3lpenrMdmalpen {
13447 let val = (self.0 >> 28usize) & 0x01;
13448 super::vals::C1Ahb3lpenrMdmalpen(val as u8)
13449 }
13450 #[doc = "D1DTCM1 Block Clock Enable During CSleep mode"]
13451 pub fn set_d1dtcm1lpen(&mut self, val: super::vals::C1Ahb3lpenrMdmalpen) {
13452 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
13453 }
13454 #[doc = "D1 DTCM2 Block Clock Enable During CSleep mode"]
13455 pub const fn dtcm2lpen(&self) -> super::vals::C1Ahb3lpenrMdmalpen {
13456 let val = (self.0 >> 29usize) & 0x01;
13457 super::vals::C1Ahb3lpenrMdmalpen(val as u8)
13458 }
13459 #[doc = "D1 DTCM2 Block Clock Enable During CSleep mode"]
13460 pub fn set_dtcm2lpen(&mut self, val: super::vals::C1Ahb3lpenrMdmalpen) {
13461 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
13462 }
13463 #[doc = "D1ITCM Block Clock Enable During CSleep mode"]
13464 pub const fn itcmlpen(&self) -> super::vals::C1Ahb3lpenrMdmalpen {
13465 let val = (self.0 >> 30usize) & 0x01;
13466 super::vals::C1Ahb3lpenrMdmalpen(val as u8)
13467 }
13468 #[doc = "D1ITCM Block Clock Enable During CSleep mode"]
13469 pub fn set_itcmlpen(&mut self, val: super::vals::C1Ahb3lpenrMdmalpen) {
13470 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
13471 }
13472 #[doc = "AXISRAM Block Clock Enable During CSleep mode"]
13473 pub const fn axisramlpen(&self) -> super::vals::C1Ahb3lpenrMdmalpen {
13474 let val = (self.0 >> 31usize) & 0x01;
13475 super::vals::C1Ahb3lpenrMdmalpen(val as u8)
13476 }
13477 #[doc = "AXISRAM Block Clock Enable During CSleep mode"]
13478 pub fn set_axisramlpen(&mut self, val: super::vals::C1Ahb3lpenrMdmalpen) {
13479 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
13480 }
13481 }
13482 impl Default for C1Ahb3lpenr {
13483 fn default() -> C1Ahb3lpenr {
13484 C1Ahb3lpenr(0)
13485 }
13486 }
13487 #[doc = "RCC AHB4 Peripheral Reset Register"]
13488 #[repr(transparent)]
13489 #[derive(Copy, Clone, Eq, PartialEq)]
13490 pub struct Ahb4rstr(pub u32);
13491 impl Ahb4rstr {
13492 #[doc = "GPIO block reset"]
13493 pub const fn gpioarst(&self) -> super::vals::Gpioarst {
13494>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
13495 let val = (self.0 >> 0usize) & 0x01;
13496 super::vals::Gpioarst(val as u8)
13497 }
13498<<<<<<< HEAD
9427 #[doc = "Serial Peripheral Enable"] 13499 #[doc = "Serial Peripheral Enable"]
9428 pub fn set_spe(&mut self, val: bool) { 13500 pub fn set_spe(&mut self, val: bool) {
9429 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 13501 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
@@ -9564,45 +13636,227 @@ pub mod spi_v3 {
9564 impl Sr { 13636 impl Sr {
9565 #[doc = "Rx-Packet available"] 13637 #[doc = "Rx-Packet available"]
9566 pub const fn rxp(&self) -> bool { 13638 pub const fn rxp(&self) -> bool {
13639=======
13640 #[doc = "GPIO block reset"]
13641 pub fn set_gpioarst(&mut self, val: super::vals::Gpioarst) {
13642 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
13643 }
13644 #[doc = "GPIO block reset"]
13645 pub const fn gpiobrst(&self) -> super::vals::Gpioarst {
13646 let val = (self.0 >> 1usize) & 0x01;
13647 super::vals::Gpioarst(val as u8)
13648 }
13649 #[doc = "GPIO block reset"]
13650 pub fn set_gpiobrst(&mut self, val: super::vals::Gpioarst) {
13651 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
13652 }
13653 #[doc = "GPIO block reset"]
13654 pub const fn gpiocrst(&self) -> super::vals::Gpioarst {
13655 let val = (self.0 >> 2usize) & 0x01;
13656 super::vals::Gpioarst(val as u8)
13657 }
13658 #[doc = "GPIO block reset"]
13659 pub fn set_gpiocrst(&mut self, val: super::vals::Gpioarst) {
13660 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
13661 }
13662 #[doc = "GPIO block reset"]
13663 pub const fn gpiodrst(&self) -> super::vals::Gpioarst {
13664 let val = (self.0 >> 3usize) & 0x01;
13665 super::vals::Gpioarst(val as u8)
13666 }
13667 #[doc = "GPIO block reset"]
13668 pub fn set_gpiodrst(&mut self, val: super::vals::Gpioarst) {
13669 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
13670 }
13671 #[doc = "GPIO block reset"]
13672 pub const fn gpioerst(&self) -> super::vals::Gpioarst {
13673 let val = (self.0 >> 4usize) & 0x01;
13674 super::vals::Gpioarst(val as u8)
13675 }
13676 #[doc = "GPIO block reset"]
13677 pub fn set_gpioerst(&mut self, val: super::vals::Gpioarst) {
13678 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
13679 }
13680 #[doc = "GPIO block reset"]
13681 pub const fn gpiofrst(&self) -> super::vals::Gpioarst {
13682 let val = (self.0 >> 5usize) & 0x01;
13683 super::vals::Gpioarst(val as u8)
13684 }
13685 #[doc = "GPIO block reset"]
13686 pub fn set_gpiofrst(&mut self, val: super::vals::Gpioarst) {
13687 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
13688 }
13689 #[doc = "GPIO block reset"]
13690 pub const fn gpiogrst(&self) -> super::vals::Gpioarst {
13691 let val = (self.0 >> 6usize) & 0x01;
13692 super::vals::Gpioarst(val as u8)
13693 }
13694 #[doc = "GPIO block reset"]
13695 pub fn set_gpiogrst(&mut self, val: super::vals::Gpioarst) {
13696 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
13697 }
13698 #[doc = "GPIO block reset"]
13699 pub const fn gpiohrst(&self) -> super::vals::Gpioarst {
13700 let val = (self.0 >> 7usize) & 0x01;
13701 super::vals::Gpioarst(val as u8)
13702 }
13703 #[doc = "GPIO block reset"]
13704 pub fn set_gpiohrst(&mut self, val: super::vals::Gpioarst) {
13705 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
13706 }
13707 #[doc = "GPIO block reset"]
13708 pub const fn gpioirst(&self) -> super::vals::Gpioarst {
13709 let val = (self.0 >> 8usize) & 0x01;
13710 super::vals::Gpioarst(val as u8)
13711 }
13712 #[doc = "GPIO block reset"]
13713 pub fn set_gpioirst(&mut self, val: super::vals::Gpioarst) {
13714 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
13715 }
13716 #[doc = "GPIO block reset"]
13717 pub const fn gpiojrst(&self) -> super::vals::Gpioarst {
13718 let val = (self.0 >> 9usize) & 0x01;
13719 super::vals::Gpioarst(val as u8)
13720 }
13721 #[doc = "GPIO block reset"]
13722 pub fn set_gpiojrst(&mut self, val: super::vals::Gpioarst) {
13723 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
13724 }
13725 #[doc = "GPIO block reset"]
13726 pub const fn gpiokrst(&self) -> super::vals::Gpioarst {
13727 let val = (self.0 >> 10usize) & 0x01;
13728 super::vals::Gpioarst(val as u8)
13729 }
13730 #[doc = "GPIO block reset"]
13731 pub fn set_gpiokrst(&mut self, val: super::vals::Gpioarst) {
13732 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
13733 }
13734 #[doc = "CRC block reset"]
13735 pub const fn crcrst(&self) -> super::vals::Gpioarst {
13736 let val = (self.0 >> 19usize) & 0x01;
13737 super::vals::Gpioarst(val as u8)
13738 }
13739 #[doc = "CRC block reset"]
13740 pub fn set_crcrst(&mut self, val: super::vals::Gpioarst) {
13741 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
13742 }
13743 #[doc = "BDMA block reset"]
13744 pub const fn bdmarst(&self) -> super::vals::Gpioarst {
13745 let val = (self.0 >> 21usize) & 0x01;
13746 super::vals::Gpioarst(val as u8)
13747 }
13748 #[doc = "BDMA block reset"]
13749 pub fn set_bdmarst(&mut self, val: super::vals::Gpioarst) {
13750 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
13751 }
13752 #[doc = "ADC3 block reset"]
13753 pub const fn adc3rst(&self) -> super::vals::Gpioarst {
13754 let val = (self.0 >> 24usize) & 0x01;
13755 super::vals::Gpioarst(val as u8)
13756 }
13757 #[doc = "ADC3 block reset"]
13758 pub fn set_adc3rst(&mut self, val: super::vals::Gpioarst) {
13759 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
13760 }
13761 #[doc = "HSEM block reset"]
13762 pub const fn hsemrst(&self) -> super::vals::Gpioarst {
13763 let val = (self.0 >> 25usize) & 0x01;
13764 super::vals::Gpioarst(val as u8)
13765 }
13766 #[doc = "HSEM block reset"]
13767 pub fn set_hsemrst(&mut self, val: super::vals::Gpioarst) {
13768 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.0 as u32) & 0x01) << 25usize);
13769 }
13770 }
13771 impl Default for Ahb4rstr {
13772 fn default() -> Ahb4rstr {
13773 Ahb4rstr(0)
13774 }
13775 }
13776 #[doc = "RCC Clock Source Interrupt Enable Register"]
13777 #[repr(transparent)]
13778 #[derive(Copy, Clone, Eq, PartialEq)]
13779 pub struct Cier(pub u32);
13780 impl Cier {
13781 #[doc = "LSI ready Interrupt Enable"]
13782 pub const fn lsirdyie(&self) -> super::vals::Lsirdyie {
13783>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9567 let val = (self.0 >> 0usize) & 0x01; 13784 let val = (self.0 >> 0usize) & 0x01;
9568 val != 0 13785 super::vals::Lsirdyie(val as u8)
9569 } 13786 }
13787<<<<<<< HEAD
9570 #[doc = "Rx-Packet available"] 13788 #[doc = "Rx-Packet available"]
9571 pub fn set_rxp(&mut self, val: bool) { 13789 pub fn set_rxp(&mut self, val: bool) {
9572 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 13790 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
9573 } 13791 }
9574 #[doc = "Tx-Packet space available"] 13792 #[doc = "Tx-Packet space available"]
9575 pub const fn txp(&self) -> bool { 13793 pub const fn txp(&self) -> bool {
13794=======
13795 #[doc = "LSI ready Interrupt Enable"]
13796 pub fn set_lsirdyie(&mut self, val: super::vals::Lsirdyie) {
13797 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
13798 }
13799 #[doc = "LSE ready Interrupt Enable"]
13800 pub const fn lserdyie(&self) -> super::vals::Lsirdyie {
13801>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9576 let val = (self.0 >> 1usize) & 0x01; 13802 let val = (self.0 >> 1usize) & 0x01;
9577 val != 0 13803 super::vals::Lsirdyie(val as u8)
9578 } 13804 }
13805<<<<<<< HEAD
9579 #[doc = "Tx-Packet space available"] 13806 #[doc = "Tx-Packet space available"]
9580 pub fn set_txp(&mut self, val: bool) { 13807 pub fn set_txp(&mut self, val: bool) {
9581 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); 13808 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
9582 } 13809 }
9583 #[doc = "Duplex Packet"] 13810 #[doc = "Duplex Packet"]
9584 pub const fn dxp(&self) -> bool { 13811 pub const fn dxp(&self) -> bool {
13812=======
13813 #[doc = "LSE ready Interrupt Enable"]
13814 pub fn set_lserdyie(&mut self, val: super::vals::Lsirdyie) {
13815 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
13816 }
13817 #[doc = "HSI ready Interrupt Enable"]
13818 pub const fn hsirdyie(&self) -> super::vals::Lsirdyie {
13819>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9585 let val = (self.0 >> 2usize) & 0x01; 13820 let val = (self.0 >> 2usize) & 0x01;
9586 val != 0 13821 super::vals::Lsirdyie(val as u8)
9587 } 13822 }
13823<<<<<<< HEAD
9588 #[doc = "Duplex Packet"] 13824 #[doc = "Duplex Packet"]
9589 pub fn set_dxp(&mut self, val: bool) { 13825 pub fn set_dxp(&mut self, val: bool) {
9590 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); 13826 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
9591 } 13827 }
9592 #[doc = "End Of Transfer"] 13828 #[doc = "End Of Transfer"]
9593 pub const fn eot(&self) -> bool { 13829 pub const fn eot(&self) -> bool {
13830=======
13831 #[doc = "HSI ready Interrupt Enable"]
13832 pub fn set_hsirdyie(&mut self, val: super::vals::Lsirdyie) {
13833 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
13834 }
13835 #[doc = "HSE ready Interrupt Enable"]
13836 pub const fn hserdyie(&self) -> super::vals::Lsirdyie {
13837>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9594 let val = (self.0 >> 3usize) & 0x01; 13838 let val = (self.0 >> 3usize) & 0x01;
9595 val != 0 13839 super::vals::Lsirdyie(val as u8)
9596 } 13840 }
13841<<<<<<< HEAD
9597 #[doc = "End Of Transfer"] 13842 #[doc = "End Of Transfer"]
9598 pub fn set_eot(&mut self, val: bool) { 13843 pub fn set_eot(&mut self, val: bool) {
9599 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); 13844 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
9600 } 13845 }
9601 #[doc = "Transmission Transfer Filled"] 13846 #[doc = "Transmission Transfer Filled"]
9602 pub const fn txtf(&self) -> bool { 13847 pub const fn txtf(&self) -> bool {
13848=======
13849 #[doc = "HSE ready Interrupt Enable"]
13850 pub fn set_hserdyie(&mut self, val: super::vals::Lsirdyie) {
13851 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
13852 }
13853 #[doc = "CSI ready Interrupt Enable"]
13854 pub const fn csirdyie(&self) -> super::vals::Lsirdyie {
13855>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9603 let val = (self.0 >> 4usize) & 0x01; 13856 let val = (self.0 >> 4usize) & 0x01;
9604 val != 0 13857 super::vals::Lsirdyie(val as u8)
9605 } 13858 }
13859<<<<<<< HEAD
9606 #[doc = "Transmission Transfer Filled"] 13860 #[doc = "Transmission Transfer Filled"]
9607 pub fn set_txtf(&mut self, val: bool) { 13861 pub fn set_txtf(&mut self, val: bool) {
9608 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); 13862 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
@@ -9645,9 +13899,40 @@ pub mod spi_v3 {
9645 } 13899 }
9646 #[doc = "Mode Fault"] 13900 #[doc = "Mode Fault"]
9647 pub const fn modf(&self) -> bool { 13901 pub const fn modf(&self) -> bool {
13902=======
13903 #[doc = "CSI ready Interrupt Enable"]
13904 pub fn set_csirdyie(&mut self, val: super::vals::Lsirdyie) {
13905 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
13906 }
13907 #[doc = "RC48 ready Interrupt Enable"]
13908 pub const fn hsi48rdyie(&self) -> super::vals::Lsirdyie {
13909 let val = (self.0 >> 5usize) & 0x01;
13910 super::vals::Lsirdyie(val as u8)
13911 }
13912 #[doc = "RC48 ready Interrupt Enable"]
13913 pub fn set_hsi48rdyie(&mut self, val: super::vals::Lsirdyie) {
13914 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
13915 }
13916 #[doc = "PLL1 ready Interrupt Enable"]
13917 pub fn pllrdyie(&self, n: usize) -> super::vals::Lsirdyie {
13918 assert!(n < 3usize);
13919 let offs = 6usize + n * 1usize;
13920 let val = (self.0 >> offs) & 0x01;
13921 super::vals::Lsirdyie(val as u8)
13922 }
13923 #[doc = "PLL1 ready Interrupt Enable"]
13924 pub fn set_pllrdyie(&mut self, n: usize, val: super::vals::Lsirdyie) {
13925 assert!(n < 3usize);
13926 let offs = 6usize + n * 1usize;
13927 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
13928 }
13929 #[doc = "LSE clock security system Interrupt Enable"]
13930 pub const fn lsecssie(&self) -> super::vals::Lsirdyie {
13931>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9648 let val = (self.0 >> 9usize) & 0x01; 13932 let val = (self.0 >> 9usize) & 0x01;
9649 val != 0 13933 super::vals::Lsirdyie(val as u8)
9650 } 13934 }
13935<<<<<<< HEAD
9651 #[doc = "Mode Fault"] 13936 #[doc = "Mode Fault"]
9652 pub fn set_modf(&mut self, val: bool) { 13937 pub fn set_modf(&mut self, val: bool) {
9653 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); 13938 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
@@ -9728,54 +14013,155 @@ pub mod spi_v3 {
9728 } 14013 }
9729 #[doc = "Transmission Transfer Filled flag clear"] 14014 #[doc = "Transmission Transfer Filled flag clear"]
9730 pub const fn txtfc(&self) -> bool { 14015 pub const fn txtfc(&self) -> bool {
14016=======
14017 #[doc = "LSE clock security system Interrupt Enable"]
14018 pub fn set_lsecssie(&mut self, val: super::vals::Lsirdyie) {
14019 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
14020 }
14021 }
14022 impl Default for Cier {
14023 fn default() -> Cier {
14024 Cier(0)
14025 }
14026 }
14027 #[doc = "RCC AHB4 Clock Register"]
14028 #[repr(transparent)]
14029 #[derive(Copy, Clone, Eq, PartialEq)]
14030 pub struct Ahb4enr(pub u32);
14031 impl Ahb4enr {
14032 #[doc = "0GPIO peripheral clock enable"]
14033 pub const fn gpioaen(&self) -> super::vals::Ahb4enrGpioaen {
14034 let val = (self.0 >> 0usize) & 0x01;
14035 super::vals::Ahb4enrGpioaen(val as u8)
14036 }
14037 #[doc = "0GPIO peripheral clock enable"]
14038 pub fn set_gpioaen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14039 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
14040 }
14041 #[doc = "0GPIO peripheral clock enable"]
14042 pub const fn gpioben(&self) -> super::vals::Ahb4enrGpioaen {
14043 let val = (self.0 >> 1usize) & 0x01;
14044 super::vals::Ahb4enrGpioaen(val as u8)
14045 }
14046 #[doc = "0GPIO peripheral clock enable"]
14047 pub fn set_gpioben(&mut self, val: super::vals::Ahb4enrGpioaen) {
14048 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
14049 }
14050 #[doc = "0GPIO peripheral clock enable"]
14051 pub const fn gpiocen(&self) -> super::vals::Ahb4enrGpioaen {
14052 let val = (self.0 >> 2usize) & 0x01;
14053 super::vals::Ahb4enrGpioaen(val as u8)
14054 }
14055 #[doc = "0GPIO peripheral clock enable"]
14056 pub fn set_gpiocen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14057 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
14058 }
14059 #[doc = "0GPIO peripheral clock enable"]
14060 pub const fn gpioden(&self) -> super::vals::Ahb4enrGpioaen {
14061 let val = (self.0 >> 3usize) & 0x01;
14062 super::vals::Ahb4enrGpioaen(val as u8)
14063 }
14064 #[doc = "0GPIO peripheral clock enable"]
14065 pub fn set_gpioden(&mut self, val: super::vals::Ahb4enrGpioaen) {
14066 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
14067 }
14068 #[doc = "0GPIO peripheral clock enable"]
14069 pub const fn gpioeen(&self) -> super::vals::Ahb4enrGpioaen {
14070>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9731 let val = (self.0 >> 4usize) & 0x01; 14071 let val = (self.0 >> 4usize) & 0x01;
9732 val != 0 14072 super::vals::Ahb4enrGpioaen(val as u8)
9733 } 14073 }
14074<<<<<<< HEAD
9734 #[doc = "Transmission Transfer Filled flag clear"] 14075 #[doc = "Transmission Transfer Filled flag clear"]
9735 pub fn set_txtfc(&mut self, val: bool) { 14076 pub fn set_txtfc(&mut self, val: bool) {
9736 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); 14077 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
9737 } 14078 }
9738 #[doc = "Underrun flag clear"] 14079 #[doc = "Underrun flag clear"]
9739 pub const fn udrc(&self) -> bool { 14080 pub const fn udrc(&self) -> bool {
14081=======
14082 #[doc = "0GPIO peripheral clock enable"]
14083 pub fn set_gpioeen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14084 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
14085 }
14086 #[doc = "0GPIO peripheral clock enable"]
14087 pub const fn gpiofen(&self) -> super::vals::Ahb4enrGpioaen {
14088>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9740 let val = (self.0 >> 5usize) & 0x01; 14089 let val = (self.0 >> 5usize) & 0x01;
9741 val != 0 14090 super::vals::Ahb4enrGpioaen(val as u8)
9742 } 14091 }
14092<<<<<<< HEAD
9743 #[doc = "Underrun flag clear"] 14093 #[doc = "Underrun flag clear"]
9744 pub fn set_udrc(&mut self, val: bool) { 14094 pub fn set_udrc(&mut self, val: bool) {
9745 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); 14095 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
9746 } 14096 }
9747 #[doc = "Overrun flag clear"] 14097 #[doc = "Overrun flag clear"]
9748 pub const fn ovrc(&self) -> bool { 14098 pub const fn ovrc(&self) -> bool {
14099=======
14100 #[doc = "0GPIO peripheral clock enable"]
14101 pub fn set_gpiofen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14102 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
14103 }
14104 #[doc = "0GPIO peripheral clock enable"]
14105 pub const fn gpiogen(&self) -> super::vals::Ahb4enrGpioaen {
14106>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9749 let val = (self.0 >> 6usize) & 0x01; 14107 let val = (self.0 >> 6usize) & 0x01;
9750 val != 0 14108 super::vals::Ahb4enrGpioaen(val as u8)
9751 } 14109 }
14110<<<<<<< HEAD
9752 #[doc = "Overrun flag clear"] 14111 #[doc = "Overrun flag clear"]
9753 pub fn set_ovrc(&mut self, val: bool) { 14112 pub fn set_ovrc(&mut self, val: bool) {
9754 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); 14113 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
9755 } 14114 }
9756 #[doc = "CRC Error flag clear"] 14115 #[doc = "CRC Error flag clear"]
9757 pub const fn crcec(&self) -> bool { 14116 pub const fn crcec(&self) -> bool {
14117=======
14118 #[doc = "0GPIO peripheral clock enable"]
14119 pub fn set_gpiogen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14120 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
14121 }
14122 #[doc = "0GPIO peripheral clock enable"]
14123 pub const fn gpiohen(&self) -> super::vals::Ahb4enrGpioaen {
14124>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9758 let val = (self.0 >> 7usize) & 0x01; 14125 let val = (self.0 >> 7usize) & 0x01;
9759 val != 0 14126 super::vals::Ahb4enrGpioaen(val as u8)
9760 } 14127 }
14128<<<<<<< HEAD
9761 #[doc = "CRC Error flag clear"] 14129 #[doc = "CRC Error flag clear"]
9762 pub fn set_crcec(&mut self, val: bool) { 14130 pub fn set_crcec(&mut self, val: bool) {
9763 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); 14131 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
9764 } 14132 }
9765 #[doc = "TI frame format error flag clear"] 14133 #[doc = "TI frame format error flag clear"]
9766 pub const fn tifrec(&self) -> bool { 14134 pub const fn tifrec(&self) -> bool {
14135=======
14136 #[doc = "0GPIO peripheral clock enable"]
14137 pub fn set_gpiohen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14138 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
14139 }
14140 #[doc = "0GPIO peripheral clock enable"]
14141 pub const fn gpioien(&self) -> super::vals::Ahb4enrGpioaen {
14142>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9767 let val = (self.0 >> 8usize) & 0x01; 14143 let val = (self.0 >> 8usize) & 0x01;
9768 val != 0 14144 super::vals::Ahb4enrGpioaen(val as u8)
9769 } 14145 }
14146<<<<<<< HEAD
9770 #[doc = "TI frame format error flag clear"] 14147 #[doc = "TI frame format error flag clear"]
9771 pub fn set_tifrec(&mut self, val: bool) { 14148 pub fn set_tifrec(&mut self, val: bool) {
9772 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); 14149 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
9773 } 14150 }
9774 #[doc = "Mode Fault flag clear"] 14151 #[doc = "Mode Fault flag clear"]
9775 pub const fn modfc(&self) -> bool { 14152 pub const fn modfc(&self) -> bool {
14153=======
14154 #[doc = "0GPIO peripheral clock enable"]
14155 pub fn set_gpioien(&mut self, val: super::vals::Ahb4enrGpioaen) {
14156 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
14157 }
14158 #[doc = "0GPIO peripheral clock enable"]
14159 pub const fn gpiojen(&self) -> super::vals::Ahb4enrGpioaen {
14160>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
9776 let val = (self.0 >> 9usize) & 0x01; 14161 let val = (self.0 >> 9usize) & 0x01;
9777 val != 0 14162 super::vals::Ahb4enrGpioaen(val as u8)
9778 } 14163 }
14164<<<<<<< HEAD
9779 #[doc = "Mode Fault flag clear"] 14165 #[doc = "Mode Fault flag clear"]
9780 pub fn set_modfc(&mut self, val: bool) { 14166 pub fn set_modfc(&mut self, val: bool) {
9781 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); 14167 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
@@ -10193,9 +14579,361 @@ pub mod rcc_l0 {
10193 } 14579 }
10194 #[doc = "HSI16DIVEN"] 14580 #[doc = "HSI16DIVEN"]
10195 pub const fn hsi16diven(&self) -> super::vals::Hsidiven { 14581 pub const fn hsi16diven(&self) -> super::vals::Hsidiven {
14582=======
14583 #[doc = "0GPIO peripheral clock enable"]
14584 pub fn set_gpiojen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14585 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
14586 }
14587 #[doc = "0GPIO peripheral clock enable"]
14588 pub const fn gpioken(&self) -> super::vals::Ahb4enrGpioaen {
14589 let val = (self.0 >> 10usize) & 0x01;
14590 super::vals::Ahb4enrGpioaen(val as u8)
14591 }
14592 #[doc = "0GPIO peripheral clock enable"]
14593 pub fn set_gpioken(&mut self, val: super::vals::Ahb4enrGpioaen) {
14594 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
14595 }
14596 #[doc = "CRC peripheral clock enable"]
14597 pub const fn crcen(&self) -> super::vals::Ahb4enrGpioaen {
14598 let val = (self.0 >> 19usize) & 0x01;
14599 super::vals::Ahb4enrGpioaen(val as u8)
14600 }
14601 #[doc = "CRC peripheral clock enable"]
14602 pub fn set_crcen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14603 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
14604 }
14605 #[doc = "BDMA and DMAMUX2 Clock Enable"]
14606 pub const fn bdmaen(&self) -> super::vals::Ahb4enrGpioaen {
14607 let val = (self.0 >> 21usize) & 0x01;
14608 super::vals::Ahb4enrGpioaen(val as u8)
14609 }
14610 #[doc = "BDMA and DMAMUX2 Clock Enable"]
14611 pub fn set_bdmaen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14612 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
14613 }
14614 #[doc = "ADC3 Peripheral Clocks Enable"]
14615 pub const fn adc3en(&self) -> super::vals::Ahb4enrGpioaen {
14616 let val = (self.0 >> 24usize) & 0x01;
14617 super::vals::Ahb4enrGpioaen(val as u8)
14618 }
14619 #[doc = "ADC3 Peripheral Clocks Enable"]
14620 pub fn set_adc3en(&mut self, val: super::vals::Ahb4enrGpioaen) {
14621 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
14622 }
14623 #[doc = "HSEM peripheral clock enable"]
14624 pub const fn hsemen(&self) -> super::vals::Ahb4enrGpioaen {
14625 let val = (self.0 >> 25usize) & 0x01;
14626 super::vals::Ahb4enrGpioaen(val as u8)
14627 }
14628 #[doc = "HSEM peripheral clock enable"]
14629 pub fn set_hsemen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14630 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.0 as u32) & 0x01) << 25usize);
14631 }
14632 #[doc = "Backup RAM Clock Enable"]
14633 pub const fn bkpramen(&self) -> super::vals::Ahb4enrGpioaen {
14634 let val = (self.0 >> 28usize) & 0x01;
14635 super::vals::Ahb4enrGpioaen(val as u8)
14636 }
14637 #[doc = "Backup RAM Clock Enable"]
14638 pub fn set_bkpramen(&mut self, val: super::vals::Ahb4enrGpioaen) {
14639 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
14640 }
14641 }
14642 impl Default for Ahb4enr {
14643 fn default() -> Ahb4enr {
14644 Ahb4enr(0)
14645 }
14646 }
14647 #[doc = "RCC PLL2 Fractional Divider Register"]
14648 #[repr(transparent)]
14649 #[derive(Copy, Clone, Eq, PartialEq)]
14650 pub struct Pll2fracr(pub u32);
14651 impl Pll2fracr {
14652 #[doc = "Fractional part of the multiplication factor for PLL VCO"]
14653 pub const fn fracn2(&self) -> u16 {
14654 let val = (self.0 >> 3usize) & 0x1fff;
14655 val as u16
14656 }
14657 #[doc = "Fractional part of the multiplication factor for PLL VCO"]
14658 pub fn set_fracn2(&mut self, val: u16) {
14659 self.0 = (self.0 & !(0x1fff << 3usize)) | (((val as u32) & 0x1fff) << 3usize);
14660 }
14661 }
14662 impl Default for Pll2fracr {
14663 fn default() -> Pll2fracr {
14664 Pll2fracr(0)
14665 }
14666 }
14667 #[doc = "RCC Clock Configuration Register"]
14668 #[repr(transparent)]
14669 #[derive(Copy, Clone, Eq, PartialEq)]
14670 pub struct Cfgr(pub u32);
14671 impl Cfgr {
14672 #[doc = "System clock switch"]
14673 pub const fn sw(&self) -> super::vals::Sw {
14674 let val = (self.0 >> 0usize) & 0x07;
14675 super::vals::Sw(val as u8)
14676 }
14677 #[doc = "System clock switch"]
14678 pub fn set_sw(&mut self, val: super::vals::Sw) {
14679 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
14680 }
14681 #[doc = "System clock switch status"]
14682 pub const fn sws(&self) -> u8 {
14683 let val = (self.0 >> 3usize) & 0x07;
14684 val as u8
14685 }
14686 #[doc = "System clock switch status"]
14687 pub fn set_sws(&mut self, val: u8) {
14688 self.0 = (self.0 & !(0x07 << 3usize)) | (((val as u32) & 0x07) << 3usize);
14689 }
14690 #[doc = "System clock selection after a wake up from system Stop"]
14691 pub const fn stopwuck(&self) -> super::vals::Stopwuck {
14692 let val = (self.0 >> 6usize) & 0x01;
14693 super::vals::Stopwuck(val as u8)
14694 }
14695 #[doc = "System clock selection after a wake up from system Stop"]
14696 pub fn set_stopwuck(&mut self, val: super::vals::Stopwuck) {
14697 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
14698 }
14699 #[doc = "Kernel clock selection after a wake up from system Stop"]
14700 pub const fn stopkerwuck(&self) -> super::vals::Stopwuck {
14701 let val = (self.0 >> 7usize) & 0x01;
14702 super::vals::Stopwuck(val as u8)
14703 }
14704 #[doc = "Kernel clock selection after a wake up from system Stop"]
14705 pub fn set_stopkerwuck(&mut self, val: super::vals::Stopwuck) {
14706 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
14707 }
14708 #[doc = "HSE division factor for RTC clock"]
14709 pub const fn rtcpre(&self) -> u8 {
14710 let val = (self.0 >> 8usize) & 0x3f;
14711 val as u8
14712 }
14713 #[doc = "HSE division factor for RTC clock"]
14714 pub fn set_rtcpre(&mut self, val: u8) {
14715 self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize);
14716 }
14717 #[doc = "High Resolution Timer clock prescaler selection"]
14718 pub const fn hrtimsel(&self) -> super::vals::Hrtimsel {
14719 let val = (self.0 >> 14usize) & 0x01;
14720 super::vals::Hrtimsel(val as u8)
14721 }
14722 #[doc = "High Resolution Timer clock prescaler selection"]
14723 pub fn set_hrtimsel(&mut self, val: super::vals::Hrtimsel) {
14724 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
14725 }
14726 #[doc = "Timers clocks prescaler selection"]
14727 pub const fn timpre(&self) -> super::vals::Timpre {
14728 let val = (self.0 >> 15usize) & 0x01;
14729 super::vals::Timpre(val as u8)
14730 }
14731 #[doc = "Timers clocks prescaler selection"]
14732 pub fn set_timpre(&mut self, val: super::vals::Timpre) {
14733 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
14734 }
14735 #[doc = "MCO1 prescaler"]
14736 pub const fn mco1pre(&self) -> u8 {
14737 let val = (self.0 >> 18usize) & 0x0f;
14738 val as u8
14739 }
14740 #[doc = "MCO1 prescaler"]
14741 pub fn set_mco1pre(&mut self, val: u8) {
14742 self.0 = (self.0 & !(0x0f << 18usize)) | (((val as u32) & 0x0f) << 18usize);
14743 }
14744 #[doc = "Micro-controller clock output 1"]
14745 pub const fn mco1(&self) -> super::vals::Mco1 {
14746 let val = (self.0 >> 22usize) & 0x07;
14747 super::vals::Mco1(val as u8)
14748 }
14749 #[doc = "Micro-controller clock output 1"]
14750 pub fn set_mco1(&mut self, val: super::vals::Mco1) {
14751 self.0 = (self.0 & !(0x07 << 22usize)) | (((val.0 as u32) & 0x07) << 22usize);
14752 }
14753 #[doc = "MCO2 prescaler"]
14754 pub const fn mco2pre(&self) -> u8 {
14755 let val = (self.0 >> 25usize) & 0x0f;
14756 val as u8
14757 }
14758 #[doc = "MCO2 prescaler"]
14759 pub fn set_mco2pre(&mut self, val: u8) {
14760 self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize);
14761 }
14762 #[doc = "Micro-controller clock output 2"]
14763 pub const fn mco2(&self) -> super::vals::Mco2 {
14764 let val = (self.0 >> 29usize) & 0x07;
14765 super::vals::Mco2(val as u8)
14766 }
14767 #[doc = "Micro-controller clock output 2"]
14768 pub fn set_mco2(&mut self, val: super::vals::Mco2) {
14769 self.0 = (self.0 & !(0x07 << 29usize)) | (((val.0 as u32) & 0x07) << 29usize);
14770 }
14771 }
14772 impl Default for Cfgr {
14773 fn default() -> Cfgr {
14774 Cfgr(0)
14775 }
14776 }
14777 #[doc = "RCC APB1 High Sleep Clock Register"]
14778 #[repr(transparent)]
14779 #[derive(Copy, Clone, Eq, PartialEq)]
14780 pub struct C1Apb1hlpenr(pub u32);
14781 impl C1Apb1hlpenr {
14782 #[doc = "Clock Recovery System peripheral clock enable during CSleep mode"]
14783 pub const fn crslpen(&self) -> super::vals::C1Apb1hlpenrCrslpen {
14784 let val = (self.0 >> 1usize) & 0x01;
14785 super::vals::C1Apb1hlpenrCrslpen(val as u8)
14786 }
14787 #[doc = "Clock Recovery System peripheral clock enable during CSleep mode"]
14788 pub fn set_crslpen(&mut self, val: super::vals::C1Apb1hlpenrCrslpen) {
14789 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
14790 }
14791 #[doc = "SWPMI Peripheral Clocks Enable During CSleep Mode"]
14792 pub const fn swplpen(&self) -> super::vals::C1Apb1hlpenrCrslpen {
14793 let val = (self.0 >> 2usize) & 0x01;
14794 super::vals::C1Apb1hlpenrCrslpen(val as u8)
14795 }
14796 #[doc = "SWPMI Peripheral Clocks Enable During CSleep Mode"]
14797 pub fn set_swplpen(&mut self, val: super::vals::C1Apb1hlpenrCrslpen) {
14798 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
14799 }
14800 #[doc = "OPAMP peripheral clock enable during CSleep mode"]
14801 pub const fn opamplpen(&self) -> super::vals::C1Apb1hlpenrCrslpen {
14802 let val = (self.0 >> 4usize) & 0x01;
14803 super::vals::C1Apb1hlpenrCrslpen(val as u8)
14804 }
14805 #[doc = "OPAMP peripheral clock enable during CSleep mode"]
14806 pub fn set_opamplpen(&mut self, val: super::vals::C1Apb1hlpenrCrslpen) {
14807 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
14808 }
14809 #[doc = "MDIOS peripheral clock enable during CSleep mode"]
14810 pub const fn mdioslpen(&self) -> super::vals::C1Apb1hlpenrCrslpen {
14811 let val = (self.0 >> 5usize) & 0x01;
14812 super::vals::C1Apb1hlpenrCrslpen(val as u8)
14813 }
14814 #[doc = "MDIOS peripheral clock enable during CSleep mode"]
14815 pub fn set_mdioslpen(&mut self, val: super::vals::C1Apb1hlpenrCrslpen) {
14816 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
14817 }
14818 #[doc = "FDCAN Peripheral Clocks Enable During CSleep Mode"]
14819 pub const fn fdcanlpen(&self) -> super::vals::C1Apb1hlpenrCrslpen {
14820 let val = (self.0 >> 8usize) & 0x01;
14821 super::vals::C1Apb1hlpenrCrslpen(val as u8)
14822 }
14823 #[doc = "FDCAN Peripheral Clocks Enable During CSleep Mode"]
14824 pub fn set_fdcanlpen(&mut self, val: super::vals::C1Apb1hlpenrCrslpen) {
14825 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
14826 }
14827 }
14828 impl Default for C1Apb1hlpenr {
14829 fn default() -> C1Apb1hlpenr {
14830 C1Apb1hlpenr(0)
14831 }
14832 }
14833 #[doc = "RCC AHB1 Peripheral Reset Register"]
14834 #[repr(transparent)]
14835 #[derive(Copy, Clone, Eq, PartialEq)]
14836 pub struct Ahb1rstr(pub u32);
14837 impl Ahb1rstr {
14838 #[doc = "DMA1 block reset"]
14839 pub const fn dma1rst(&self) -> super::vals::Dma1rst {
14840 let val = (self.0 >> 0usize) & 0x01;
14841 super::vals::Dma1rst(val as u8)
14842 }
14843 #[doc = "DMA1 block reset"]
14844 pub fn set_dma1rst(&mut self, val: super::vals::Dma1rst) {
14845 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
14846 }
14847 #[doc = "DMA2 block reset"]
14848 pub const fn dma2rst(&self) -> super::vals::Dma1rst {
14849 let val = (self.0 >> 1usize) & 0x01;
14850 super::vals::Dma1rst(val as u8)
14851 }
14852 #[doc = "DMA2 block reset"]
14853 pub fn set_dma2rst(&mut self, val: super::vals::Dma1rst) {
14854 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
14855 }
14856 #[doc = "ADC1&2 block reset"]
14857 pub const fn adc12rst(&self) -> super::vals::Dma1rst {
14858 let val = (self.0 >> 5usize) & 0x01;
14859 super::vals::Dma1rst(val as u8)
14860 }
14861 #[doc = "ADC1&2 block reset"]
14862 pub fn set_adc12rst(&mut self, val: super::vals::Dma1rst) {
14863 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
14864 }
14865 #[doc = "ETH1MAC block reset"]
14866 pub const fn eth1macrst(&self) -> super::vals::Dma1rst {
14867 let val = (self.0 >> 15usize) & 0x01;
14868 super::vals::Dma1rst(val as u8)
14869 }
14870 #[doc = "ETH1MAC block reset"]
14871 pub fn set_eth1macrst(&mut self, val: super::vals::Dma1rst) {
14872 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
14873 }
14874 #[doc = "USB1OTG block reset"]
14875 pub const fn usb1otgrst(&self) -> super::vals::Dma1rst {
14876 let val = (self.0 >> 25usize) & 0x01;
14877 super::vals::Dma1rst(val as u8)
14878 }
14879 #[doc = "USB1OTG block reset"]
14880 pub fn set_usb1otgrst(&mut self, val: super::vals::Dma1rst) {
14881 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.0 as u32) & 0x01) << 25usize);
14882 }
14883 #[doc = "USB2OTG block reset"]
14884 pub const fn usb2otgrst(&self) -> super::vals::Dma1rst {
14885 let val = (self.0 >> 27usize) & 0x01;
14886 super::vals::Dma1rst(val as u8)
14887 }
14888 #[doc = "USB2OTG block reset"]
14889 pub fn set_usb2otgrst(&mut self, val: super::vals::Dma1rst) {
14890 self.0 = (self.0 & !(0x01 << 27usize)) | (((val.0 as u32) & 0x01) << 27usize);
14891 }
14892 }
14893 impl Default for Ahb1rstr {
14894 fn default() -> Ahb1rstr {
14895 Ahb1rstr(0)
14896 }
14897 }
14898 #[doc = "RCC Clock Source Interrupt Flag Register"]
14899 #[repr(transparent)]
14900 #[derive(Copy, Clone, Eq, PartialEq)]
14901 pub struct Cifr(pub u32);
14902 impl Cifr {
14903 #[doc = "LSI ready Interrupt Flag"]
14904 pub const fn lsirdyf(&self) -> bool {
14905 let val = (self.0 >> 0usize) & 0x01;
14906 val != 0
14907 }
14908 #[doc = "LSI ready Interrupt Flag"]
14909 pub fn set_lsirdyf(&mut self, val: bool) {
14910 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
14911 }
14912 #[doc = "LSE ready Interrupt Flag"]
14913 pub const fn lserdyf(&self) -> bool {
14914 let val = (self.0 >> 1usize) & 0x01;
14915 val != 0
14916 }
14917 #[doc = "LSE ready Interrupt Flag"]
14918 pub fn set_lserdyf(&mut self, val: bool) {
14919 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
14920 }
14921 #[doc = "HSI ready Interrupt Flag"]
14922 pub const fn hsirdyf(&self) -> bool {
14923 let val = (self.0 >> 2usize) & 0x01;
14924 val != 0
14925 }
14926 #[doc = "HSI ready Interrupt Flag"]
14927 pub fn set_hsirdyf(&mut self, val: bool) {
14928 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
14929 }
14930 #[doc = "HSE ready Interrupt Flag"]
14931 pub const fn hserdyf(&self) -> bool {
14932>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
10196 let val = (self.0 >> 3usize) & 0x01; 14933 let val = (self.0 >> 3usize) & 0x01;
10197 super::vals::Hsidiven(val as u8) 14934 super::vals::Hsidiven(val as u8)
10198 } 14935 }
14936<<<<<<< HEAD
10199 #[doc = "HSI16DIVEN"] 14937 #[doc = "HSI16DIVEN"]
10200 pub fn set_hsi16diven(&mut self, val: super::vals::Hsidiven) { 14938 pub fn set_hsi16diven(&mut self, val: super::vals::Hsidiven) {
10201 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); 14939 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
@@ -10211,6 +14949,23 @@ pub mod rcc_l0 {
10211 } 14949 }
10212 #[doc = "16 MHz high-speed internal clock output enable"] 14950 #[doc = "16 MHz high-speed internal clock output enable"]
10213 pub const fn hsi16outen(&self) -> super::vals::Hsiouten { 14951 pub const fn hsi16outen(&self) -> super::vals::Hsiouten {
14952=======
14953 #[doc = "HSE ready Interrupt Flag"]
14954 pub fn set_hserdyf(&mut self, val: bool) {
14955 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
14956 }
14957 #[doc = "CSI ready Interrupt Flag"]
14958 pub const fn csirdy(&self) -> bool {
14959 let val = (self.0 >> 4usize) & 0x01;
14960 val != 0
14961 }
14962 #[doc = "CSI ready Interrupt Flag"]
14963 pub fn set_csirdy(&mut self, val: bool) {
14964 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
14965 }
14966 #[doc = "RC48 ready Interrupt Flag"]
14967 pub const fn hsi48rdyf(&self) -> bool {
14968>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
10214 let val = (self.0 >> 5usize) & 0x01; 14969 let val = (self.0 >> 5usize) & 0x01;
10215 super::vals::Hsiouten(val as u8) 14970 super::vals::Hsiouten(val as u8)
10216 } 14971 }
@@ -10232,6 +14987,7 @@ pub mod rcc_l0 {
10232 let val = (self.0 >> 9usize) & 0x01; 14987 let val = (self.0 >> 9usize) & 0x01;
10233 val != 0 14988 val != 0
10234 } 14989 }
14990<<<<<<< HEAD
10235 #[doc = "MSI clock ready flag"] 14991 #[doc = "MSI clock ready flag"]
10236 pub fn set_msirdy(&mut self, val: bool) { 14992 pub fn set_msirdy(&mut self, val: bool) {
10237 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); 14993 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
@@ -10711,9 +15467,652 @@ pub mod rcc_l0 {
10711 } 15467 }
10712 #[doc = "IOPBSMEN"] 15468 #[doc = "IOPBSMEN"]
10713 pub const fn iopbsmen(&self) -> super::vals::Iophsmen { 15469 pub const fn iopbsmen(&self) -> super::vals::Iophsmen {
15470=======
15471 #[doc = "RC48 ready Interrupt Flag"]
15472 pub fn set_hsi48rdyf(&mut self, val: bool) {
15473 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
15474 }
15475 #[doc = "PLL1 ready Interrupt Flag"]
15476 pub fn pllrdyf(&self, n: usize) -> bool {
15477 assert!(n < 3usize);
15478 let offs = 6usize + n * 1usize;
15479 let val = (self.0 >> offs) & 0x01;
15480 val != 0
15481 }
15482 #[doc = "PLL1 ready Interrupt Flag"]
15483 pub fn set_pllrdyf(&mut self, n: usize, val: bool) {
15484 assert!(n < 3usize);
15485 let offs = 6usize + n * 1usize;
15486 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
15487 }
15488 #[doc = "LSE clock security system Interrupt Flag"]
15489 pub const fn lsecssf(&self) -> bool {
15490 let val = (self.0 >> 9usize) & 0x01;
15491 val != 0
15492 }
15493 #[doc = "LSE clock security system Interrupt Flag"]
15494 pub fn set_lsecssf(&mut self, val: bool) {
15495 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
15496 }
15497 #[doc = "HSE clock security system Interrupt Flag"]
15498 pub const fn hsecssf(&self) -> bool {
15499 let val = (self.0 >> 10usize) & 0x01;
15500 val != 0
15501 }
15502 #[doc = "HSE clock security system Interrupt Flag"]
15503 pub fn set_hsecssf(&mut self, val: bool) {
15504 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
15505 }
15506 }
15507 impl Default for Cifr {
15508 fn default() -> Cifr {
15509 Cifr(0)
15510 }
15511 }
15512 #[doc = "RCC Domain 2 Clock Configuration Register"]
15513 #[repr(transparent)]
15514 #[derive(Copy, Clone, Eq, PartialEq)]
15515 pub struct D2cfgr(pub u32);
15516 impl D2cfgr {
15517 #[doc = "D2 domain APB1 prescaler"]
15518 pub const fn d2ppre1(&self) -> super::vals::D2ppre1 {
15519 let val = (self.0 >> 4usize) & 0x07;
15520 super::vals::D2ppre1(val as u8)
15521 }
15522 #[doc = "D2 domain APB1 prescaler"]
15523 pub fn set_d2ppre1(&mut self, val: super::vals::D2ppre1) {
15524 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
15525 }
15526 #[doc = "D2 domain APB2 prescaler"]
15527 pub const fn d2ppre2(&self) -> super::vals::D2ppre1 {
15528 let val = (self.0 >> 8usize) & 0x07;
15529 super::vals::D2ppre1(val as u8)
15530 }
15531 #[doc = "D2 domain APB2 prescaler"]
15532 pub fn set_d2ppre2(&mut self, val: super::vals::D2ppre1) {
15533 self.0 = (self.0 & !(0x07 << 8usize)) | (((val.0 as u32) & 0x07) << 8usize);
15534 }
15535 }
15536 impl Default for D2cfgr {
15537 fn default() -> D2cfgr {
15538 D2cfgr(0)
15539 }
15540 }
15541 #[doc = "RCC Domain 1 Kernel Clock Configuration Register"]
15542 #[repr(transparent)]
15543 #[derive(Copy, Clone, Eq, PartialEq)]
15544 pub struct D1ccipr(pub u32);
15545 impl D1ccipr {
15546 #[doc = "FMC kernel clock source selection"]
15547 pub const fn fmcsel(&self) -> super::vals::Fmcsel {
15548 let val = (self.0 >> 0usize) & 0x03;
15549 super::vals::Fmcsel(val as u8)
15550 }
15551 #[doc = "FMC kernel clock source selection"]
15552 pub fn set_fmcsel(&mut self, val: super::vals::Fmcsel) {
15553 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
15554 }
15555 #[doc = "QUADSPI kernel clock source selection"]
15556 pub const fn qspisel(&self) -> super::vals::Fmcsel {
15557 let val = (self.0 >> 4usize) & 0x03;
15558 super::vals::Fmcsel(val as u8)
15559 }
15560 #[doc = "QUADSPI kernel clock source selection"]
15561 pub fn set_qspisel(&mut self, val: super::vals::Fmcsel) {
15562 self.0 = (self.0 & !(0x03 << 4usize)) | (((val.0 as u32) & 0x03) << 4usize);
15563 }
15564 #[doc = "SDMMC kernel clock source selection"]
15565 pub const fn sdmmcsel(&self) -> super::vals::Sdmmcsel {
15566 let val = (self.0 >> 16usize) & 0x01;
15567 super::vals::Sdmmcsel(val as u8)
15568 }
15569 #[doc = "SDMMC kernel clock source selection"]
15570 pub fn set_sdmmcsel(&mut self, val: super::vals::Sdmmcsel) {
15571 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
15572 }
15573 #[doc = "per_ck clock source selection"]
15574 pub const fn ckpersel(&self) -> super::vals::Ckpersel {
15575 let val = (self.0 >> 28usize) & 0x03;
15576 super::vals::Ckpersel(val as u8)
15577 }
15578 #[doc = "per_ck clock source selection"]
15579 pub fn set_ckpersel(&mut self, val: super::vals::Ckpersel) {
15580 self.0 = (self.0 & !(0x03 << 28usize)) | (((val.0 as u32) & 0x03) << 28usize);
15581 }
15582 }
15583 impl Default for D1ccipr {
15584 fn default() -> D1ccipr {
15585 D1ccipr(0)
15586 }
15587 }
15588 #[doc = "RCC APB4 Sleep Clock Register"]
15589 #[repr(transparent)]
15590 #[derive(Copy, Clone, Eq, PartialEq)]
15591 pub struct C1Apb4lpenr(pub u32);
15592 impl C1Apb4lpenr {
15593 #[doc = "SYSCFG peripheral clock enable during CSleep mode"]
15594 pub const fn syscfglpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15595 let val = (self.0 >> 1usize) & 0x01;
15596 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15597 }
15598 #[doc = "SYSCFG peripheral clock enable during CSleep mode"]
15599 pub fn set_syscfglpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15600 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
15601 }
15602 #[doc = "LPUART1 Peripheral Clocks Enable During CSleep Mode"]
15603 pub const fn lpuart1lpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15604 let val = (self.0 >> 3usize) & 0x01;
15605 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15606 }
15607 #[doc = "LPUART1 Peripheral Clocks Enable During CSleep Mode"]
15608 pub fn set_lpuart1lpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15609 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
15610 }
15611 #[doc = "SPI6 Peripheral Clocks Enable During CSleep Mode"]
15612 pub const fn spi6lpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15613 let val = (self.0 >> 5usize) & 0x01;
15614 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15615 }
15616 #[doc = "SPI6 Peripheral Clocks Enable During CSleep Mode"]
15617 pub fn set_spi6lpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15618 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
15619 }
15620 #[doc = "I2C4 Peripheral Clocks Enable During CSleep Mode"]
15621 pub const fn i2c4lpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15622 let val = (self.0 >> 7usize) & 0x01;
15623 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15624 }
15625 #[doc = "I2C4 Peripheral Clocks Enable During CSleep Mode"]
15626 pub fn set_i2c4lpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15627 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
15628 }
15629 #[doc = "LPTIM2 Peripheral Clocks Enable During CSleep Mode"]
15630 pub const fn lptim2lpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15631 let val = (self.0 >> 9usize) & 0x01;
15632 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15633 }
15634 #[doc = "LPTIM2 Peripheral Clocks Enable During CSleep Mode"]
15635 pub fn set_lptim2lpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15636 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
15637 }
15638 #[doc = "LPTIM3 Peripheral Clocks Enable During CSleep Mode"]
15639 pub const fn lptim3lpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15640 let val = (self.0 >> 10usize) & 0x01;
15641 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15642 }
15643 #[doc = "LPTIM3 Peripheral Clocks Enable During CSleep Mode"]
15644 pub fn set_lptim3lpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15645 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
15646 }
15647 #[doc = "LPTIM4 Peripheral Clocks Enable During CSleep Mode"]
15648 pub const fn lptim4lpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15649 let val = (self.0 >> 11usize) & 0x01;
15650 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15651 }
15652 #[doc = "LPTIM4 Peripheral Clocks Enable During CSleep Mode"]
15653 pub fn set_lptim4lpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15654 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
15655 }
15656 #[doc = "LPTIM5 Peripheral Clocks Enable During CSleep Mode"]
15657 pub const fn lptim5lpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15658 let val = (self.0 >> 12usize) & 0x01;
15659 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15660 }
15661 #[doc = "LPTIM5 Peripheral Clocks Enable During CSleep Mode"]
15662 pub fn set_lptim5lpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15663 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
15664 }
15665 #[doc = "COMP1/2 peripheral clock enable during CSleep mode"]
15666 pub const fn comp12lpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15667 let val = (self.0 >> 14usize) & 0x01;
15668 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15669 }
15670 #[doc = "COMP1/2 peripheral clock enable during CSleep mode"]
15671 pub fn set_comp12lpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15672 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
15673 }
15674 #[doc = "VREF peripheral clock enable during CSleep mode"]
15675 pub const fn vreflpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15676 let val = (self.0 >> 15usize) & 0x01;
15677 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15678 }
15679 #[doc = "VREF peripheral clock enable during CSleep mode"]
15680 pub fn set_vreflpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15681 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
15682 }
15683 #[doc = "RTC APB Clock Enable During CSleep Mode"]
15684 pub const fn rtcapblpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15685 let val = (self.0 >> 16usize) & 0x01;
15686 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15687 }
15688 #[doc = "RTC APB Clock Enable During CSleep Mode"]
15689 pub fn set_rtcapblpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15690 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
15691 }
15692 #[doc = "SAI4 Peripheral Clocks Enable During CSleep Mode"]
15693 pub const fn sai4lpen(&self) -> super::vals::C1Apb4lpenrSyscfglpen {
15694 let val = (self.0 >> 21usize) & 0x01;
15695 super::vals::C1Apb4lpenrSyscfglpen(val as u8)
15696 }
15697 #[doc = "SAI4 Peripheral Clocks Enable During CSleep Mode"]
15698 pub fn set_sai4lpen(&mut self, val: super::vals::C1Apb4lpenrSyscfglpen) {
15699 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
15700 }
15701 }
15702 impl Default for C1Apb4lpenr {
15703 fn default() -> C1Apb4lpenr {
15704 C1Apb4lpenr(0)
15705 }
15706 }
15707 #[doc = "RCC AHB1 Clock Register"]
15708 #[repr(transparent)]
15709 #[derive(Copy, Clone, Eq, PartialEq)]
15710 pub struct C1Ahb1enr(pub u32);
15711 impl C1Ahb1enr {
15712 #[doc = "DMA1 Clock Enable"]
15713 pub const fn dma1en(&self) -> super::vals::C1Ahb1enrDma1en {
15714 let val = (self.0 >> 0usize) & 0x01;
15715 super::vals::C1Ahb1enrDma1en(val as u8)
15716 }
15717 #[doc = "DMA1 Clock Enable"]
15718 pub fn set_dma1en(&mut self, val: super::vals::C1Ahb1enrDma1en) {
15719 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
15720 }
15721 #[doc = "DMA2 Clock Enable"]
15722 pub const fn dma2en(&self) -> super::vals::C1Ahb1enrDma1en {
15723 let val = (self.0 >> 1usize) & 0x01;
15724 super::vals::C1Ahb1enrDma1en(val as u8)
15725 }
15726 #[doc = "DMA2 Clock Enable"]
15727 pub fn set_dma2en(&mut self, val: super::vals::C1Ahb1enrDma1en) {
15728 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
15729 }
15730 #[doc = "ADC1/2 Peripheral Clocks Enable"]
15731 pub const fn adc12en(&self) -> super::vals::C1Ahb1enrDma1en {
15732 let val = (self.0 >> 5usize) & 0x01;
15733 super::vals::C1Ahb1enrDma1en(val as u8)
15734 }
15735 #[doc = "ADC1/2 Peripheral Clocks Enable"]
15736 pub fn set_adc12en(&mut self, val: super::vals::C1Ahb1enrDma1en) {
15737 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
15738 }
15739 #[doc = "Ethernet MAC bus interface Clock Enable"]
15740 pub const fn eth1macen(&self) -> super::vals::C1Ahb1enrDma1en {
15741 let val = (self.0 >> 15usize) & 0x01;
15742 super::vals::C1Ahb1enrDma1en(val as u8)
15743 }
15744 #[doc = "Ethernet MAC bus interface Clock Enable"]
15745 pub fn set_eth1macen(&mut self, val: super::vals::C1Ahb1enrDma1en) {
15746 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
15747 }
15748 #[doc = "Ethernet Transmission Clock Enable"]
15749 pub const fn eth1txen(&self) -> super::vals::C1Ahb1enrDma1en {
15750 let val = (self.0 >> 16usize) & 0x01;
15751 super::vals::C1Ahb1enrDma1en(val as u8)
15752 }
15753 #[doc = "Ethernet Transmission Clock Enable"]
15754 pub fn set_eth1txen(&mut self, val: super::vals::C1Ahb1enrDma1en) {
15755 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
15756 }
15757 #[doc = "Ethernet Reception Clock Enable"]
15758 pub const fn eth1rxen(&self) -> super::vals::C1Ahb1enrDma1en {
15759 let val = (self.0 >> 17usize) & 0x01;
15760 super::vals::C1Ahb1enrDma1en(val as u8)
15761 }
15762 #[doc = "Ethernet Reception Clock Enable"]
15763 pub fn set_eth1rxen(&mut self, val: super::vals::C1Ahb1enrDma1en) {
15764 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
15765 }
15766 #[doc = "USB1OTG Peripheral Clocks Enable"]
15767 pub const fn usb1otgen(&self) -> super::vals::C1Ahb1enrDma1en {
15768 let val = (self.0 >> 25usize) & 0x01;
15769 super::vals::C1Ahb1enrDma1en(val as u8)
15770 }
15771 #[doc = "USB1OTG Peripheral Clocks Enable"]
15772 pub fn set_usb1otgen(&mut self, val: super::vals::C1Ahb1enrDma1en) {
15773 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.0 as u32) & 0x01) << 25usize);
15774 }
15775 #[doc = "USB_PHY1 Clocks Enable"]
15776 pub const fn usb1ulpien(&self) -> super::vals::C1Ahb1enrDma1en {
15777 let val = (self.0 >> 26usize) & 0x01;
15778 super::vals::C1Ahb1enrDma1en(val as u8)
15779 }
15780 #[doc = "USB_PHY1 Clocks Enable"]
15781 pub fn set_usb1ulpien(&mut self, val: super::vals::C1Ahb1enrDma1en) {
15782 self.0 = (self.0 & !(0x01 << 26usize)) | (((val.0 as u32) & 0x01) << 26usize);
15783 }
15784 #[doc = "USB2OTG Peripheral Clocks Enable"]
15785 pub const fn usb2otgen(&self) -> super::vals::C1Ahb1enrDma1en {
15786 let val = (self.0 >> 27usize) & 0x01;
15787 super::vals::C1Ahb1enrDma1en(val as u8)
15788 }
15789 #[doc = "USB2OTG Peripheral Clocks Enable"]
15790 pub fn set_usb2otgen(&mut self, val: super::vals::C1Ahb1enrDma1en) {
15791 self.0 = (self.0 & !(0x01 << 27usize)) | (((val.0 as u32) & 0x01) << 27usize);
15792 }
15793 #[doc = "USB_PHY2 Clocks Enable"]
15794 pub const fn usb2ulpien(&self) -> super::vals::C1Ahb1enrDma1en {
15795 let val = (self.0 >> 28usize) & 0x01;
15796 super::vals::C1Ahb1enrDma1en(val as u8)
15797 }
15798 #[doc = "USB_PHY2 Clocks Enable"]
15799 pub fn set_usb2ulpien(&mut self, val: super::vals::C1Ahb1enrDma1en) {
15800 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
15801 }
15802 }
15803 impl Default for C1Ahb1enr {
15804 fn default() -> C1Ahb1enr {
15805 C1Ahb1enr(0)
15806 }
15807 }
15808 #[doc = "RCC APB1 Clock Register"]
15809 #[repr(transparent)]
15810 #[derive(Copy, Clone, Eq, PartialEq)]
15811 pub struct C1Apb1henr(pub u32);
15812 impl C1Apb1henr {
15813 #[doc = "Clock Recovery System peripheral clock enable"]
15814 pub const fn crsen(&self) -> super::vals::C1Apb1henrCrsen {
15815 let val = (self.0 >> 1usize) & 0x01;
15816 super::vals::C1Apb1henrCrsen(val as u8)
15817 }
15818 #[doc = "Clock Recovery System peripheral clock enable"]
15819 pub fn set_crsen(&mut self, val: super::vals::C1Apb1henrCrsen) {
15820 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
15821 }
15822 #[doc = "SWPMI Peripheral Clocks Enable"]
15823 pub const fn swpen(&self) -> super::vals::C1Apb1henrCrsen {
15824 let val = (self.0 >> 2usize) & 0x01;
15825 super::vals::C1Apb1henrCrsen(val as u8)
15826 }
15827 #[doc = "SWPMI Peripheral Clocks Enable"]
15828 pub fn set_swpen(&mut self, val: super::vals::C1Apb1henrCrsen) {
15829 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
15830 }
15831 #[doc = "OPAMP peripheral clock enable"]
15832 pub const fn opampen(&self) -> super::vals::C1Apb1henrCrsen {
15833 let val = (self.0 >> 4usize) & 0x01;
15834 super::vals::C1Apb1henrCrsen(val as u8)
15835 }
15836 #[doc = "OPAMP peripheral clock enable"]
15837 pub fn set_opampen(&mut self, val: super::vals::C1Apb1henrCrsen) {
15838 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
15839 }
15840 #[doc = "MDIOS peripheral clock enable"]
15841 pub const fn mdiosen(&self) -> super::vals::C1Apb1henrCrsen {
15842 let val = (self.0 >> 5usize) & 0x01;
15843 super::vals::C1Apb1henrCrsen(val as u8)
15844 }
15845 #[doc = "MDIOS peripheral clock enable"]
15846 pub fn set_mdiosen(&mut self, val: super::vals::C1Apb1henrCrsen) {
15847 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
15848 }
15849 #[doc = "FDCAN Peripheral Clocks Enable"]
15850 pub const fn fdcanen(&self) -> super::vals::C1Apb1henrCrsen {
15851 let val = (self.0 >> 8usize) & 0x01;
15852 super::vals::C1Apb1henrCrsen(val as u8)
15853 }
15854 #[doc = "FDCAN Peripheral Clocks Enable"]
15855 pub fn set_fdcanen(&mut self, val: super::vals::C1Apb1henrCrsen) {
15856 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
15857 }
15858 }
15859 impl Default for C1Apb1henr {
15860 fn default() -> C1Apb1henr {
15861 C1Apb1henr(0)
15862 }
15863 }
15864 #[doc = "RCC AHB2 Clock Register"]
15865 #[repr(transparent)]
15866 #[derive(Copy, Clone, Eq, PartialEq)]
15867 pub struct C1Ahb2enr(pub u32);
15868 impl C1Ahb2enr {
15869 #[doc = "DCMI peripheral clock"]
15870 pub const fn dcmien(&self) -> super::vals::C1Ahb2enrDcmien {
15871 let val = (self.0 >> 0usize) & 0x01;
15872 super::vals::C1Ahb2enrDcmien(val as u8)
15873 }
15874 #[doc = "DCMI peripheral clock"]
15875 pub fn set_dcmien(&mut self, val: super::vals::C1Ahb2enrDcmien) {
15876 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
15877 }
15878 #[doc = "CRYPT peripheral clock enable"]
15879 pub const fn crypten(&self) -> super::vals::C1Ahb2enrDcmien {
15880 let val = (self.0 >> 4usize) & 0x01;
15881 super::vals::C1Ahb2enrDcmien(val as u8)
15882 }
15883 #[doc = "CRYPT peripheral clock enable"]
15884 pub fn set_crypten(&mut self, val: super::vals::C1Ahb2enrDcmien) {
15885 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
15886 }
15887 #[doc = "HASH peripheral clock enable"]
15888 pub const fn hashen(&self) -> super::vals::C1Ahb2enrDcmien {
15889 let val = (self.0 >> 5usize) & 0x01;
15890 super::vals::C1Ahb2enrDcmien(val as u8)
15891 }
15892 #[doc = "HASH peripheral clock enable"]
15893 pub fn set_hashen(&mut self, val: super::vals::C1Ahb2enrDcmien) {
15894 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
15895 }
15896 #[doc = "RNG peripheral clocks enable"]
15897 pub const fn rngen(&self) -> super::vals::C1Ahb2enrDcmien {
15898 let val = (self.0 >> 6usize) & 0x01;
15899 super::vals::C1Ahb2enrDcmien(val as u8)
15900 }
15901 #[doc = "RNG peripheral clocks enable"]
15902 pub fn set_rngen(&mut self, val: super::vals::C1Ahb2enrDcmien) {
15903 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
15904 }
15905 #[doc = "SDMMC2 and SDMMC2 delay clock enable"]
15906 pub const fn sdmmc2en(&self) -> super::vals::C1Ahb2enrDcmien {
15907 let val = (self.0 >> 9usize) & 0x01;
15908 super::vals::C1Ahb2enrDcmien(val as u8)
15909 }
15910 #[doc = "SDMMC2 and SDMMC2 delay clock enable"]
15911 pub fn set_sdmmc2en(&mut self, val: super::vals::C1Ahb2enrDcmien) {
15912 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
15913 }
15914 #[doc = "SRAM1 block enable"]
15915 pub const fn sram1en(&self) -> super::vals::C1Ahb2enrDcmien {
15916 let val = (self.0 >> 29usize) & 0x01;
15917 super::vals::C1Ahb2enrDcmien(val as u8)
15918 }
15919 #[doc = "SRAM1 block enable"]
15920 pub fn set_sram1en(&mut self, val: super::vals::C1Ahb2enrDcmien) {
15921 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
15922 }
15923 #[doc = "SRAM2 block enable"]
15924 pub const fn sram2en(&self) -> super::vals::C1Ahb2enrDcmien {
15925 let val = (self.0 >> 30usize) & 0x01;
15926 super::vals::C1Ahb2enrDcmien(val as u8)
15927 }
15928 #[doc = "SRAM2 block enable"]
15929 pub fn set_sram2en(&mut self, val: super::vals::C1Ahb2enrDcmien) {
15930 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
15931 }
15932 #[doc = "SRAM3 block enable"]
15933 pub const fn sram3en(&self) -> super::vals::C1Ahb2enrDcmien {
15934 let val = (self.0 >> 31usize) & 0x01;
15935 super::vals::C1Ahb2enrDcmien(val as u8)
15936 }
15937 #[doc = "SRAM3 block enable"]
15938 pub fn set_sram3en(&mut self, val: super::vals::C1Ahb2enrDcmien) {
15939 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
15940 }
15941 }
15942 impl Default for C1Ahb2enr {
15943 fn default() -> C1Ahb2enr {
15944 C1Ahb2enr(0)
15945 }
15946 }
15947 #[doc = "RCC APB3 Clock Register"]
15948 #[repr(transparent)]
15949 #[derive(Copy, Clone, Eq, PartialEq)]
15950 pub struct Apb3enr(pub u32);
15951 impl Apb3enr {
15952 #[doc = "LTDC peripheral clock enable"]
15953 pub const fn ltdcen(&self) -> super::vals::Apb3enrLtdcen {
15954 let val = (self.0 >> 3usize) & 0x01;
15955 super::vals::Apb3enrLtdcen(val as u8)
15956 }
15957 #[doc = "LTDC peripheral clock enable"]
15958 pub fn set_ltdcen(&mut self, val: super::vals::Apb3enrLtdcen) {
15959 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
15960 }
15961 #[doc = "WWDG1 Clock Enable"]
15962 pub const fn wwdg1en(&self) -> super::vals::Apb3enrLtdcen {
15963 let val = (self.0 >> 6usize) & 0x01;
15964 super::vals::Apb3enrLtdcen(val as u8)
15965 }
15966 #[doc = "WWDG1 Clock Enable"]
15967 pub fn set_wwdg1en(&mut self, val: super::vals::Apb3enrLtdcen) {
15968 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
15969 }
15970 }
15971 impl Default for Apb3enr {
15972 fn default() -> Apb3enr {
15973 Apb3enr(0)
15974 }
15975 }
15976 #[doc = "RCC APB4 Clock Register"]
15977 #[repr(transparent)]
15978 #[derive(Copy, Clone, Eq, PartialEq)]
15979 pub struct C1Apb4enr(pub u32);
15980 impl C1Apb4enr {
15981 #[doc = "SYSCFG peripheral clock enable"]
15982 pub const fn syscfgen(&self) -> super::vals::C1Apb4enrSyscfgen {
15983 let val = (self.0 >> 1usize) & 0x01;
15984 super::vals::C1Apb4enrSyscfgen(val as u8)
15985 }
15986 #[doc = "SYSCFG peripheral clock enable"]
15987 pub fn set_syscfgen(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
15988 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
15989 }
15990 #[doc = "LPUART1 Peripheral Clocks Enable"]
15991 pub const fn lpuart1en(&self) -> super::vals::C1Apb4enrSyscfgen {
15992 let val = (self.0 >> 3usize) & 0x01;
15993 super::vals::C1Apb4enrSyscfgen(val as u8)
15994 }
15995 #[doc = "LPUART1 Peripheral Clocks Enable"]
15996 pub fn set_lpuart1en(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
15997 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
15998 }
15999 #[doc = "SPI6 Peripheral Clocks Enable"]
16000 pub const fn spi6en(&self) -> super::vals::C1Apb4enrSyscfgen {
16001 let val = (self.0 >> 5usize) & 0x01;
16002 super::vals::C1Apb4enrSyscfgen(val as u8)
16003 }
16004 #[doc = "SPI6 Peripheral Clocks Enable"]
16005 pub fn set_spi6en(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
16006 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
16007 }
16008 #[doc = "I2C4 Peripheral Clocks Enable"]
16009 pub const fn i2c4en(&self) -> super::vals::C1Apb4enrSyscfgen {
16010 let val = (self.0 >> 7usize) & 0x01;
16011 super::vals::C1Apb4enrSyscfgen(val as u8)
16012 }
16013 #[doc = "I2C4 Peripheral Clocks Enable"]
16014 pub fn set_i2c4en(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
16015 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
16016 }
16017 #[doc = "LPTIM2 Peripheral Clocks Enable"]
16018 pub const fn lptim2en(&self) -> super::vals::C1Apb4enrSyscfgen {
16019 let val = (self.0 >> 9usize) & 0x01;
16020 super::vals::C1Apb4enrSyscfgen(val as u8)
16021 }
16022 #[doc = "LPTIM2 Peripheral Clocks Enable"]
16023 pub fn set_lptim2en(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
16024 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
16025 }
16026 #[doc = "LPTIM3 Peripheral Clocks Enable"]
16027 pub const fn lptim3en(&self) -> super::vals::C1Apb4enrSyscfgen {
16028 let val = (self.0 >> 10usize) & 0x01;
16029 super::vals::C1Apb4enrSyscfgen(val as u8)
16030 }
16031 #[doc = "LPTIM3 Peripheral Clocks Enable"]
16032 pub fn set_lptim3en(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
16033 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
16034 }
16035 #[doc = "LPTIM4 Peripheral Clocks Enable"]
16036 pub const fn lptim4en(&self) -> super::vals::C1Apb4enrSyscfgen {
16037 let val = (self.0 >> 11usize) & 0x01;
16038 super::vals::C1Apb4enrSyscfgen(val as u8)
16039 }
16040 #[doc = "LPTIM4 Peripheral Clocks Enable"]
16041 pub fn set_lptim4en(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
16042 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
16043 }
16044 #[doc = "LPTIM5 Peripheral Clocks Enable"]
16045 pub const fn lptim5en(&self) -> super::vals::C1Apb4enrSyscfgen {
16046 let val = (self.0 >> 12usize) & 0x01;
16047 super::vals::C1Apb4enrSyscfgen(val as u8)
16048 }
16049 #[doc = "LPTIM5 Peripheral Clocks Enable"]
16050 pub fn set_lptim5en(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
16051 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
16052 }
16053 #[doc = "COMP1/2 peripheral clock enable"]
16054 pub const fn comp12en(&self) -> super::vals::C1Apb4enrSyscfgen {
16055 let val = (self.0 >> 14usize) & 0x01;
16056 super::vals::C1Apb4enrSyscfgen(val as u8)
16057 }
16058 #[doc = "COMP1/2 peripheral clock enable"]
16059 pub fn set_comp12en(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
16060 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
16061 }
16062 #[doc = "VREF peripheral clock enable"]
16063 pub const fn vrefen(&self) -> super::vals::C1Apb4enrSyscfgen {
16064 let val = (self.0 >> 15usize) & 0x01;
16065 super::vals::C1Apb4enrSyscfgen(val as u8)
16066 }
16067 #[doc = "VREF peripheral clock enable"]
16068 pub fn set_vrefen(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
16069 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
16070 }
16071 #[doc = "RTC APB Clock Enable"]
16072 pub const fn rtcapben(&self) -> super::vals::C1Apb4enrSyscfgen {
16073 let val = (self.0 >> 16usize) & 0x01;
16074 super::vals::C1Apb4enrSyscfgen(val as u8)
16075 }
16076 #[doc = "RTC APB Clock Enable"]
16077 pub fn set_rtcapben(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
16078 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
16079 }
16080 #[doc = "SAI4 Peripheral Clocks Enable"]
16081 pub const fn sai4en(&self) -> super::vals::C1Apb4enrSyscfgen {
16082 let val = (self.0 >> 21usize) & 0x01;
16083 super::vals::C1Apb4enrSyscfgen(val as u8)
16084 }
16085 #[doc = "SAI4 Peripheral Clocks Enable"]
16086 pub fn set_sai4en(&mut self, val: super::vals::C1Apb4enrSyscfgen) {
16087 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
16088 }
16089 }
16090 impl Default for C1Apb4enr {
16091 fn default() -> C1Apb4enr {
16092 C1Apb4enr(0)
16093 }
16094 }
16095 #[doc = "RCC Clock Control and Status Register"]
16096 #[repr(transparent)]
16097 #[derive(Copy, Clone, Eq, PartialEq)]
16098 pub struct Csr(pub u32);
16099 impl Csr {
16100 #[doc = "LSI oscillator enable"]
16101 pub const fn lsion(&self) -> super::vals::Lsion {
16102 let val = (self.0 >> 0usize) & 0x01;
16103 super::vals::Lsion(val as u8)
16104 }
16105 #[doc = "LSI oscillator enable"]
16106 pub fn set_lsion(&mut self, val: super::vals::Lsion) {
16107 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
16108 }
16109 #[doc = "LSI oscillator ready"]
16110 pub const fn lsirdy(&self) -> bool {
16111>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
10714 let val = (self.0 >> 1usize) & 0x01; 16112 let val = (self.0 >> 1usize) & 0x01;
10715 super::vals::Iophsmen(val as u8) 16113 super::vals::Iophsmen(val as u8)
10716 } 16114 }
16115<<<<<<< HEAD
10717 #[doc = "IOPBSMEN"] 16116 #[doc = "IOPBSMEN"]
10718 pub fn set_iopbsmen(&mut self, val: super::vals::Iophsmen) { 16117 pub fn set_iopbsmen(&mut self, val: super::vals::Iophsmen) {
10719 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); 16118 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
@@ -12183,12 +17582,1094 @@ pub mod rcc_l0 {
12183 impl Default for Ahbrstr { 17582 impl Default for Ahbrstr {
12184 fn default() -> Ahbrstr { 17583 fn default() -> Ahbrstr {
12185 Ahbrstr(0) 17584 Ahbrstr(0)
17585=======
17586 #[doc = "LSI oscillator ready"]
17587 pub fn set_lsirdy(&mut self, val: bool) {
17588 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
12186 } 17589 }
12187 } 17590 }
12188 } 17591 impl Default for Csr {
12189 pub mod vals { 17592 fn default() -> Csr {
12190 use crate::generic::*; 17593 Csr(0)
17594 }
17595 }
17596 #[doc = "RCC APB3 Clock Register"]
17597 #[repr(transparent)]
17598 #[derive(Copy, Clone, Eq, PartialEq)]
17599 pub struct C1Apb3enr(pub u32);
17600 impl C1Apb3enr {
17601 #[doc = "LTDC peripheral clock enable"]
17602 pub const fn ltdcen(&self) -> super::vals::C1Apb3enrLtdcen {
17603 let val = (self.0 >> 3usize) & 0x01;
17604 super::vals::C1Apb3enrLtdcen(val as u8)
17605 }
17606 #[doc = "LTDC peripheral clock enable"]
17607 pub fn set_ltdcen(&mut self, val: super::vals::C1Apb3enrLtdcen) {
17608 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
17609 }
17610 #[doc = "WWDG1 Clock Enable"]
17611 pub const fn wwdg1en(&self) -> super::vals::C1Apb3enrLtdcen {
17612 let val = (self.0 >> 6usize) & 0x01;
17613 super::vals::C1Apb3enrLtdcen(val as u8)
17614 }
17615 #[doc = "WWDG1 Clock Enable"]
17616 pub fn set_wwdg1en(&mut self, val: super::vals::C1Apb3enrLtdcen) {
17617 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
17618 }
17619 }
17620 impl Default for C1Apb3enr {
17621 fn default() -> C1Apb3enr {
17622 C1Apb3enr(0)
17623 }
17624 }
17625 #[doc = "RCC AHB4 Sleep Clock Register"]
17626 #[repr(transparent)]
17627 #[derive(Copy, Clone, Eq, PartialEq)]
17628 pub struct C1Ahb4lpenr(pub u32);
17629 impl C1Ahb4lpenr {
17630 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17631 pub const fn gpioalpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17632 let val = (self.0 >> 0usize) & 0x01;
17633 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17634 }
17635 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17636 pub fn set_gpioalpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17637 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
17638 }
17639 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17640 pub const fn gpioblpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17641 let val = (self.0 >> 1usize) & 0x01;
17642 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17643 }
17644 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17645 pub fn set_gpioblpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17646 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
17647 }
17648 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17649 pub const fn gpioclpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17650 let val = (self.0 >> 2usize) & 0x01;
17651 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17652 }
17653 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17654 pub fn set_gpioclpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17655 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
17656 }
17657 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17658 pub const fn gpiodlpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17659 let val = (self.0 >> 3usize) & 0x01;
17660 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17661 }
17662 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17663 pub fn set_gpiodlpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17664 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
17665 }
17666 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17667 pub const fn gpioelpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17668 let val = (self.0 >> 4usize) & 0x01;
17669 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17670 }
17671 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17672 pub fn set_gpioelpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17673 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
17674 }
17675 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17676 pub const fn gpioflpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17677 let val = (self.0 >> 5usize) & 0x01;
17678 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17679 }
17680 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17681 pub fn set_gpioflpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17682 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
17683 }
17684 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17685 pub const fn gpioglpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17686 let val = (self.0 >> 6usize) & 0x01;
17687 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17688 }
17689 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17690 pub fn set_gpioglpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17691 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
17692 }
17693 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17694 pub const fn gpiohlpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17695 let val = (self.0 >> 7usize) & 0x01;
17696 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17697 }
17698 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17699 pub fn set_gpiohlpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17700 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
17701 }
17702 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17703 pub const fn gpioilpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17704 let val = (self.0 >> 8usize) & 0x01;
17705 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17706 }
17707 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17708 pub fn set_gpioilpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17709 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
17710 }
17711 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17712 pub const fn gpiojlpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17713 let val = (self.0 >> 9usize) & 0x01;
17714 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17715 }
17716 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17717 pub fn set_gpiojlpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17718 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
17719 }
17720 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17721 pub const fn gpioklpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17722 let val = (self.0 >> 10usize) & 0x01;
17723 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17724 }
17725 #[doc = "GPIO peripheral clock enable during CSleep mode"]
17726 pub fn set_gpioklpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17727 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
17728 }
17729 #[doc = "CRC peripheral clock enable during CSleep mode"]
17730 pub const fn crclpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17731 let val = (self.0 >> 19usize) & 0x01;
17732 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17733 }
17734 #[doc = "CRC peripheral clock enable during CSleep mode"]
17735 pub fn set_crclpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17736 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
17737 }
17738 #[doc = "BDMA Clock Enable During CSleep Mode"]
17739 pub const fn bdmalpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17740 let val = (self.0 >> 21usize) & 0x01;
17741 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17742 }
17743 #[doc = "BDMA Clock Enable During CSleep Mode"]
17744 pub fn set_bdmalpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17745 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
17746 }
17747 #[doc = "ADC3 Peripheral Clocks Enable During CSleep Mode"]
17748 pub const fn adc3lpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17749 let val = (self.0 >> 24usize) & 0x01;
17750 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17751 }
17752 #[doc = "ADC3 Peripheral Clocks Enable During CSleep Mode"]
17753 pub fn set_adc3lpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17754 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
17755 }
17756 #[doc = "Backup RAM Clock Enable During CSleep Mode"]
17757 pub const fn bkpramlpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17758 let val = (self.0 >> 28usize) & 0x01;
17759 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17760 }
17761 #[doc = "Backup RAM Clock Enable During CSleep Mode"]
17762 pub fn set_bkpramlpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17763 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
17764 }
17765 #[doc = "SRAM4 Clock Enable During CSleep Mode"]
17766 pub const fn sram4lpen(&self) -> super::vals::C1Ahb4lpenrGpioalpen {
17767 let val = (self.0 >> 29usize) & 0x01;
17768 super::vals::C1Ahb4lpenrGpioalpen(val as u8)
17769 }
17770 #[doc = "SRAM4 Clock Enable During CSleep Mode"]
17771 pub fn set_sram4lpen(&mut self, val: super::vals::C1Ahb4lpenrGpioalpen) {
17772 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
17773 }
17774 }
17775 impl Default for C1Ahb4lpenr {
17776 fn default() -> C1Ahb4lpenr {
17777 C1Ahb4lpenr(0)
17778 }
17779 }
17780 #[doc = "RCC AHB2 Peripheral Reset Register"]
17781 #[repr(transparent)]
17782 #[derive(Copy, Clone, Eq, PartialEq)]
17783 pub struct Ahb2rstr(pub u32);
17784 impl Ahb2rstr {
17785 #[doc = "CAMITF block reset"]
17786 pub const fn camitfrst(&self) -> super::vals::Camitfrst {
17787 let val = (self.0 >> 0usize) & 0x01;
17788 super::vals::Camitfrst(val as u8)
17789 }
17790 #[doc = "CAMITF block reset"]
17791 pub fn set_camitfrst(&mut self, val: super::vals::Camitfrst) {
17792 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
17793 }
17794 #[doc = "Cryptography block reset"]
17795 pub const fn cryptrst(&self) -> super::vals::Camitfrst {
17796 let val = (self.0 >> 4usize) & 0x01;
17797 super::vals::Camitfrst(val as u8)
17798 }
17799 #[doc = "Cryptography block reset"]
17800 pub fn set_cryptrst(&mut self, val: super::vals::Camitfrst) {
17801 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
17802 }
17803 #[doc = "Hash block reset"]
17804 pub const fn hashrst(&self) -> super::vals::Camitfrst {
17805 let val = (self.0 >> 5usize) & 0x01;
17806 super::vals::Camitfrst(val as u8)
17807 }
17808 #[doc = "Hash block reset"]
17809 pub fn set_hashrst(&mut self, val: super::vals::Camitfrst) {
17810 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
17811 }
17812 #[doc = "Random Number Generator block reset"]
17813 pub const fn rngrst(&self) -> super::vals::Camitfrst {
17814 let val = (self.0 >> 6usize) & 0x01;
17815 super::vals::Camitfrst(val as u8)
17816 }
17817 #[doc = "Random Number Generator block reset"]
17818 pub fn set_rngrst(&mut self, val: super::vals::Camitfrst) {
17819 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
17820 }
17821 #[doc = "SDMMC2 and SDMMC2 Delay block reset"]
17822 pub const fn sdmmc2rst(&self) -> super::vals::Camitfrst {
17823 let val = (self.0 >> 9usize) & 0x01;
17824 super::vals::Camitfrst(val as u8)
17825 }
17826 #[doc = "SDMMC2 and SDMMC2 Delay block reset"]
17827 pub fn set_sdmmc2rst(&mut self, val: super::vals::Camitfrst) {
17828 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
17829 }
17830 }
17831 impl Default for Ahb2rstr {
17832 fn default() -> Ahb2rstr {
17833 Ahb2rstr(0)
17834 }
17835 }
17836 #[doc = "RCC PLL3 Fractional Divider Register"]
17837 #[repr(transparent)]
17838 #[derive(Copy, Clone, Eq, PartialEq)]
17839 pub struct Pll3fracr(pub u32);
17840 impl Pll3fracr {
17841 #[doc = "Fractional part of the multiplication factor for PLL3 VCO"]
17842 pub const fn fracn3(&self) -> u16 {
17843 let val = (self.0 >> 3usize) & 0x1fff;
17844 val as u16
17845 }
17846 #[doc = "Fractional part of the multiplication factor for PLL3 VCO"]
17847 pub fn set_fracn3(&mut self, val: u16) {
17848 self.0 = (self.0 & !(0x1fff << 3usize)) | (((val as u32) & 0x1fff) << 3usize);
17849 }
17850 }
17851 impl Default for Pll3fracr {
17852 fn default() -> Pll3fracr {
17853 Pll3fracr(0)
17854 }
17855 }
17856 #[doc = "RCC HSI configuration register"]
17857 #[repr(transparent)]
17858 #[derive(Copy, Clone, Eq, PartialEq)]
17859 pub struct Hsicfgr(pub u32);
17860 impl Hsicfgr {
17861 #[doc = "HSI clock calibration"]
17862 pub const fn hsical(&self) -> u16 {
17863 let val = (self.0 >> 0usize) & 0x0fff;
17864 val as u16
17865 }
17866 #[doc = "HSI clock calibration"]
17867 pub fn set_hsical(&mut self, val: u16) {
17868 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
17869 }
17870 #[doc = "HSI clock trimming"]
17871 pub const fn hsitrim(&self) -> u8 {
17872 let val = (self.0 >> 24usize) & 0x7f;
17873 val as u8
17874 }
17875 #[doc = "HSI clock trimming"]
17876 pub fn set_hsitrim(&mut self, val: u8) {
17877 self.0 = (self.0 & !(0x7f << 24usize)) | (((val as u32) & 0x7f) << 24usize);
17878 }
17879 }
17880 impl Default for Hsicfgr {
17881 fn default() -> Hsicfgr {
17882 Hsicfgr(0)
17883 }
17884 }
17885 #[doc = "RCC APB1 Clock Register"]
17886 #[repr(transparent)]
17887 #[derive(Copy, Clone, Eq, PartialEq)]
17888 pub struct C1Apb1lenr(pub u32);
17889 impl C1Apb1lenr {
17890 #[doc = "TIM peripheral clock enable"]
17891 pub const fn tim2en(&self) -> super::vals::C1Apb1lenrTim2en {
17892 let val = (self.0 >> 0usize) & 0x01;
17893 super::vals::C1Apb1lenrTim2en(val as u8)
17894 }
17895 #[doc = "TIM peripheral clock enable"]
17896 pub fn set_tim2en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17897 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
17898 }
17899 #[doc = "TIM peripheral clock enable"]
17900 pub const fn tim3en(&self) -> super::vals::C1Apb1lenrTim2en {
17901 let val = (self.0 >> 1usize) & 0x01;
17902 super::vals::C1Apb1lenrTim2en(val as u8)
17903 }
17904 #[doc = "TIM peripheral clock enable"]
17905 pub fn set_tim3en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17906 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
17907 }
17908 #[doc = "TIM peripheral clock enable"]
17909 pub const fn tim4en(&self) -> super::vals::C1Apb1lenrTim2en {
17910 let val = (self.0 >> 2usize) & 0x01;
17911 super::vals::C1Apb1lenrTim2en(val as u8)
17912 }
17913 #[doc = "TIM peripheral clock enable"]
17914 pub fn set_tim4en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17915 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
17916 }
17917 #[doc = "TIM peripheral clock enable"]
17918 pub const fn tim5en(&self) -> super::vals::C1Apb1lenrTim2en {
17919 let val = (self.0 >> 3usize) & 0x01;
17920 super::vals::C1Apb1lenrTim2en(val as u8)
17921 }
17922 #[doc = "TIM peripheral clock enable"]
17923 pub fn set_tim5en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17924 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
17925 }
17926 #[doc = "TIM peripheral clock enable"]
17927 pub const fn tim6en(&self) -> super::vals::C1Apb1lenrTim2en {
17928 let val = (self.0 >> 4usize) & 0x01;
17929 super::vals::C1Apb1lenrTim2en(val as u8)
17930 }
17931 #[doc = "TIM peripheral clock enable"]
17932 pub fn set_tim6en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17933 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
17934 }
17935 #[doc = "TIM peripheral clock enable"]
17936 pub const fn tim7en(&self) -> super::vals::C1Apb1lenrTim2en {
17937 let val = (self.0 >> 5usize) & 0x01;
17938 super::vals::C1Apb1lenrTim2en(val as u8)
17939 }
17940 #[doc = "TIM peripheral clock enable"]
17941 pub fn set_tim7en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17942 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
17943 }
17944 #[doc = "TIM peripheral clock enable"]
17945 pub const fn tim12en(&self) -> super::vals::C1Apb1lenrTim2en {
17946 let val = (self.0 >> 6usize) & 0x01;
17947 super::vals::C1Apb1lenrTim2en(val as u8)
17948 }
17949 #[doc = "TIM peripheral clock enable"]
17950 pub fn set_tim12en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17951 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
17952 }
17953 #[doc = "TIM peripheral clock enable"]
17954 pub const fn tim13en(&self) -> super::vals::C1Apb1lenrTim2en {
17955 let val = (self.0 >> 7usize) & 0x01;
17956 super::vals::C1Apb1lenrTim2en(val as u8)
17957 }
17958 #[doc = "TIM peripheral clock enable"]
17959 pub fn set_tim13en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17960 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
17961 }
17962 #[doc = "TIM peripheral clock enable"]
17963 pub const fn tim14en(&self) -> super::vals::C1Apb1lenrTim2en {
17964 let val = (self.0 >> 8usize) & 0x01;
17965 super::vals::C1Apb1lenrTim2en(val as u8)
17966 }
17967 #[doc = "TIM peripheral clock enable"]
17968 pub fn set_tim14en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17969 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
17970 }
17971 #[doc = "LPTIM1 Peripheral Clocks Enable"]
17972 pub const fn lptim1en(&self) -> super::vals::C1Apb1lenrTim2en {
17973 let val = (self.0 >> 9usize) & 0x01;
17974 super::vals::C1Apb1lenrTim2en(val as u8)
17975 }
17976 #[doc = "LPTIM1 Peripheral Clocks Enable"]
17977 pub fn set_lptim1en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17978 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
17979 }
17980 #[doc = "SPI2 Peripheral Clocks Enable"]
17981 pub const fn spi2en(&self) -> super::vals::C1Apb1lenrTim2en {
17982 let val = (self.0 >> 14usize) & 0x01;
17983 super::vals::C1Apb1lenrTim2en(val as u8)
17984 }
17985 #[doc = "SPI2 Peripheral Clocks Enable"]
17986 pub fn set_spi2en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17987 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
17988 }
17989 #[doc = "SPI3 Peripheral Clocks Enable"]
17990 pub const fn spi3en(&self) -> super::vals::C1Apb1lenrTim2en {
17991 let val = (self.0 >> 15usize) & 0x01;
17992 super::vals::C1Apb1lenrTim2en(val as u8)
17993 }
17994 #[doc = "SPI3 Peripheral Clocks Enable"]
17995 pub fn set_spi3en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
17996 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
17997 }
17998 #[doc = "SPDIFRX Peripheral Clocks Enable"]
17999 pub const fn spdifrxen(&self) -> super::vals::C1Apb1lenrTim2en {
18000 let val = (self.0 >> 16usize) & 0x01;
18001 super::vals::C1Apb1lenrTim2en(val as u8)
18002 }
18003 #[doc = "SPDIFRX Peripheral Clocks Enable"]
18004 pub fn set_spdifrxen(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18005 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
18006 }
18007 #[doc = "USART2 Peripheral Clocks Enable"]
18008 pub const fn usart2en(&self) -> super::vals::C1Apb1lenrTim2en {
18009 let val = (self.0 >> 17usize) & 0x01;
18010 super::vals::C1Apb1lenrTim2en(val as u8)
18011 }
18012 #[doc = "USART2 Peripheral Clocks Enable"]
18013 pub fn set_usart2en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18014 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
18015 }
18016 #[doc = "USART3 Peripheral Clocks Enable"]
18017 pub const fn usart3en(&self) -> super::vals::C1Apb1lenrTim2en {
18018 let val = (self.0 >> 18usize) & 0x01;
18019 super::vals::C1Apb1lenrTim2en(val as u8)
18020 }
18021 #[doc = "USART3 Peripheral Clocks Enable"]
18022 pub fn set_usart3en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18023 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
18024 }
18025 #[doc = "UART4 Peripheral Clocks Enable"]
18026 pub const fn uart4en(&self) -> super::vals::C1Apb1lenrTim2en {
18027 let val = (self.0 >> 19usize) & 0x01;
18028 super::vals::C1Apb1lenrTim2en(val as u8)
18029 }
18030 #[doc = "UART4 Peripheral Clocks Enable"]
18031 pub fn set_uart4en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18032 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
18033 }
18034 #[doc = "UART5 Peripheral Clocks Enable"]
18035 pub const fn uart5en(&self) -> super::vals::C1Apb1lenrTim2en {
18036 let val = (self.0 >> 20usize) & 0x01;
18037 super::vals::C1Apb1lenrTim2en(val as u8)
18038 }
18039 #[doc = "UART5 Peripheral Clocks Enable"]
18040 pub fn set_uart5en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18041 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.0 as u32) & 0x01) << 20usize);
18042 }
18043 #[doc = "I2C1 Peripheral Clocks Enable"]
18044 pub const fn i2c1en(&self) -> super::vals::C1Apb1lenrTim2en {
18045 let val = (self.0 >> 21usize) & 0x01;
18046 super::vals::C1Apb1lenrTim2en(val as u8)
18047 }
18048 #[doc = "I2C1 Peripheral Clocks Enable"]
18049 pub fn set_i2c1en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18050 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
18051 }
18052 #[doc = "I2C2 Peripheral Clocks Enable"]
18053 pub const fn i2c2en(&self) -> super::vals::C1Apb1lenrTim2en {
18054 let val = (self.0 >> 22usize) & 0x01;
18055 super::vals::C1Apb1lenrTim2en(val as u8)
18056 }
18057 #[doc = "I2C2 Peripheral Clocks Enable"]
18058 pub fn set_i2c2en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18059 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
18060 }
18061 #[doc = "I2C3 Peripheral Clocks Enable"]
18062 pub const fn i2c3en(&self) -> super::vals::C1Apb1lenrTim2en {
18063 let val = (self.0 >> 23usize) & 0x01;
18064 super::vals::C1Apb1lenrTim2en(val as u8)
18065 }
18066 #[doc = "I2C3 Peripheral Clocks Enable"]
18067 pub fn set_i2c3en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18068 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
18069 }
18070 #[doc = "HDMI-CEC peripheral clock enable"]
18071 pub const fn cecen(&self) -> super::vals::C1Apb1lenrTim2en {
18072 let val = (self.0 >> 27usize) & 0x01;
18073 super::vals::C1Apb1lenrTim2en(val as u8)
18074 }
18075 #[doc = "HDMI-CEC peripheral clock enable"]
18076 pub fn set_cecen(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18077 self.0 = (self.0 & !(0x01 << 27usize)) | (((val.0 as u32) & 0x01) << 27usize);
18078 }
18079 #[doc = "DAC1&2 peripheral clock enable"]
18080 pub const fn dac12en(&self) -> super::vals::C1Apb1lenrTim2en {
18081 let val = (self.0 >> 29usize) & 0x01;
18082 super::vals::C1Apb1lenrTim2en(val as u8)
18083 }
18084 #[doc = "DAC1&2 peripheral clock enable"]
18085 pub fn set_dac12en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18086 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
18087 }
18088 #[doc = "UART7 Peripheral Clocks Enable"]
18089 pub const fn uart7en(&self) -> super::vals::C1Apb1lenrTim2en {
18090 let val = (self.0 >> 30usize) & 0x01;
18091 super::vals::C1Apb1lenrTim2en(val as u8)
18092 }
18093 #[doc = "UART7 Peripheral Clocks Enable"]
18094 pub fn set_uart7en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18095 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
18096 }
18097 #[doc = "UART8 Peripheral Clocks Enable"]
18098 pub const fn uart8en(&self) -> super::vals::C1Apb1lenrTim2en {
18099 let val = (self.0 >> 31usize) & 0x01;
18100 super::vals::C1Apb1lenrTim2en(val as u8)
18101 }
18102 #[doc = "UART8 Peripheral Clocks Enable"]
18103 pub fn set_uart8en(&mut self, val: super::vals::C1Apb1lenrTim2en) {
18104 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
18105 }
18106 }
18107 impl Default for C1Apb1lenr {
18108 fn default() -> C1Apb1lenr {
18109 C1Apb1lenr(0)
18110 }
18111 }
18112 #[doc = "RCC APB1 Clock Register"]
18113 #[repr(transparent)]
18114 #[derive(Copy, Clone, Eq, PartialEq)]
18115 pub struct Apb1lenr(pub u32);
18116 impl Apb1lenr {
18117 #[doc = "TIM peripheral clock enable"]
18118 pub const fn tim2en(&self) -> super::vals::Apb1lenrTim2en {
18119 let val = (self.0 >> 0usize) & 0x01;
18120 super::vals::Apb1lenrTim2en(val as u8)
18121 }
18122 #[doc = "TIM peripheral clock enable"]
18123 pub fn set_tim2en(&mut self, val: super::vals::Apb1lenrTim2en) {
18124 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
18125 }
18126 #[doc = "TIM peripheral clock enable"]
18127 pub const fn tim3en(&self) -> super::vals::Apb1lenrTim2en {
18128 let val = (self.0 >> 1usize) & 0x01;
18129 super::vals::Apb1lenrTim2en(val as u8)
18130 }
18131 #[doc = "TIM peripheral clock enable"]
18132 pub fn set_tim3en(&mut self, val: super::vals::Apb1lenrTim2en) {
18133 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
18134 }
18135 #[doc = "TIM peripheral clock enable"]
18136 pub const fn tim4en(&self) -> super::vals::Apb1lenrTim2en {
18137 let val = (self.0 >> 2usize) & 0x01;
18138 super::vals::Apb1lenrTim2en(val as u8)
18139 }
18140 #[doc = "TIM peripheral clock enable"]
18141 pub fn set_tim4en(&mut self, val: super::vals::Apb1lenrTim2en) {
18142 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
18143 }
18144 #[doc = "TIM peripheral clock enable"]
18145 pub const fn tim5en(&self) -> super::vals::Apb1lenrTim2en {
18146 let val = (self.0 >> 3usize) & 0x01;
18147 super::vals::Apb1lenrTim2en(val as u8)
18148 }
18149 #[doc = "TIM peripheral clock enable"]
18150 pub fn set_tim5en(&mut self, val: super::vals::Apb1lenrTim2en) {
18151 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
18152 }
18153 #[doc = "TIM peripheral clock enable"]
18154 pub const fn tim6en(&self) -> super::vals::Apb1lenrTim2en {
18155 let val = (self.0 >> 4usize) & 0x01;
18156 super::vals::Apb1lenrTim2en(val as u8)
18157 }
18158 #[doc = "TIM peripheral clock enable"]
18159 pub fn set_tim6en(&mut self, val: super::vals::Apb1lenrTim2en) {
18160 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
18161 }
18162 #[doc = "TIM peripheral clock enable"]
18163 pub const fn tim7en(&self) -> super::vals::Apb1lenrTim2en {
18164 let val = (self.0 >> 5usize) & 0x01;
18165 super::vals::Apb1lenrTim2en(val as u8)
18166 }
18167 #[doc = "TIM peripheral clock enable"]
18168 pub fn set_tim7en(&mut self, val: super::vals::Apb1lenrTim2en) {
18169 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
18170 }
18171 #[doc = "TIM peripheral clock enable"]
18172 pub const fn tim12en(&self) -> super::vals::Apb1lenrTim2en {
18173 let val = (self.0 >> 6usize) & 0x01;
18174 super::vals::Apb1lenrTim2en(val as u8)
18175 }
18176 #[doc = "TIM peripheral clock enable"]
18177 pub fn set_tim12en(&mut self, val: super::vals::Apb1lenrTim2en) {
18178 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
18179 }
18180 #[doc = "TIM peripheral clock enable"]
18181 pub const fn tim13en(&self) -> super::vals::Apb1lenrTim2en {
18182 let val = (self.0 >> 7usize) & 0x01;
18183 super::vals::Apb1lenrTim2en(val as u8)
18184 }
18185 #[doc = "TIM peripheral clock enable"]
18186 pub fn set_tim13en(&mut self, val: super::vals::Apb1lenrTim2en) {
18187 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
18188 }
18189 #[doc = "TIM peripheral clock enable"]
18190 pub const fn tim14en(&self) -> super::vals::Apb1lenrTim2en {
18191 let val = (self.0 >> 8usize) & 0x01;
18192 super::vals::Apb1lenrTim2en(val as u8)
18193 }
18194 #[doc = "TIM peripheral clock enable"]
18195 pub fn set_tim14en(&mut self, val: super::vals::Apb1lenrTim2en) {
18196 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
18197 }
18198 #[doc = "LPTIM1 Peripheral Clocks Enable"]
18199 pub const fn lptim1en(&self) -> super::vals::Apb1lenrTim2en {
18200 let val = (self.0 >> 9usize) & 0x01;
18201 super::vals::Apb1lenrTim2en(val as u8)
18202 }
18203 #[doc = "LPTIM1 Peripheral Clocks Enable"]
18204 pub fn set_lptim1en(&mut self, val: super::vals::Apb1lenrTim2en) {
18205 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
18206 }
18207 #[doc = "SPI2 Peripheral Clocks Enable"]
18208 pub const fn spi2en(&self) -> super::vals::Apb1lenrTim2en {
18209 let val = (self.0 >> 14usize) & 0x01;
18210 super::vals::Apb1lenrTim2en(val as u8)
18211 }
18212 #[doc = "SPI2 Peripheral Clocks Enable"]
18213 pub fn set_spi2en(&mut self, val: super::vals::Apb1lenrTim2en) {
18214 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
18215 }
18216 #[doc = "SPI3 Peripheral Clocks Enable"]
18217 pub const fn spi3en(&self) -> super::vals::Apb1lenrTim2en {
18218 let val = (self.0 >> 15usize) & 0x01;
18219 super::vals::Apb1lenrTim2en(val as u8)
18220 }
18221 #[doc = "SPI3 Peripheral Clocks Enable"]
18222 pub fn set_spi3en(&mut self, val: super::vals::Apb1lenrTim2en) {
18223 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
18224 }
18225 #[doc = "SPDIFRX Peripheral Clocks Enable"]
18226 pub const fn spdifrxen(&self) -> super::vals::Apb1lenrTim2en {
18227 let val = (self.0 >> 16usize) & 0x01;
18228 super::vals::Apb1lenrTim2en(val as u8)
18229 }
18230 #[doc = "SPDIFRX Peripheral Clocks Enable"]
18231 pub fn set_spdifrxen(&mut self, val: super::vals::Apb1lenrTim2en) {
18232 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
18233 }
18234 #[doc = "USART2 Peripheral Clocks Enable"]
18235 pub const fn usart2en(&self) -> super::vals::Apb1lenrTim2en {
18236 let val = (self.0 >> 17usize) & 0x01;
18237 super::vals::Apb1lenrTim2en(val as u8)
18238 }
18239 #[doc = "USART2 Peripheral Clocks Enable"]
18240 pub fn set_usart2en(&mut self, val: super::vals::Apb1lenrTim2en) {
18241 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
18242 }
18243 #[doc = "USART3 Peripheral Clocks Enable"]
18244 pub const fn usart3en(&self) -> super::vals::Apb1lenrTim2en {
18245 let val = (self.0 >> 18usize) & 0x01;
18246 super::vals::Apb1lenrTim2en(val as u8)
18247 }
18248 #[doc = "USART3 Peripheral Clocks Enable"]
18249 pub fn set_usart3en(&mut self, val: super::vals::Apb1lenrTim2en) {
18250 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
18251 }
18252 #[doc = "UART4 Peripheral Clocks Enable"]
18253 pub const fn uart4en(&self) -> super::vals::Apb1lenrTim2en {
18254 let val = (self.0 >> 19usize) & 0x01;
18255 super::vals::Apb1lenrTim2en(val as u8)
18256 }
18257 #[doc = "UART4 Peripheral Clocks Enable"]
18258 pub fn set_uart4en(&mut self, val: super::vals::Apb1lenrTim2en) {
18259 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
18260 }
18261 #[doc = "UART5 Peripheral Clocks Enable"]
18262 pub const fn uart5en(&self) -> super::vals::Apb1lenrTim2en {
18263 let val = (self.0 >> 20usize) & 0x01;
18264 super::vals::Apb1lenrTim2en(val as u8)
18265 }
18266 #[doc = "UART5 Peripheral Clocks Enable"]
18267 pub fn set_uart5en(&mut self, val: super::vals::Apb1lenrTim2en) {
18268 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.0 as u32) & 0x01) << 20usize);
18269 }
18270 #[doc = "I2C1 Peripheral Clocks Enable"]
18271 pub const fn i2c1en(&self) -> super::vals::Apb1lenrTim2en {
18272 let val = (self.0 >> 21usize) & 0x01;
18273 super::vals::Apb1lenrTim2en(val as u8)
18274 }
18275 #[doc = "I2C1 Peripheral Clocks Enable"]
18276 pub fn set_i2c1en(&mut self, val: super::vals::Apb1lenrTim2en) {
18277 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
18278 }
18279 #[doc = "I2C2 Peripheral Clocks Enable"]
18280 pub const fn i2c2en(&self) -> super::vals::Apb1lenrTim2en {
18281 let val = (self.0 >> 22usize) & 0x01;
18282 super::vals::Apb1lenrTim2en(val as u8)
18283 }
18284 #[doc = "I2C2 Peripheral Clocks Enable"]
18285 pub fn set_i2c2en(&mut self, val: super::vals::Apb1lenrTim2en) {
18286 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
18287 }
18288 #[doc = "I2C3 Peripheral Clocks Enable"]
18289 pub const fn i2c3en(&self) -> super::vals::Apb1lenrTim2en {
18290 let val = (self.0 >> 23usize) & 0x01;
18291 super::vals::Apb1lenrTim2en(val as u8)
18292 }
18293 #[doc = "I2C3 Peripheral Clocks Enable"]
18294 pub fn set_i2c3en(&mut self, val: super::vals::Apb1lenrTim2en) {
18295 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
18296 }
18297 #[doc = "HDMI-CEC peripheral clock enable"]
18298 pub const fn cecen(&self) -> super::vals::Apb1lenrTim2en {
18299 let val = (self.0 >> 27usize) & 0x01;
18300 super::vals::Apb1lenrTim2en(val as u8)
18301 }
18302 #[doc = "HDMI-CEC peripheral clock enable"]
18303 pub fn set_cecen(&mut self, val: super::vals::Apb1lenrTim2en) {
18304 self.0 = (self.0 & !(0x01 << 27usize)) | (((val.0 as u32) & 0x01) << 27usize);
18305 }
18306 #[doc = "DAC1&2 peripheral clock enable"]
18307 pub const fn dac12en(&self) -> super::vals::Apb1lenrTim2en {
18308 let val = (self.0 >> 29usize) & 0x01;
18309 super::vals::Apb1lenrTim2en(val as u8)
18310 }
18311 #[doc = "DAC1&2 peripheral clock enable"]
18312 pub fn set_dac12en(&mut self, val: super::vals::Apb1lenrTim2en) {
18313 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
18314 }
18315 #[doc = "UART7 Peripheral Clocks Enable"]
18316 pub const fn uart7en(&self) -> super::vals::Apb1lenrTim2en {
18317 let val = (self.0 >> 30usize) & 0x01;
18318 super::vals::Apb1lenrTim2en(val as u8)
18319 }
18320 #[doc = "UART7 Peripheral Clocks Enable"]
18321 pub fn set_uart7en(&mut self, val: super::vals::Apb1lenrTim2en) {
18322 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
18323 }
18324 #[doc = "UART8 Peripheral Clocks Enable"]
18325 pub const fn uart8en(&self) -> super::vals::Apb1lenrTim2en {
18326 let val = (self.0 >> 31usize) & 0x01;
18327 super::vals::Apb1lenrTim2en(val as u8)
18328 }
18329 #[doc = "UART8 Peripheral Clocks Enable"]
18330 pub fn set_uart8en(&mut self, val: super::vals::Apb1lenrTim2en) {
18331 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
18332 }
18333 }
18334 impl Default for Apb1lenr {
18335 fn default() -> Apb1lenr {
18336 Apb1lenr(0)
18337 }
18338 }
18339 #[doc = "RCC APB4 Clock Register"]
12191 #[repr(transparent)] 18340 #[repr(transparent)]
18341 #[derive(Copy, Clone, Eq, PartialEq)]
18342 pub struct Apb4enr(pub u32);
18343 impl Apb4enr {
18344 #[doc = "SYSCFG peripheral clock enable"]
18345 pub const fn syscfgen(&self) -> super::vals::Apb4enrSyscfgen {
18346 let val = (self.0 >> 1usize) & 0x01;
18347 super::vals::Apb4enrSyscfgen(val as u8)
18348 }
18349 #[doc = "SYSCFG peripheral clock enable"]
18350 pub fn set_syscfgen(&mut self, val: super::vals::Apb4enrSyscfgen) {
18351 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
18352 }
18353 #[doc = "LPUART1 Peripheral Clocks Enable"]
18354 pub const fn lpuart1en(&self) -> super::vals::Apb4enrSyscfgen {
18355 let val = (self.0 >> 3usize) & 0x01;
18356 super::vals::Apb4enrSyscfgen(val as u8)
18357 }
18358 #[doc = "LPUART1 Peripheral Clocks Enable"]
18359 pub fn set_lpuart1en(&mut self, val: super::vals::Apb4enrSyscfgen) {
18360 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
18361 }
18362 #[doc = "SPI6 Peripheral Clocks Enable"]
18363 pub const fn spi6en(&self) -> super::vals::Apb4enrSyscfgen {
18364 let val = (self.0 >> 5usize) & 0x01;
18365 super::vals::Apb4enrSyscfgen(val as u8)
18366 }
18367 #[doc = "SPI6 Peripheral Clocks Enable"]
18368 pub fn set_spi6en(&mut self, val: super::vals::Apb4enrSyscfgen) {
18369 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
18370 }
18371 #[doc = "I2C4 Peripheral Clocks Enable"]
18372 pub const fn i2c4en(&self) -> super::vals::Apb4enrSyscfgen {
18373 let val = (self.0 >> 7usize) & 0x01;
18374 super::vals::Apb4enrSyscfgen(val as u8)
18375 }
18376 #[doc = "I2C4 Peripheral Clocks Enable"]
18377 pub fn set_i2c4en(&mut self, val: super::vals::Apb4enrSyscfgen) {
18378 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
18379 }
18380 #[doc = "LPTIM2 Peripheral Clocks Enable"]
18381 pub const fn lptim2en(&self) -> super::vals::Apb4enrSyscfgen {
18382 let val = (self.0 >> 9usize) & 0x01;
18383 super::vals::Apb4enrSyscfgen(val as u8)
18384 }
18385 #[doc = "LPTIM2 Peripheral Clocks Enable"]
18386 pub fn set_lptim2en(&mut self, val: super::vals::Apb4enrSyscfgen) {
18387 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
18388 }
18389 #[doc = "LPTIM3 Peripheral Clocks Enable"]
18390 pub const fn lptim3en(&self) -> super::vals::Apb4enrSyscfgen {
18391 let val = (self.0 >> 10usize) & 0x01;
18392 super::vals::Apb4enrSyscfgen(val as u8)
18393 }
18394 #[doc = "LPTIM3 Peripheral Clocks Enable"]
18395 pub fn set_lptim3en(&mut self, val: super::vals::Apb4enrSyscfgen) {
18396 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
18397 }
18398 #[doc = "LPTIM4 Peripheral Clocks Enable"]
18399 pub const fn lptim4en(&self) -> super::vals::Apb4enrSyscfgen {
18400 let val = (self.0 >> 11usize) & 0x01;
18401 super::vals::Apb4enrSyscfgen(val as u8)
18402 }
18403 #[doc = "LPTIM4 Peripheral Clocks Enable"]
18404 pub fn set_lptim4en(&mut self, val: super::vals::Apb4enrSyscfgen) {
18405 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
18406 }
18407 #[doc = "LPTIM5 Peripheral Clocks Enable"]
18408 pub const fn lptim5en(&self) -> super::vals::Apb4enrSyscfgen {
18409 let val = (self.0 >> 12usize) & 0x01;
18410 super::vals::Apb4enrSyscfgen(val as u8)
18411 }
18412 #[doc = "LPTIM5 Peripheral Clocks Enable"]
18413 pub fn set_lptim5en(&mut self, val: super::vals::Apb4enrSyscfgen) {
18414 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
18415 }
18416 #[doc = "COMP1/2 peripheral clock enable"]
18417 pub const fn comp12en(&self) -> super::vals::Apb4enrSyscfgen {
18418 let val = (self.0 >> 14usize) & 0x01;
18419 super::vals::Apb4enrSyscfgen(val as u8)
18420 }
18421 #[doc = "COMP1/2 peripheral clock enable"]
18422 pub fn set_comp12en(&mut self, val: super::vals::Apb4enrSyscfgen) {
18423 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
18424 }
18425 #[doc = "VREF peripheral clock enable"]
18426 pub const fn vrefen(&self) -> super::vals::Apb4enrSyscfgen {
18427 let val = (self.0 >> 15usize) & 0x01;
18428 super::vals::Apb4enrSyscfgen(val as u8)
18429 }
18430 #[doc = "VREF peripheral clock enable"]
18431 pub fn set_vrefen(&mut self, val: super::vals::Apb4enrSyscfgen) {
18432 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
18433 }
18434 #[doc = "RTC APB Clock Enable"]
18435 pub const fn rtcapben(&self) -> super::vals::Apb4enrSyscfgen {
18436 let val = (self.0 >> 16usize) & 0x01;
18437 super::vals::Apb4enrSyscfgen(val as u8)
18438 }
18439 #[doc = "RTC APB Clock Enable"]
18440 pub fn set_rtcapben(&mut self, val: super::vals::Apb4enrSyscfgen) {
18441 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
18442 }
18443 #[doc = "SAI4 Peripheral Clocks Enable"]
18444 pub const fn sai4en(&self) -> super::vals::Apb4enrSyscfgen {
18445 let val = (self.0 >> 21usize) & 0x01;
18446 super::vals::Apb4enrSyscfgen(val as u8)
18447 }
18448 #[doc = "SAI4 Peripheral Clocks Enable"]
18449 pub fn set_sai4en(&mut self, val: super::vals::Apb4enrSyscfgen) {
18450 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
18451 }
18452 }
18453 impl Default for Apb4enr {
18454 fn default() -> Apb4enr {
18455 Apb4enr(0)
18456 }
18457 }
18458 #[doc = "RCC AHB1 Sleep Clock Register"]
18459 #[repr(transparent)]
18460 #[derive(Copy, Clone, Eq, PartialEq)]
18461 pub struct Ahb1lpenr(pub u32);
18462 impl Ahb1lpenr {
18463 #[doc = "DMA1 Clock Enable During CSleep Mode"]
18464 pub const fn dma1lpen(&self) -> super::vals::Ahb1lpenrDma1lpen {
18465 let val = (self.0 >> 0usize) & 0x01;
18466 super::vals::Ahb1lpenrDma1lpen(val as u8)
18467 }
18468 #[doc = "DMA1 Clock Enable During CSleep Mode"]
18469 pub fn set_dma1lpen(&mut self, val: super::vals::Ahb1lpenrDma1lpen) {
18470 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
18471 }
18472 #[doc = "DMA2 Clock Enable During CSleep Mode"]
18473 pub const fn dma2lpen(&self) -> super::vals::Ahb1lpenrDma1lpen {
18474 let val = (self.0 >> 1usize) & 0x01;
18475 super::vals::Ahb1lpenrDma1lpen(val as u8)
18476 }
18477 #[doc = "DMA2 Clock Enable During CSleep Mode"]
18478 pub fn set_dma2lpen(&mut self, val: super::vals::Ahb1lpenrDma1lpen) {
18479 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
18480 }
18481 #[doc = "ADC1/2 Peripheral Clocks Enable During CSleep Mode"]
18482 pub const fn adc12lpen(&self) -> super::vals::Ahb1lpenrDma1lpen {
18483 let val = (self.0 >> 5usize) & 0x01;
18484 super::vals::Ahb1lpenrDma1lpen(val as u8)
18485 }
18486 #[doc = "ADC1/2 Peripheral Clocks Enable During CSleep Mode"]
18487 pub fn set_adc12lpen(&mut self, val: super::vals::Ahb1lpenrDma1lpen) {
18488 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
18489 }
18490 #[doc = "Ethernet MAC bus interface Clock Enable During CSleep Mode"]
18491 pub const fn eth1maclpen(&self) -> super::vals::Ahb1lpenrDma1lpen {
18492 let val = (self.0 >> 15usize) & 0x01;
18493 super::vals::Ahb1lpenrDma1lpen(val as u8)
18494 }
18495 #[doc = "Ethernet MAC bus interface Clock Enable During CSleep Mode"]
18496 pub fn set_eth1maclpen(&mut self, val: super::vals::Ahb1lpenrDma1lpen) {
18497 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
18498 }
18499 #[doc = "Ethernet Transmission Clock Enable During CSleep Mode"]
18500 pub const fn eth1txlpen(&self) -> super::vals::Ahb1lpenrDma1lpen {
18501 let val = (self.0 >> 16usize) & 0x01;
18502 super::vals::Ahb1lpenrDma1lpen(val as u8)
18503 }
18504 #[doc = "Ethernet Transmission Clock Enable During CSleep Mode"]
18505 pub fn set_eth1txlpen(&mut self, val: super::vals::Ahb1lpenrDma1lpen) {
18506 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
18507 }
18508 #[doc = "Ethernet Reception Clock Enable During CSleep Mode"]
18509 pub const fn eth1rxlpen(&self) -> super::vals::Ahb1lpenrDma1lpen {
18510 let val = (self.0 >> 17usize) & 0x01;
18511 super::vals::Ahb1lpenrDma1lpen(val as u8)
18512 }
18513 #[doc = "Ethernet Reception Clock Enable During CSleep Mode"]
18514 pub fn set_eth1rxlpen(&mut self, val: super::vals::Ahb1lpenrDma1lpen) {
18515 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
18516 }
18517 #[doc = "USB1OTG peripheral clock enable during CSleep mode"]
18518 pub const fn usb1otglpen(&self) -> super::vals::Ahb1lpenrDma1lpen {
18519 let val = (self.0 >> 25usize) & 0x01;
18520 super::vals::Ahb1lpenrDma1lpen(val as u8)
18521 }
18522 #[doc = "USB1OTG peripheral clock enable during CSleep mode"]
18523 pub fn set_usb1otglpen(&mut self, val: super::vals::Ahb1lpenrDma1lpen) {
18524 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.0 as u32) & 0x01) << 25usize);
18525 }
18526 #[doc = "USB_PHY1 clock enable during CSleep mode"]
18527 pub const fn usb1otghsulpilpen(&self) -> super::vals::Ahb1lpenrDma1lpen {
18528 let val = (self.0 >> 26usize) & 0x01;
18529 super::vals::Ahb1lpenrDma1lpen(val as u8)
18530 }
18531 #[doc = "USB_PHY1 clock enable during CSleep mode"]
18532 pub fn set_usb1otghsulpilpen(&mut self, val: super::vals::Ahb1lpenrDma1lpen) {
18533 self.0 = (self.0 & !(0x01 << 26usize)) | (((val.0 as u32) & 0x01) << 26usize);
18534 }
18535 #[doc = "USB2OTG peripheral clock enable during CSleep mode"]
18536 pub const fn usb2otglpen(&self) -> super::vals::Ahb1lpenrDma1lpen {
18537 let val = (self.0 >> 27usize) & 0x01;
18538 super::vals::Ahb1lpenrDma1lpen(val as u8)
18539 }
18540 #[doc = "USB2OTG peripheral clock enable during CSleep mode"]
18541 pub fn set_usb2otglpen(&mut self, val: super::vals::Ahb1lpenrDma1lpen) {
18542 self.0 = (self.0 & !(0x01 << 27usize)) | (((val.0 as u32) & 0x01) << 27usize);
18543 }
18544 #[doc = "USB_PHY2 clocks enable during CSleep mode"]
18545 pub const fn usb2otghsulpilpen(&self) -> super::vals::Ahb1lpenrDma1lpen {
18546 let val = (self.0 >> 28usize) & 0x01;
18547 super::vals::Ahb1lpenrDma1lpen(val as u8)
18548 }
18549 #[doc = "USB_PHY2 clocks enable during CSleep mode"]
18550 pub fn set_usb2otghsulpilpen(&mut self, val: super::vals::Ahb1lpenrDma1lpen) {
18551 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
18552 }
18553 }
18554 impl Default for Ahb1lpenr {
18555 fn default() -> Ahb1lpenr {
18556 Ahb1lpenr(0)
18557 }
18558 }
18559 #[doc = "RCC AHB1 Clock Register"]
18560 #[repr(transparent)]
18561 #[derive(Copy, Clone, Eq, PartialEq)]
18562 pub struct Ahb1enr(pub u32);
18563 impl Ahb1enr {
18564 #[doc = "DMA1 Clock Enable"]
18565 pub const fn dma1en(&self) -> super::vals::Ahb1enrDma1en {
18566 let val = (self.0 >> 0usize) & 0x01;
18567 super::vals::Ahb1enrDma1en(val as u8)
18568 }
18569 #[doc = "DMA1 Clock Enable"]
18570 pub fn set_dma1en(&mut self, val: super::vals::Ahb1enrDma1en) {
18571 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
18572 }
18573 #[doc = "DMA2 Clock Enable"]
18574 pub const fn dma2en(&self) -> super::vals::Ahb1enrDma1en {
18575 let val = (self.0 >> 1usize) & 0x01;
18576 super::vals::Ahb1enrDma1en(val as u8)
18577 }
18578 #[doc = "DMA2 Clock Enable"]
18579 pub fn set_dma2en(&mut self, val: super::vals::Ahb1enrDma1en) {
18580 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
18581 }
18582 #[doc = "ADC1/2 Peripheral Clocks Enable"]
18583 pub const fn adc12en(&self) -> super::vals::Ahb1enrDma1en {
18584 let val = (self.0 >> 5usize) & 0x01;
18585 super::vals::Ahb1enrDma1en(val as u8)
18586 }
18587 #[doc = "ADC1/2 Peripheral Clocks Enable"]
18588 pub fn set_adc12en(&mut self, val: super::vals::Ahb1enrDma1en) {
18589 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
18590 }
18591 #[doc = "Ethernet MAC bus interface Clock Enable"]
18592 pub const fn eth1macen(&self) -> super::vals::Ahb1enrDma1en {
18593 let val = (self.0 >> 15usize) & 0x01;
18594 super::vals::Ahb1enrDma1en(val as u8)
18595 }
18596 #[doc = "Ethernet MAC bus interface Clock Enable"]
18597 pub fn set_eth1macen(&mut self, val: super::vals::Ahb1enrDma1en) {
18598 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
18599 }
18600 #[doc = "Ethernet Transmission Clock Enable"]
18601 pub const fn eth1txen(&self) -> super::vals::Ahb1enrDma1en {
18602 let val = (self.0 >> 16usize) & 0x01;
18603 super::vals::Ahb1enrDma1en(val as u8)
18604 }
18605 #[doc = "Ethernet Transmission Clock Enable"]
18606 pub fn set_eth1txen(&mut self, val: super::vals::Ahb1enrDma1en) {
18607 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
18608 }
18609 #[doc = "Ethernet Reception Clock Enable"]
18610 pub const fn eth1rxen(&self) -> super::vals::Ahb1enrDma1en {
18611 let val = (self.0 >> 17usize) & 0x01;
18612 super::vals::Ahb1enrDma1en(val as u8)
18613 }
18614 #[doc = "Ethernet Reception Clock Enable"]
18615 pub fn set_eth1rxen(&mut self, val: super::vals::Ahb1enrDma1en) {
18616 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
18617 }
18618 #[doc = "Enable USB_PHY2 clocks"]
18619 pub const fn usb2otghsulpien(&self) -> super::vals::Ahb1enrDma1en {
18620 let val = (self.0 >> 18usize) & 0x01;
18621 super::vals::Ahb1enrDma1en(val as u8)
18622 }
18623 #[doc = "Enable USB_PHY2 clocks"]
18624 pub fn set_usb2otghsulpien(&mut self, val: super::vals::Ahb1enrDma1en) {
18625 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
18626 }
18627 #[doc = "USB1OTG Peripheral Clocks Enable"]
18628 pub const fn usb1otgen(&self) -> super::vals::Ahb1enrDma1en {
18629 let val = (self.0 >> 25usize) & 0x01;
18630 super::vals::Ahb1enrDma1en(val as u8)
18631 }
18632 #[doc = "USB1OTG Peripheral Clocks Enable"]
18633 pub fn set_usb1otgen(&mut self, val: super::vals::Ahb1enrDma1en) {
18634 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.0 as u32) & 0x01) << 25usize);
18635 }
18636 #[doc = "USB_PHY1 Clocks Enable"]
18637 pub const fn usb1ulpien(&self) -> super::vals::Ahb1enrDma1en {
18638 let val = (self.0 >> 26usize) & 0x01;
18639 super::vals::Ahb1enrDma1en(val as u8)
18640 }
18641 #[doc = "USB_PHY1 Clocks Enable"]
18642 pub fn set_usb1ulpien(&mut self, val: super::vals::Ahb1enrDma1en) {
18643 self.0 = (self.0 & !(0x01 << 26usize)) | (((val.0 as u32) & 0x01) << 26usize);
18644 }
18645 #[doc = "USB2OTG Peripheral Clocks Enable"]
18646 pub const fn usb2otgen(&self) -> super::vals::Ahb1enrDma1en {
18647 let val = (self.0 >> 27usize) & 0x01;
18648 super::vals::Ahb1enrDma1en(val as u8)
18649 }
18650 #[doc = "USB2OTG Peripheral Clocks Enable"]
18651 pub fn set_usb2otgen(&mut self, val: super::vals::Ahb1enrDma1en) {
18652 self.0 = (self.0 & !(0x01 << 27usize)) | (((val.0 as u32) & 0x01) << 27usize);
18653 }
18654 #[doc = "USB_PHY2 Clocks Enable"]
18655 pub const fn usb2ulpien(&self) -> super::vals::Ahb1enrDma1en {
18656 let val = (self.0 >> 28usize) & 0x01;
18657 super::vals::Ahb1enrDma1en(val as u8)
18658 }
18659 #[doc = "USB_PHY2 Clocks Enable"]
18660 pub fn set_usb2ulpien(&mut self, val: super::vals::Ahb1enrDma1en) {
18661 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
18662 }
18663 }
18664 impl Default for Ahb1enr {
18665 fn default() -> Ahb1enr {
18666 Ahb1enr(0)
18667>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
18668 }
18669 }
18670 #[doc = "RCC AHB3 Clock Register"]
18671 #[repr(transparent)]
18672<<<<<<< HEAD
12192 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 18673 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
12193 pub struct Msirange(pub u8); 18674 pub struct Msirange(pub u8);
12194 impl Msirange { 18675 impl Msirange {
@@ -12217,8 +18698,74 @@ pub mod rcc_l0 {
12217 pub const NOTREADY: Self = Self(0); 18698 pub const NOTREADY: Self = Self(0);
12218 #[doc = "Oscillator is stable"] 18699 #[doc = "Oscillator is stable"]
12219 pub const READY: Self = Self(0x01); 18700 pub const READY: Self = Self(0x01);
18701=======
18702 #[derive(Copy, Clone, Eq, PartialEq)]
18703 pub struct C1Ahb3enr(pub u32);
18704 impl C1Ahb3enr {
18705 #[doc = "MDMA Peripheral Clock Enable"]
18706 pub const fn mdmaen(&self) -> super::vals::C1Ahb3enrMdmaen {
18707 let val = (self.0 >> 0usize) & 0x01;
18708 super::vals::C1Ahb3enrMdmaen(val as u8)
18709 }
18710 #[doc = "MDMA Peripheral Clock Enable"]
18711 pub fn set_mdmaen(&mut self, val: super::vals::C1Ahb3enrMdmaen) {
18712 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
18713 }
18714 #[doc = "DMA2D Peripheral Clock Enable"]
18715 pub const fn dma2den(&self) -> super::vals::C1Ahb3enrMdmaen {
18716 let val = (self.0 >> 4usize) & 0x01;
18717 super::vals::C1Ahb3enrMdmaen(val as u8)
18718 }
18719 #[doc = "DMA2D Peripheral Clock Enable"]
18720 pub fn set_dma2den(&mut self, val: super::vals::C1Ahb3enrMdmaen) {
18721 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
18722 }
18723 #[doc = "JPGDEC Peripheral Clock Enable"]
18724 pub const fn jpgdecen(&self) -> super::vals::C1Ahb3enrMdmaen {
18725 let val = (self.0 >> 5usize) & 0x01;
18726 super::vals::C1Ahb3enrMdmaen(val as u8)
18727 }
18728 #[doc = "JPGDEC Peripheral Clock Enable"]
18729 pub fn set_jpgdecen(&mut self, val: super::vals::C1Ahb3enrMdmaen) {
18730 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
18731 }
18732 #[doc = "FMC Peripheral Clocks Enable"]
18733 pub const fn fmcen(&self) -> super::vals::C1Ahb3enrMdmaen {
18734 let val = (self.0 >> 12usize) & 0x01;
18735 super::vals::C1Ahb3enrMdmaen(val as u8)
18736 }
18737 #[doc = "FMC Peripheral Clocks Enable"]
18738 pub fn set_fmcen(&mut self, val: super::vals::C1Ahb3enrMdmaen) {
18739 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
18740 }
18741 #[doc = "QUADSPI and QUADSPI Delay Clock Enable"]
18742 pub const fn qspien(&self) -> super::vals::C1Ahb3enrMdmaen {
18743 let val = (self.0 >> 14usize) & 0x01;
18744 super::vals::C1Ahb3enrMdmaen(val as u8)
18745 }
18746 #[doc = "QUADSPI and QUADSPI Delay Clock Enable"]
18747 pub fn set_qspien(&mut self, val: super::vals::C1Ahb3enrMdmaen) {
18748 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
18749 }
18750 #[doc = "SDMMC1 and SDMMC1 Delay Clock Enable"]
18751 pub const fn sdmmc1en(&self) -> super::vals::C1Ahb3enrMdmaen {
18752 let val = (self.0 >> 16usize) & 0x01;
18753 super::vals::C1Ahb3enrMdmaen(val as u8)
18754 }
18755 #[doc = "SDMMC1 and SDMMC1 Delay Clock Enable"]
18756 pub fn set_sdmmc1en(&mut self, val: super::vals::C1Ahb3enrMdmaen) {
18757 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
18758 }
18759 }
18760 impl Default for C1Ahb3enr {
18761 fn default() -> C1Ahb3enr {
18762 C1Ahb3enr(0)
18763 }
18764>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
12220 } 18765 }
18766 #[doc = "RCC Backup Domain Control Register"]
12221 #[repr(transparent)] 18767 #[repr(transparent)]
18768<<<<<<< HEAD
12222 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 18769 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
12223 pub struct Crcsmen(pub u8); 18770 pub struct Crcsmen(pub u8);
12224 impl Crcsmen { 18771 impl Crcsmen {
@@ -12233,8 +18780,101 @@ pub mod rcc_l0 {
12233 impl Cryprstw { 18780 impl Cryprstw {
12234 #[doc = "Reset the module"] 18781 #[doc = "Reset the module"]
12235 pub const RESET: Self = Self(0x01); 18782 pub const RESET: Self = Self(0x01);
18783=======
18784 #[derive(Copy, Clone, Eq, PartialEq)]
18785 pub struct Bdcr(pub u32);
18786 impl Bdcr {
18787 #[doc = "LSE oscillator enabled"]
18788 pub const fn lseon(&self) -> super::vals::Lseon {
18789 let val = (self.0 >> 0usize) & 0x01;
18790 super::vals::Lseon(val as u8)
18791 }
18792 #[doc = "LSE oscillator enabled"]
18793 pub fn set_lseon(&mut self, val: super::vals::Lseon) {
18794 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
18795 }
18796 #[doc = "LSE oscillator ready"]
18797 pub const fn lserdy(&self) -> bool {
18798 let val = (self.0 >> 1usize) & 0x01;
18799 val != 0
18800 }
18801 #[doc = "LSE oscillator ready"]
18802 pub fn set_lserdy(&mut self, val: bool) {
18803 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
18804 }
18805 #[doc = "LSE oscillator bypass"]
18806 pub const fn lsebyp(&self) -> super::vals::Lsebyp {
18807 let val = (self.0 >> 2usize) & 0x01;
18808 super::vals::Lsebyp(val as u8)
18809 }
18810 #[doc = "LSE oscillator bypass"]
18811 pub fn set_lsebyp(&mut self, val: super::vals::Lsebyp) {
18812 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
18813 }
18814 #[doc = "LSE oscillator driving capability"]
18815 pub const fn lsedrv(&self) -> super::vals::Lsedrv {
18816 let val = (self.0 >> 3usize) & 0x03;
18817 super::vals::Lsedrv(val as u8)
18818 }
18819 #[doc = "LSE oscillator driving capability"]
18820 pub fn set_lsedrv(&mut self, val: super::vals::Lsedrv) {
18821 self.0 = (self.0 & !(0x03 << 3usize)) | (((val.0 as u32) & 0x03) << 3usize);
18822 }
18823 #[doc = "LSE clock security system enable"]
18824 pub const fn lsecsson(&self) -> super::vals::Lsecsson {
18825 let val = (self.0 >> 5usize) & 0x01;
18826 super::vals::Lsecsson(val as u8)
18827 }
18828 #[doc = "LSE clock security system enable"]
18829 pub fn set_lsecsson(&mut self, val: super::vals::Lsecsson) {
18830 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
18831 }
18832 #[doc = "LSE clock security system failure detection"]
18833 pub const fn lsecssd(&self) -> bool {
18834 let val = (self.0 >> 6usize) & 0x01;
18835 val != 0
18836 }
18837 #[doc = "LSE clock security system failure detection"]
18838 pub fn set_lsecssd(&mut self, val: bool) {
18839 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
18840 }
18841 #[doc = "RTC clock source selection"]
18842 pub const fn rtcsel(&self) -> super::vals::Rtcsel {
18843 let val = (self.0 >> 8usize) & 0x03;
18844 super::vals::Rtcsel(val as u8)
18845 }
18846 #[doc = "RTC clock source selection"]
18847 pub fn set_rtcsel(&mut self, val: super::vals::Rtcsel) {
18848 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
18849 }
18850 #[doc = "RTC clock enable"]
18851 pub const fn rtcen(&self) -> super::vals::Rtcen {
18852 let val = (self.0 >> 15usize) & 0x01;
18853 super::vals::Rtcen(val as u8)
18854 }
18855 #[doc = "RTC clock enable"]
18856 pub fn set_rtcen(&mut self, val: super::vals::Rtcen) {
18857 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
18858 }
18859 #[doc = "VSwitch domain software reset"]
18860 pub const fn bdrst(&self) -> super::vals::Bdrst {
18861 let val = (self.0 >> 16usize) & 0x01;
18862 super::vals::Bdrst(val as u8)
18863 }
18864 #[doc = "VSwitch domain software reset"]
18865 pub fn set_bdrst(&mut self, val: super::vals::Bdrst) {
18866 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
18867 }
12236 } 18868 }
18869 impl Default for Bdcr {
18870 fn default() -> Bdcr {
18871 Bdcr(0)
18872 }
18873>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
18874 }
18875 #[doc = "RCC AHB2 Sleep Clock Register"]
12237 #[repr(transparent)] 18876 #[repr(transparent)]
18877<<<<<<< HEAD
12238 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 18878 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
12239 pub struct Dbgrstw(pub u8); 18879 pub struct Dbgrstw(pub u8);
12240 impl Dbgrstw { 18880 impl Dbgrstw {
@@ -12289,15 +18929,147 @@ pub mod rcc_l0 {
12289 pub const DIV8: Self = Self(0x02); 18929 pub const DIV8: Self = Self(0x02);
12290 #[doc = "HSE divided by 16"] 18930 #[doc = "HSE divided by 16"]
12291 pub const DIV16: Self = Self(0x03); 18931 pub const DIV16: Self = Self(0x03);
18932=======
18933 #[derive(Copy, Clone, Eq, PartialEq)]
18934 pub struct Ahb2lpenr(pub u32);
18935 impl Ahb2lpenr {
18936 #[doc = "DCMI peripheral clock enable during csleep mode"]
18937 pub const fn dcmilpen(&self) -> super::vals::Ahb2lpenrDcmilpen {
18938 let val = (self.0 >> 0usize) & 0x01;
18939 super::vals::Ahb2lpenrDcmilpen(val as u8)
18940 }
18941 #[doc = "DCMI peripheral clock enable during csleep mode"]
18942 pub fn set_dcmilpen(&mut self, val: super::vals::Ahb2lpenrDcmilpen) {
18943 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
18944 }
18945 #[doc = "CRYPT peripheral clock enable during CSleep mode"]
18946 pub const fn cryptlpen(&self) -> super::vals::Ahb2lpenrDcmilpen {
18947 let val = (self.0 >> 4usize) & 0x01;
18948 super::vals::Ahb2lpenrDcmilpen(val as u8)
18949 }
18950 #[doc = "CRYPT peripheral clock enable during CSleep mode"]
18951 pub fn set_cryptlpen(&mut self, val: super::vals::Ahb2lpenrDcmilpen) {
18952 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
18953 }
18954 #[doc = "HASH peripheral clock enable during CSleep mode"]
18955 pub const fn hashlpen(&self) -> super::vals::Ahb2lpenrDcmilpen {
18956 let val = (self.0 >> 5usize) & 0x01;
18957 super::vals::Ahb2lpenrDcmilpen(val as u8)
18958 }
18959 #[doc = "HASH peripheral clock enable during CSleep mode"]
18960 pub fn set_hashlpen(&mut self, val: super::vals::Ahb2lpenrDcmilpen) {
18961 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
18962 }
18963 #[doc = "RNG peripheral clock enable during CSleep mode"]
18964 pub const fn rnglpen(&self) -> super::vals::Ahb2lpenrDcmilpen {
18965 let val = (self.0 >> 6usize) & 0x01;
18966 super::vals::Ahb2lpenrDcmilpen(val as u8)
18967 }
18968 #[doc = "RNG peripheral clock enable during CSleep mode"]
18969 pub fn set_rnglpen(&mut self, val: super::vals::Ahb2lpenrDcmilpen) {
18970 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
18971 }
18972 #[doc = "SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode"]
18973 pub const fn sdmmc2lpen(&self) -> super::vals::Ahb2lpenrDcmilpen {
18974 let val = (self.0 >> 9usize) & 0x01;
18975 super::vals::Ahb2lpenrDcmilpen(val as u8)
18976 }
18977 #[doc = "SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode"]
18978 pub fn set_sdmmc2lpen(&mut self, val: super::vals::Ahb2lpenrDcmilpen) {
18979 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
18980 }
18981 #[doc = "SRAM1 Clock Enable During CSleep Mode"]
18982 pub const fn sram1lpen(&self) -> super::vals::Ahb2lpenrDcmilpen {
18983 let val = (self.0 >> 29usize) & 0x01;
18984 super::vals::Ahb2lpenrDcmilpen(val as u8)
18985 }
18986 #[doc = "SRAM1 Clock Enable During CSleep Mode"]
18987 pub fn set_sram1lpen(&mut self, val: super::vals::Ahb2lpenrDcmilpen) {
18988 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
18989 }
18990 #[doc = "SRAM2 Clock Enable During CSleep Mode"]
18991 pub const fn sram2lpen(&self) -> super::vals::Ahb2lpenrDcmilpen {
18992 let val = (self.0 >> 30usize) & 0x01;
18993 super::vals::Ahb2lpenrDcmilpen(val as u8)
18994 }
18995 #[doc = "SRAM2 Clock Enable During CSleep Mode"]
18996 pub fn set_sram2lpen(&mut self, val: super::vals::Ahb2lpenrDcmilpen) {
18997 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
18998 }
18999 #[doc = "SRAM3 Clock Enable During CSleep Mode"]
19000 pub const fn sram3lpen(&self) -> super::vals::Ahb2lpenrDcmilpen {
19001 let val = (self.0 >> 31usize) & 0x01;
19002 super::vals::Ahb2lpenrDcmilpen(val as u8)
19003 }
19004 #[doc = "SRAM3 Clock Enable During CSleep Mode"]
19005 pub fn set_sram3lpen(&mut self, val: super::vals::Ahb2lpenrDcmilpen) {
19006 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
19007 }
19008 }
19009 impl Default for Ahb2lpenr {
19010 fn default() -> Ahb2lpenr {
19011 Ahb2lpenr(0)
19012 }
19013>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
12292 } 19014 }
19015 #[doc = "RCC PLL3 Dividers Configuration Register"]
12293 #[repr(transparent)] 19016 #[repr(transparent)]
19017<<<<<<< HEAD
12294 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 19018 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
12295 pub struct Csshsecw(pub u8); 19019 pub struct Csshsecw(pub u8);
12296 impl Csshsecw { 19020 impl Csshsecw {
12297 #[doc = "Clear interrupt flag"] 19021 #[doc = "Clear interrupt flag"]
12298 pub const CLEAR: Self = Self(0x01); 19022 pub const CLEAR: Self = Self(0x01);
19023=======
19024 #[derive(Copy, Clone, Eq, PartialEq)]
19025 pub struct Pll3divr(pub u32);
19026 impl Pll3divr {
19027 #[doc = "Multiplication factor for PLL1 VCO"]
19028 pub const fn divn3(&self) -> u16 {
19029 let val = (self.0 >> 0usize) & 0x01ff;
19030 val as u16
19031 }
19032 #[doc = "Multiplication factor for PLL1 VCO"]
19033 pub fn set_divn3(&mut self, val: u16) {
19034 self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
19035 }
19036 #[doc = "PLL DIVP division factor"]
19037 pub const fn divp3(&self) -> u8 {
19038 let val = (self.0 >> 9usize) & 0x7f;
19039 val as u8
19040 }
19041 #[doc = "PLL DIVP division factor"]
19042 pub fn set_divp3(&mut self, val: u8) {
19043 self.0 = (self.0 & !(0x7f << 9usize)) | (((val as u32) & 0x7f) << 9usize);
19044 }
19045 #[doc = "PLL DIVQ division factor"]
19046 pub const fn divq3(&self) -> u8 {
19047 let val = (self.0 >> 16usize) & 0x7f;
19048 val as u8
19049 }
19050 #[doc = "PLL DIVQ division factor"]
19051 pub fn set_divq3(&mut self, val: u8) {
19052 self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
19053 }
19054 #[doc = "PLL DIVR division factor"]
19055 pub const fn divr3(&self) -> u8 {
19056 let val = (self.0 >> 24usize) & 0x7f;
19057 val as u8
19058 }
19059 #[doc = "PLL DIVR division factor"]
19060 pub fn set_divr3(&mut self, val: u8) {
19061 self.0 = (self.0 & !(0x7f << 24usize)) | (((val as u32) & 0x7f) << 24usize);
19062 }
12299 } 19063 }
19064 impl Default for Pll3divr {
19065 fn default() -> Pll3divr {
19066 Pll3divr(0)
19067 }
19068>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
19069 }
19070 #[doc = "RCC APB3 Sleep Clock Register"]
12300 #[repr(transparent)] 19071 #[repr(transparent)]
19072<<<<<<< HEAD
12301 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 19073 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
12302 pub struct Csslsef(pub u8); 19074 pub struct Csslsef(pub u8);
12303 impl Csslsef { 19075 impl Csslsef {
@@ -12305,8 +19077,38 @@ pub mod rcc_l0 {
12305 pub const NOFAILURE: Self = Self(0); 19077 pub const NOFAILURE: Self = Self(0);
12306 #[doc = "Failure detected on LSE clock failure"] 19078 #[doc = "Failure detected on LSE clock failure"]
12307 pub const FAILURE: Self = Self(0x01); 19079 pub const FAILURE: Self = Self(0x01);
19080=======
19081 #[derive(Copy, Clone, Eq, PartialEq)]
19082 pub struct Apb3lpenr(pub u32);
19083 impl Apb3lpenr {
19084 #[doc = "LTDC peripheral clock enable during CSleep mode"]
19085 pub const fn ltdclpen(&self) -> super::vals::Apb3lpenrLtdclpen {
19086 let val = (self.0 >> 3usize) & 0x01;
19087 super::vals::Apb3lpenrLtdclpen(val as u8)
19088 }
19089 #[doc = "LTDC peripheral clock enable during CSleep mode"]
19090 pub fn set_ltdclpen(&mut self, val: super::vals::Apb3lpenrLtdclpen) {
19091 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
19092 }
19093 #[doc = "WWDG1 Clock Enable During CSleep Mode"]
19094 pub const fn wwdg1lpen(&self) -> super::vals::Apb3lpenrLtdclpen {
19095 let val = (self.0 >> 6usize) & 0x01;
19096 super::vals::Apb3lpenrLtdclpen(val as u8)
19097 }
19098 #[doc = "WWDG1 Clock Enable During CSleep Mode"]
19099 pub fn set_wwdg1lpen(&mut self, val: super::vals::Apb3lpenrLtdclpen) {
19100 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
19101 }
19102 }
19103 impl Default for Apb3lpenr {
19104 fn default() -> Apb3lpenr {
19105 Apb3lpenr(0)
19106 }
19107>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
12308 } 19108 }
19109 #[doc = "RCC AHB3 Sleep Clock Register"]
12309 #[repr(transparent)] 19110 #[repr(transparent)]
19111<<<<<<< HEAD
12310 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 19112 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
12311 pub struct Csslsed(pub u8); 19113 pub struct Csslsed(pub u8);
12312 impl Csslsed { 19114 impl Csslsed {
@@ -12323,8 +19125,119 @@ pub mod rcc_l0 {
12323 pub const DISABLED: Self = Self(0); 19125 pub const DISABLED: Self = Self(0);
12324 #[doc = "Clock enabled"] 19126 #[doc = "Clock enabled"]
12325 pub const ENABLED: Self = Self(0x01); 19127 pub const ENABLED: Self = Self(0x01);
19128=======
19129 #[derive(Copy, Clone, Eq, PartialEq)]
19130 pub struct Ahb3lpenr(pub u32);
19131 impl Ahb3lpenr {
19132 #[doc = "MDMA Clock Enable During CSleep Mode"]
19133 pub const fn mdmalpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19134 let val = (self.0 >> 0usize) & 0x01;
19135 super::vals::Ahb3lpenrMdmalpen(val as u8)
19136 }
19137 #[doc = "MDMA Clock Enable During CSleep Mode"]
19138 pub fn set_mdmalpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19139 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
19140 }
19141 #[doc = "DMA2D Clock Enable During CSleep Mode"]
19142 pub const fn dma2dlpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19143 let val = (self.0 >> 4usize) & 0x01;
19144 super::vals::Ahb3lpenrMdmalpen(val as u8)
19145 }
19146 #[doc = "DMA2D Clock Enable During CSleep Mode"]
19147 pub fn set_dma2dlpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19148 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
19149 }
19150 #[doc = "JPGDEC Clock Enable During CSleep Mode"]
19151 pub const fn jpgdeclpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19152 let val = (self.0 >> 5usize) & 0x01;
19153 super::vals::Ahb3lpenrMdmalpen(val as u8)
19154 }
19155 #[doc = "JPGDEC Clock Enable During CSleep Mode"]
19156 pub fn set_jpgdeclpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19157 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
19158 }
19159 #[doc = "FLITF Clock Enable During CSleep Mode"]
19160 pub const fn flashlpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19161 let val = (self.0 >> 8usize) & 0x01;
19162 super::vals::Ahb3lpenrMdmalpen(val as u8)
19163 }
19164 #[doc = "FLITF Clock Enable During CSleep Mode"]
19165 pub fn set_flashlpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19166 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
19167 }
19168 #[doc = "FMC Peripheral Clocks Enable During CSleep Mode"]
19169 pub const fn fmclpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19170 let val = (self.0 >> 12usize) & 0x01;
19171 super::vals::Ahb3lpenrMdmalpen(val as u8)
19172 }
19173 #[doc = "FMC Peripheral Clocks Enable During CSleep Mode"]
19174 pub fn set_fmclpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19175 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
19176 }
19177 #[doc = "QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode"]
19178 pub const fn qspilpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19179 let val = (self.0 >> 14usize) & 0x01;
19180 super::vals::Ahb3lpenrMdmalpen(val as u8)
19181 }
19182 #[doc = "QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode"]
19183 pub fn set_qspilpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19184 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
19185 }
19186 #[doc = "SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode"]
19187 pub const fn sdmmc1lpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19188 let val = (self.0 >> 16usize) & 0x01;
19189 super::vals::Ahb3lpenrMdmalpen(val as u8)
19190 }
19191 #[doc = "SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode"]
19192 pub fn set_sdmmc1lpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19193 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
19194 }
19195 #[doc = "D1DTCM1 Block Clock Enable During CSleep mode"]
19196 pub const fn d1dtcm1lpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19197 let val = (self.0 >> 28usize) & 0x01;
19198 super::vals::Ahb3lpenrMdmalpen(val as u8)
19199 }
19200 #[doc = "D1DTCM1 Block Clock Enable During CSleep mode"]
19201 pub fn set_d1dtcm1lpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19202 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
19203 }
19204 #[doc = "D1 DTCM2 Block Clock Enable During CSleep mode"]
19205 pub const fn dtcm2lpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19206 let val = (self.0 >> 29usize) & 0x01;
19207 super::vals::Ahb3lpenrMdmalpen(val as u8)
19208 }
19209 #[doc = "D1 DTCM2 Block Clock Enable During CSleep mode"]
19210 pub fn set_dtcm2lpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19211 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
19212 }
19213 #[doc = "D1ITCM Block Clock Enable During CSleep mode"]
19214 pub const fn itcmlpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19215 let val = (self.0 >> 30usize) & 0x01;
19216 super::vals::Ahb3lpenrMdmalpen(val as u8)
19217 }
19218 #[doc = "D1ITCM Block Clock Enable During CSleep mode"]
19219 pub fn set_itcmlpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19220 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
19221 }
19222 #[doc = "AXISRAM Block Clock Enable During CSleep mode"]
19223 pub const fn axisramlpen(&self) -> super::vals::Ahb3lpenrMdmalpen {
19224 let val = (self.0 >> 31usize) & 0x01;
19225 super::vals::Ahb3lpenrMdmalpen(val as u8)
19226 }
19227 #[doc = "AXISRAM Block Clock Enable During CSleep mode"]
19228 pub fn set_axisramlpen(&mut self, val: super::vals::Ahb3lpenrMdmalpen) {
19229 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
19230 }
12326 } 19231 }
19232 impl Default for Ahb3lpenr {
19233 fn default() -> Ahb3lpenr {
19234 Ahb3lpenr(0)
19235 }
19236>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
19237 }
19238 #[doc = "RCC Domain 2 Kernel Clock Configuration Register"]
12327 #[repr(transparent)] 19239 #[repr(transparent)]
19240<<<<<<< HEAD
12328 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 19241 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
12329 pub struct Rtcsel(pub u8); 19242 pub struct Rtcsel(pub u8);
12330 impl Rtcsel { 19243 impl Rtcsel {
@@ -12368,8 +19281,83 @@ bits in the RCC clock control register (RCC_CR)) used as the RTC clock"]
12368 pub const DISABLED: Self = Self(0); 19281 pub const DISABLED: Self = Self(0);
12369 #[doc = "DMA clock enabled in Sleep mode"] 19282 #[doc = "DMA clock enabled in Sleep mode"]
12370 pub const ENABLED: Self = Self(0x01); 19283 pub const ENABLED: Self = Self(0x01);
19284=======
19285 #[derive(Copy, Clone, Eq, PartialEq)]
19286 pub struct D2ccip2r(pub u32);
19287 impl D2ccip2r {
19288 #[doc = "USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection"]
19289 pub const fn usart234578sel(&self) -> super::vals::Usart234578sel {
19290 let val = (self.0 >> 0usize) & 0x07;
19291 super::vals::Usart234578sel(val as u8)
19292 }
19293 #[doc = "USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection"]
19294 pub fn set_usart234578sel(&mut self, val: super::vals::Usart234578sel) {
19295 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
19296 }
19297 #[doc = "USART1 and 6 kernel clock source selection"]
19298 pub const fn usart16sel(&self) -> super::vals::Usart16sel {
19299 let val = (self.0 >> 3usize) & 0x07;
19300 super::vals::Usart16sel(val as u8)
19301 }
19302 #[doc = "USART1 and 6 kernel clock source selection"]
19303 pub fn set_usart16sel(&mut self, val: super::vals::Usart16sel) {
19304 self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
19305 }
19306 #[doc = "RNG kernel clock source selection"]
19307 pub const fn rngsel(&self) -> super::vals::Rngsel {
19308 let val = (self.0 >> 8usize) & 0x03;
19309 super::vals::Rngsel(val as u8)
19310 }
19311 #[doc = "RNG kernel clock source selection"]
19312 pub fn set_rngsel(&mut self, val: super::vals::Rngsel) {
19313 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
19314 }
19315 #[doc = "I2C1,2,3 kernel clock source selection"]
19316 pub const fn i2c123sel(&self) -> super::vals::I2c123sel {
19317 let val = (self.0 >> 12usize) & 0x03;
19318 super::vals::I2c123sel(val as u8)
19319 }
19320 #[doc = "I2C1,2,3 kernel clock source selection"]
19321 pub fn set_i2c123sel(&mut self, val: super::vals::I2c123sel) {
19322 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
19323 }
19324 #[doc = "USBOTG 1 and 2 kernel clock source selection"]
19325 pub const fn usbsel(&self) -> super::vals::Usbsel {
19326 let val = (self.0 >> 20usize) & 0x03;
19327 super::vals::Usbsel(val as u8)
19328 }
19329 #[doc = "USBOTG 1 and 2 kernel clock source selection"]
19330 pub fn set_usbsel(&mut self, val: super::vals::Usbsel) {
19331 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.0 as u32) & 0x03) << 20usize);
19332 }
19333 #[doc = "HDMI-CEC kernel clock source selection"]
19334 pub const fn cecsel(&self) -> super::vals::Cecsel {
19335 let val = (self.0 >> 22usize) & 0x03;
19336 super::vals::Cecsel(val as u8)
19337 }
19338 #[doc = "HDMI-CEC kernel clock source selection"]
19339 pub fn set_cecsel(&mut self, val: super::vals::Cecsel) {
19340 self.0 = (self.0 & !(0x03 << 22usize)) | (((val.0 as u32) & 0x03) << 22usize);
19341 }
19342 #[doc = "LPTIM1 kernel clock source selection"]
19343 pub const fn lptim1sel(&self) -> super::vals::Lptim1sel {
19344 let val = (self.0 >> 28usize) & 0x07;
19345 super::vals::Lptim1sel(val as u8)
19346 }
19347 #[doc = "LPTIM1 kernel clock source selection"]
19348 pub fn set_lptim1sel(&mut self, val: super::vals::Lptim1sel) {
19349 self.0 = (self.0 & !(0x07 << 28usize)) | (((val.0 as u32) & 0x07) << 28usize);
19350 }
12371 } 19351 }
19352 impl Default for D2ccip2r {
19353 fn default() -> D2ccip2r {
19354 D2ccip2r(0)
19355 }
19356>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
19357 }
19358 #[doc = "RCC APB2 Clock Register"]
12372 #[repr(transparent)] 19359 #[repr(transparent)]
19360<<<<<<< HEAD
12373 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 19361 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
12374 pub struct Lpwrrstfr(pub u8); 19362 pub struct Lpwrrstfr(pub u8);
12375 impl Lpwrrstfr { 19363 impl Lpwrrstfr {
@@ -12398,15 +19386,264 @@ bits in the RCC clock control register (RCC_CR)) used as the RTC clock"]
12398 pub const LSI: Self = Self(0x06); 19386 pub const LSI: Self = Self(0x06);
12399 #[doc = "LSE oscillator clock selected"] 19387 #[doc = "LSE oscillator clock selected"]
12400 pub const LSE: Self = Self(0x07); 19388 pub const LSE: Self = Self(0x07);
19389=======
19390 #[derive(Copy, Clone, Eq, PartialEq)]
19391 pub struct C1Apb2enr(pub u32);
19392 impl C1Apb2enr {
19393 #[doc = "TIM1 peripheral clock enable"]
19394 pub const fn tim1en(&self) -> super::vals::C1Apb2enrTim1en {
19395 let val = (self.0 >> 0usize) & 0x01;
19396 super::vals::C1Apb2enrTim1en(val as u8)
19397 }
19398 #[doc = "TIM1 peripheral clock enable"]
19399 pub fn set_tim1en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19400 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
19401 }
19402 #[doc = "TIM8 peripheral clock enable"]
19403 pub const fn tim8en(&self) -> super::vals::C1Apb2enrTim1en {
19404 let val = (self.0 >> 1usize) & 0x01;
19405 super::vals::C1Apb2enrTim1en(val as u8)
19406 }
19407 #[doc = "TIM8 peripheral clock enable"]
19408 pub fn set_tim8en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19409 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
19410 }
19411 #[doc = "USART1 Peripheral Clocks Enable"]
19412 pub const fn usart1en(&self) -> super::vals::C1Apb2enrTim1en {
19413 let val = (self.0 >> 4usize) & 0x01;
19414 super::vals::C1Apb2enrTim1en(val as u8)
19415 }
19416 #[doc = "USART1 Peripheral Clocks Enable"]
19417 pub fn set_usart1en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19418 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
19419 }
19420 #[doc = "USART6 Peripheral Clocks Enable"]
19421 pub const fn usart6en(&self) -> super::vals::C1Apb2enrTim1en {
19422 let val = (self.0 >> 5usize) & 0x01;
19423 super::vals::C1Apb2enrTim1en(val as u8)
19424 }
19425 #[doc = "USART6 Peripheral Clocks Enable"]
19426 pub fn set_usart6en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19427 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
19428 }
19429 #[doc = "SPI1 Peripheral Clocks Enable"]
19430 pub const fn spi1en(&self) -> super::vals::C1Apb2enrTim1en {
19431 let val = (self.0 >> 12usize) & 0x01;
19432 super::vals::C1Apb2enrTim1en(val as u8)
19433 }
19434 #[doc = "SPI1 Peripheral Clocks Enable"]
19435 pub fn set_spi1en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19436 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
19437 }
19438 #[doc = "SPI4 Peripheral Clocks Enable"]
19439 pub const fn spi4en(&self) -> super::vals::C1Apb2enrTim1en {
19440 let val = (self.0 >> 13usize) & 0x01;
19441 super::vals::C1Apb2enrTim1en(val as u8)
19442 }
19443 #[doc = "SPI4 Peripheral Clocks Enable"]
19444 pub fn set_spi4en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19445 self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize);
19446 }
19447 #[doc = "TIM15 peripheral clock enable"]
19448 pub const fn tim15en(&self) -> super::vals::C1Apb2enrTim1en {
19449 let val = (self.0 >> 16usize) & 0x01;
19450 super::vals::C1Apb2enrTim1en(val as u8)
19451 }
19452 #[doc = "TIM15 peripheral clock enable"]
19453 pub fn set_tim15en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19454 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
19455 }
19456 #[doc = "TIM16 peripheral clock enable"]
19457 pub const fn tim16en(&self) -> super::vals::C1Apb2enrTim1en {
19458 let val = (self.0 >> 17usize) & 0x01;
19459 super::vals::C1Apb2enrTim1en(val as u8)
19460 }
19461 #[doc = "TIM16 peripheral clock enable"]
19462 pub fn set_tim16en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19463 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
19464 }
19465 #[doc = "TIM17 peripheral clock enable"]
19466 pub const fn tim17en(&self) -> super::vals::C1Apb2enrTim1en {
19467 let val = (self.0 >> 18usize) & 0x01;
19468 super::vals::C1Apb2enrTim1en(val as u8)
19469 }
19470 #[doc = "TIM17 peripheral clock enable"]
19471 pub fn set_tim17en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19472 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
19473 }
19474 #[doc = "SPI5 Peripheral Clocks Enable"]
19475 pub const fn spi5en(&self) -> super::vals::C1Apb2enrTim1en {
19476 let val = (self.0 >> 20usize) & 0x01;
19477 super::vals::C1Apb2enrTim1en(val as u8)
19478 }
19479 #[doc = "SPI5 Peripheral Clocks Enable"]
19480 pub fn set_spi5en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19481 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.0 as u32) & 0x01) << 20usize);
19482 }
19483 #[doc = "SAI1 Peripheral Clocks Enable"]
19484 pub const fn sai1en(&self) -> super::vals::C1Apb2enrTim1en {
19485 let val = (self.0 >> 22usize) & 0x01;
19486 super::vals::C1Apb2enrTim1en(val as u8)
19487 }
19488 #[doc = "SAI1 Peripheral Clocks Enable"]
19489 pub fn set_sai1en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19490 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
19491 }
19492 #[doc = "SAI2 Peripheral Clocks Enable"]
19493 pub const fn sai2en(&self) -> super::vals::C1Apb2enrTim1en {
19494 let val = (self.0 >> 23usize) & 0x01;
19495 super::vals::C1Apb2enrTim1en(val as u8)
19496 }
19497 #[doc = "SAI2 Peripheral Clocks Enable"]
19498 pub fn set_sai2en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19499 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
19500 }
19501 #[doc = "SAI3 Peripheral Clocks Enable"]
19502 pub const fn sai3en(&self) -> super::vals::C1Apb2enrTim1en {
19503 let val = (self.0 >> 24usize) & 0x01;
19504 super::vals::C1Apb2enrTim1en(val as u8)
19505 }
19506 #[doc = "SAI3 Peripheral Clocks Enable"]
19507 pub fn set_sai3en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19508 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
19509 }
19510 #[doc = "DFSDM1 Peripheral Clocks Enable"]
19511 pub const fn dfsdm1en(&self) -> super::vals::C1Apb2enrTim1en {
19512 let val = (self.0 >> 28usize) & 0x01;
19513 super::vals::C1Apb2enrTim1en(val as u8)
19514 }
19515 #[doc = "DFSDM1 Peripheral Clocks Enable"]
19516 pub fn set_dfsdm1en(&mut self, val: super::vals::C1Apb2enrTim1en) {
19517 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
19518 }
19519 #[doc = "HRTIM peripheral clock enable"]
19520 pub const fn hrtimen(&self) -> super::vals::C1Apb2enrTim1en {
19521 let val = (self.0 >> 29usize) & 0x01;
19522 super::vals::C1Apb2enrTim1en(val as u8)
19523 }
19524 #[doc = "HRTIM peripheral clock enable"]
19525 pub fn set_hrtimen(&mut self, val: super::vals::C1Apb2enrTim1en) {
19526 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
19527 }
19528 }
19529 impl Default for C1Apb2enr {
19530 fn default() -> C1Apb2enr {
19531 C1Apb2enr(0)
19532 }
19533>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
12401 } 19534 }
19535 #[doc = "RCC AHB1 Sleep Clock Register"]
12402 #[repr(transparent)] 19536 #[repr(transparent)]
19537<<<<<<< HEAD
12403 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 19538 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
12404 pub struct Rmvfw(pub u8); 19539 pub struct Rmvfw(pub u8);
12405 impl Rmvfw { 19540 impl Rmvfw {
12406 #[doc = "Clears the reset flag"] 19541 #[doc = "Clears the reset flag"]
12407 pub const CLEAR: Self = Self(0x01); 19542 pub const CLEAR: Self = Self(0x01);
19543=======
19544 #[derive(Copy, Clone, Eq, PartialEq)]
19545 pub struct C1Ahb1lpenr(pub u32);
19546 impl C1Ahb1lpenr {
19547 #[doc = "DMA1 Clock Enable During CSleep Mode"]
19548 pub const fn dma1lpen(&self) -> super::vals::C1Ahb1lpenrDma1lpen {
19549 let val = (self.0 >> 0usize) & 0x01;
19550 super::vals::C1Ahb1lpenrDma1lpen(val as u8)
19551 }
19552 #[doc = "DMA1 Clock Enable During CSleep Mode"]
19553 pub fn set_dma1lpen(&mut self, val: super::vals::C1Ahb1lpenrDma1lpen) {
19554 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
19555 }
19556 #[doc = "DMA2 Clock Enable During CSleep Mode"]
19557 pub const fn dma2lpen(&self) -> super::vals::C1Ahb1lpenrDma1lpen {
19558 let val = (self.0 >> 1usize) & 0x01;
19559 super::vals::C1Ahb1lpenrDma1lpen(val as u8)
19560 }
19561 #[doc = "DMA2 Clock Enable During CSleep Mode"]
19562 pub fn set_dma2lpen(&mut self, val: super::vals::C1Ahb1lpenrDma1lpen) {
19563 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
19564 }
19565 #[doc = "ADC1/2 Peripheral Clocks Enable During CSleep Mode"]
19566 pub const fn adc12lpen(&self) -> super::vals::C1Ahb1lpenrDma1lpen {
19567 let val = (self.0 >> 5usize) & 0x01;
19568 super::vals::C1Ahb1lpenrDma1lpen(val as u8)
19569 }
19570 #[doc = "ADC1/2 Peripheral Clocks Enable During CSleep Mode"]
19571 pub fn set_adc12lpen(&mut self, val: super::vals::C1Ahb1lpenrDma1lpen) {
19572 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
19573 }
19574 #[doc = "Ethernet MAC bus interface Clock Enable During CSleep Mode"]
19575 pub const fn eth1maclpen(&self) -> super::vals::C1Ahb1lpenrDma1lpen {
19576 let val = (self.0 >> 15usize) & 0x01;
19577 super::vals::C1Ahb1lpenrDma1lpen(val as u8)
19578 }
19579 #[doc = "Ethernet MAC bus interface Clock Enable During CSleep Mode"]
19580 pub fn set_eth1maclpen(&mut self, val: super::vals::C1Ahb1lpenrDma1lpen) {
19581 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
19582 }
19583 #[doc = "Ethernet Transmission Clock Enable During CSleep Mode"]
19584 pub const fn eth1txlpen(&self) -> super::vals::C1Ahb1lpenrDma1lpen {
19585 let val = (self.0 >> 16usize) & 0x01;
19586 super::vals::C1Ahb1lpenrDma1lpen(val as u8)
19587 }
19588 #[doc = "Ethernet Transmission Clock Enable During CSleep Mode"]
19589 pub fn set_eth1txlpen(&mut self, val: super::vals::C1Ahb1lpenrDma1lpen) {
19590 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
19591 }
19592 #[doc = "Ethernet Reception Clock Enable During CSleep Mode"]
19593 pub const fn eth1rxlpen(&self) -> super::vals::C1Ahb1lpenrDma1lpen {
19594 let val = (self.0 >> 17usize) & 0x01;
19595 super::vals::C1Ahb1lpenrDma1lpen(val as u8)
19596 }
19597 #[doc = "Ethernet Reception Clock Enable During CSleep Mode"]
19598 pub fn set_eth1rxlpen(&mut self, val: super::vals::C1Ahb1lpenrDma1lpen) {
19599 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
19600 }
19601 #[doc = "USB1OTG peripheral clock enable during CSleep mode"]
19602 pub const fn usb1otglpen(&self) -> super::vals::C1Ahb1lpenrDma1lpen {
19603 let val = (self.0 >> 25usize) & 0x01;
19604 super::vals::C1Ahb1lpenrDma1lpen(val as u8)
19605 }
19606 #[doc = "USB1OTG peripheral clock enable during CSleep mode"]
19607 pub fn set_usb1otglpen(&mut self, val: super::vals::C1Ahb1lpenrDma1lpen) {
19608 self.0 = (self.0 & !(0x01 << 25usize)) | (((val.0 as u32) & 0x01) << 25usize);
19609 }
19610 #[doc = "USB_PHY1 clock enable during CSleep mode"]
19611 pub const fn usb1ulpilpen(&self) -> super::vals::C1Ahb1lpenrDma1lpen {
19612 let val = (self.0 >> 26usize) & 0x01;
19613 super::vals::C1Ahb1lpenrDma1lpen(val as u8)
19614 }
19615 #[doc = "USB_PHY1 clock enable during CSleep mode"]
19616 pub fn set_usb1ulpilpen(&mut self, val: super::vals::C1Ahb1lpenrDma1lpen) {
19617 self.0 = (self.0 & !(0x01 << 26usize)) | (((val.0 as u32) & 0x01) << 26usize);
19618 }
19619 #[doc = "USB2OTG peripheral clock enable during CSleep mode"]
19620 pub const fn usb2otglpen(&self) -> super::vals::C1Ahb1lpenrDma1lpen {
19621 let val = (self.0 >> 27usize) & 0x01;
19622 super::vals::C1Ahb1lpenrDma1lpen(val as u8)
19623 }
19624 #[doc = "USB2OTG peripheral clock enable during CSleep mode"]
19625 pub fn set_usb2otglpen(&mut self, val: super::vals::C1Ahb1lpenrDma1lpen) {
19626 self.0 = (self.0 & !(0x01 << 27usize)) | (((val.0 as u32) & 0x01) << 27usize);
19627 }
19628 #[doc = "USB_PHY2 clocks enable during CSleep mode"]
19629 pub const fn usb2ulpilpen(&self) -> super::vals::C1Ahb1lpenrDma1lpen {
19630 let val = (self.0 >> 28usize) & 0x01;
19631 super::vals::C1Ahb1lpenrDma1lpen(val as u8)
19632 }
19633 #[doc = "USB_PHY2 clocks enable during CSleep mode"]
19634 pub fn set_usb2ulpilpen(&mut self, val: super::vals::C1Ahb1lpenrDma1lpen) {
19635 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
19636 }
19637 }
19638 impl Default for C1Ahb1lpenr {
19639 fn default() -> C1Ahb1lpenr {
19640 C1Ahb1lpenr(0)
19641 }
19642>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
12408 } 19643 }
19644 #[doc = "RCC PLL1 Dividers Configuration Register"]
12409 #[repr(transparent)] 19645 #[repr(transparent)]
19646<<<<<<< HEAD
12410 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] 19647 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
12411 pub struct Iophrst(pub u8); 19648 pub struct Iophrst(pub u8);
12412 impl Iophrst { 19649 impl Iophrst {
@@ -13099,18 +20336,632 @@ pub mod dma_v2 {
13099 impl Cr { 20336 impl Cr {
13100 #[doc = "Stream enable / flag stream ready when read low"] 20337 #[doc = "Stream enable / flag stream ready when read low"]
13101 pub const fn en(&self) -> bool { 20338 pub const fn en(&self) -> bool {
20339=======
20340 #[derive(Copy, Clone, Eq, PartialEq)]
20341 pub struct Pll1divr(pub u32);
20342 impl Pll1divr {
20343 #[doc = "Multiplication factor for PLL1 VCO"]
20344 pub const fn divn1(&self) -> u16 {
20345 let val = (self.0 >> 0usize) & 0x01ff;
20346 val as u16
20347 }
20348 #[doc = "Multiplication factor for PLL1 VCO"]
20349 pub fn set_divn1(&mut self, val: u16) {
20350 self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
20351 }
20352 #[doc = "PLL1 DIVP division factor"]
20353 pub const fn divp1(&self) -> super::vals::Divp1 {
20354 let val = (self.0 >> 9usize) & 0x7f;
20355 super::vals::Divp1(val as u8)
20356 }
20357 #[doc = "PLL1 DIVP division factor"]
20358 pub fn set_divp1(&mut self, val: super::vals::Divp1) {
20359 self.0 = (self.0 & !(0x7f << 9usize)) | (((val.0 as u32) & 0x7f) << 9usize);
20360 }
20361 #[doc = "PLL1 DIVQ division factor"]
20362 pub const fn divq1(&self) -> u8 {
20363 let val = (self.0 >> 16usize) & 0x7f;
20364 val as u8
20365 }
20366 #[doc = "PLL1 DIVQ division factor"]
20367 pub fn set_divq1(&mut self, val: u8) {
20368 self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
20369 }
20370 #[doc = "PLL1 DIVR division factor"]
20371 pub const fn divr1(&self) -> u8 {
20372 let val = (self.0 >> 24usize) & 0x7f;
20373 val as u8
20374 }
20375 #[doc = "PLL1 DIVR division factor"]
20376 pub fn set_divr1(&mut self, val: u8) {
20377 self.0 = (self.0 & !(0x7f << 24usize)) | (((val as u32) & 0x7f) << 24usize);
20378 }
20379 }
20380 impl Default for Pll1divr {
20381 fn default() -> Pll1divr {
20382 Pll1divr(0)
20383 }
20384 }
20385 #[doc = "RCC APB1 Low Sleep Clock Register"]
20386 #[repr(transparent)]
20387 #[derive(Copy, Clone, Eq, PartialEq)]
20388 pub struct C1Apb1llpenr(pub u32);
20389 impl C1Apb1llpenr {
20390 #[doc = "TIM2 peripheral clock enable during CSleep mode"]
20391 pub const fn tim2lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
13102 let val = (self.0 >> 0usize) & 0x01; 20392 let val = (self.0 >> 0usize) & 0x01;
13103 val != 0 20393 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20394 }
20395 #[doc = "TIM2 peripheral clock enable during CSleep mode"]
20396 pub fn set_tim2lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20397 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
20398 }
20399 #[doc = "TIM3 peripheral clock enable during CSleep mode"]
20400 pub const fn tim3lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20401 let val = (self.0 >> 1usize) & 0x01;
20402 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20403 }
20404 #[doc = "TIM3 peripheral clock enable during CSleep mode"]
20405 pub fn set_tim3lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20406 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
20407 }
20408 #[doc = "TIM4 peripheral clock enable during CSleep mode"]
20409 pub const fn tim4lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20410 let val = (self.0 >> 2usize) & 0x01;
20411 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20412 }
20413 #[doc = "TIM4 peripheral clock enable during CSleep mode"]
20414 pub fn set_tim4lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20415 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
20416 }
20417 #[doc = "TIM5 peripheral clock enable during CSleep mode"]
20418 pub const fn tim5lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20419 let val = (self.0 >> 3usize) & 0x01;
20420 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20421 }
20422 #[doc = "TIM5 peripheral clock enable during CSleep mode"]
20423 pub fn set_tim5lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20424 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
20425 }
20426 #[doc = "TIM6 peripheral clock enable during CSleep mode"]
20427 pub const fn tim6lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20428 let val = (self.0 >> 4usize) & 0x01;
20429 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20430 }
20431 #[doc = "TIM6 peripheral clock enable during CSleep mode"]
20432 pub fn set_tim6lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20433 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
20434 }
20435 #[doc = "TIM7 peripheral clock enable during CSleep mode"]
20436 pub const fn tim7lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20437 let val = (self.0 >> 5usize) & 0x01;
20438 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20439 }
20440 #[doc = "TIM7 peripheral clock enable during CSleep mode"]
20441 pub fn set_tim7lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20442 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
20443 }
20444 #[doc = "TIM12 peripheral clock enable during CSleep mode"]
20445 pub const fn tim12lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20446 let val = (self.0 >> 6usize) & 0x01;
20447 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20448 }
20449 #[doc = "TIM12 peripheral clock enable during CSleep mode"]
20450 pub fn set_tim12lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20451 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
20452 }
20453 #[doc = "TIM13 peripheral clock enable during CSleep mode"]
20454 pub const fn tim13lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20455 let val = (self.0 >> 7usize) & 0x01;
20456 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20457 }
20458 #[doc = "TIM13 peripheral clock enable during CSleep mode"]
20459 pub fn set_tim13lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20460 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
20461 }
20462 #[doc = "TIM14 peripheral clock enable during CSleep mode"]
20463 pub const fn tim14lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20464 let val = (self.0 >> 8usize) & 0x01;
20465 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20466 }
20467 #[doc = "TIM14 peripheral clock enable during CSleep mode"]
20468 pub fn set_tim14lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20469 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
20470 }
20471 #[doc = "LPTIM1 Peripheral Clocks Enable During CSleep Mode"]
20472 pub const fn lptim1lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20473 let val = (self.0 >> 9usize) & 0x01;
20474 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20475 }
20476 #[doc = "LPTIM1 Peripheral Clocks Enable During CSleep Mode"]
20477 pub fn set_lptim1lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20478 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
20479 }
20480 #[doc = "SPI2 Peripheral Clocks Enable During CSleep Mode"]
20481 pub const fn spi2lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20482 let val = (self.0 >> 14usize) & 0x01;
20483 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20484 }
20485 #[doc = "SPI2 Peripheral Clocks Enable During CSleep Mode"]
20486 pub fn set_spi2lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20487 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
20488 }
20489 #[doc = "SPI3 Peripheral Clocks Enable During CSleep Mode"]
20490 pub const fn spi3lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20491 let val = (self.0 >> 15usize) & 0x01;
20492 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20493 }
20494 #[doc = "SPI3 Peripheral Clocks Enable During CSleep Mode"]
20495 pub fn set_spi3lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20496 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
20497 }
20498 #[doc = "SPDIFRX Peripheral Clocks Enable During CSleep Mode"]
20499 pub const fn spdifrxlpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20500 let val = (self.0 >> 16usize) & 0x01;
20501 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20502 }
20503 #[doc = "SPDIFRX Peripheral Clocks Enable During CSleep Mode"]
20504 pub fn set_spdifrxlpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20505 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
20506 }
20507 #[doc = "USART2 Peripheral Clocks Enable During CSleep Mode"]
20508 pub const fn usart2lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20509 let val = (self.0 >> 17usize) & 0x01;
20510 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20511 }
20512 #[doc = "USART2 Peripheral Clocks Enable During CSleep Mode"]
20513 pub fn set_usart2lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20514 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
20515 }
20516 #[doc = "USART3 Peripheral Clocks Enable During CSleep Mode"]
20517 pub const fn usart3lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20518 let val = (self.0 >> 18usize) & 0x01;
20519 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20520 }
20521 #[doc = "USART3 Peripheral Clocks Enable During CSleep Mode"]
20522 pub fn set_usart3lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20523 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
20524 }
20525 #[doc = "UART4 Peripheral Clocks Enable During CSleep Mode"]
20526 pub const fn uart4lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20527 let val = (self.0 >> 19usize) & 0x01;
20528 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20529 }
20530 #[doc = "UART4 Peripheral Clocks Enable During CSleep Mode"]
20531 pub fn set_uart4lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20532 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
20533 }
20534 #[doc = "UART5 Peripheral Clocks Enable During CSleep Mode"]
20535 pub const fn uart5lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20536 let val = (self.0 >> 20usize) & 0x01;
20537 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20538 }
20539 #[doc = "UART5 Peripheral Clocks Enable During CSleep Mode"]
20540 pub fn set_uart5lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20541 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.0 as u32) & 0x01) << 20usize);
20542 }
20543 #[doc = "I2C1 Peripheral Clocks Enable During CSleep Mode"]
20544 pub const fn i2c1lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20545 let val = (self.0 >> 21usize) & 0x01;
20546 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20547 }
20548 #[doc = "I2C1 Peripheral Clocks Enable During CSleep Mode"]
20549 pub fn set_i2c1lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20550 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
20551 }
20552 #[doc = "I2C2 Peripheral Clocks Enable During CSleep Mode"]
20553 pub const fn i2c2lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20554 let val = (self.0 >> 22usize) & 0x01;
20555 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20556 }
20557 #[doc = "I2C2 Peripheral Clocks Enable During CSleep Mode"]
20558 pub fn set_i2c2lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20559 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
20560 }
20561 #[doc = "I2C3 Peripheral Clocks Enable During CSleep Mode"]
20562 pub const fn i2c3lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20563 let val = (self.0 >> 23usize) & 0x01;
20564 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20565 }
20566 #[doc = "I2C3 Peripheral Clocks Enable During CSleep Mode"]
20567 pub fn set_i2c3lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20568 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
20569 }
20570 #[doc = "HDMI-CEC Peripheral Clocks Enable During CSleep Mode"]
20571 pub const fn ceclpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20572 let val = (self.0 >> 27usize) & 0x01;
20573 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20574 }
20575 #[doc = "HDMI-CEC Peripheral Clocks Enable During CSleep Mode"]
20576 pub fn set_ceclpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20577 self.0 = (self.0 & !(0x01 << 27usize)) | (((val.0 as u32) & 0x01) << 27usize);
20578 }
20579 #[doc = "DAC1/2 peripheral clock enable during CSleep mode"]
20580 pub const fn dac12lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20581 let val = (self.0 >> 29usize) & 0x01;
20582 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20583 }
20584 #[doc = "DAC1/2 peripheral clock enable during CSleep mode"]
20585 pub fn set_dac12lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20586 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
20587 }
20588 #[doc = "UART7 Peripheral Clocks Enable During CSleep Mode"]
20589 pub const fn uart7lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20590 let val = (self.0 >> 30usize) & 0x01;
20591 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20592 }
20593 #[doc = "UART7 Peripheral Clocks Enable During CSleep Mode"]
20594 pub fn set_uart7lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20595 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
20596 }
20597 #[doc = "UART8 Peripheral Clocks Enable During CSleep Mode"]
20598 pub const fn uart8lpen(&self) -> super::vals::C1Apb1llpenrTim2lpen {
20599 let val = (self.0 >> 31usize) & 0x01;
20600 super::vals::C1Apb1llpenrTim2lpen(val as u8)
20601 }
20602 #[doc = "UART8 Peripheral Clocks Enable During CSleep Mode"]
20603 pub fn set_uart8lpen(&mut self, val: super::vals::C1Apb1llpenrTim2lpen) {
20604 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
20605 }
20606 }
20607 impl Default for C1Apb1llpenr {
20608 fn default() -> C1Apb1llpenr {
20609 C1Apb1llpenr(0)
20610 }
20611 }
20612 #[doc = "RCC D3 Autonomous mode Register"]
20613 #[repr(transparent)]
20614 #[derive(Copy, Clone, Eq, PartialEq)]
20615 pub struct D3amr(pub u32);
20616 impl D3amr {
20617 #[doc = "BDMA and DMAMUX Autonomous mode enable"]
20618 pub const fn bdmaamen(&self) -> super::vals::Bdmaamen {
20619 let val = (self.0 >> 0usize) & 0x01;
20620 super::vals::Bdmaamen(val as u8)
20621 }
20622 #[doc = "BDMA and DMAMUX Autonomous mode enable"]
20623 pub fn set_bdmaamen(&mut self, val: super::vals::Bdmaamen) {
20624 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
20625 }
20626 #[doc = "LPUART1 Autonomous mode enable"]
20627 pub const fn lpuart1amen(&self) -> super::vals::Bdmaamen {
20628 let val = (self.0 >> 3usize) & 0x01;
20629 super::vals::Bdmaamen(val as u8)
20630 }
20631 #[doc = "LPUART1 Autonomous mode enable"]
20632 pub fn set_lpuart1amen(&mut self, val: super::vals::Bdmaamen) {
20633 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
20634 }
20635 #[doc = "SPI6 Autonomous mode enable"]
20636 pub const fn spi6amen(&self) -> super::vals::Bdmaamen {
20637 let val = (self.0 >> 5usize) & 0x01;
20638 super::vals::Bdmaamen(val as u8)
20639 }
20640 #[doc = "SPI6 Autonomous mode enable"]
20641 pub fn set_spi6amen(&mut self, val: super::vals::Bdmaamen) {
20642 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
20643 }
20644 #[doc = "I2C4 Autonomous mode enable"]
20645 pub const fn i2c4amen(&self) -> super::vals::Bdmaamen {
20646 let val = (self.0 >> 7usize) & 0x01;
20647 super::vals::Bdmaamen(val as u8)
20648 }
20649 #[doc = "I2C4 Autonomous mode enable"]
20650 pub fn set_i2c4amen(&mut self, val: super::vals::Bdmaamen) {
20651 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
20652 }
20653 #[doc = "LPTIM2 Autonomous mode enable"]
20654 pub const fn lptim2amen(&self) -> super::vals::Bdmaamen {
20655 let val = (self.0 >> 9usize) & 0x01;
20656 super::vals::Bdmaamen(val as u8)
20657 }
20658 #[doc = "LPTIM2 Autonomous mode enable"]
20659 pub fn set_lptim2amen(&mut self, val: super::vals::Bdmaamen) {
20660 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
20661 }
20662 #[doc = "LPTIM3 Autonomous mode enable"]
20663 pub const fn lptim3amen(&self) -> super::vals::Bdmaamen {
20664 let val = (self.0 >> 10usize) & 0x01;
20665 super::vals::Bdmaamen(val as u8)
20666 }
20667 #[doc = "LPTIM3 Autonomous mode enable"]
20668 pub fn set_lptim3amen(&mut self, val: super::vals::Bdmaamen) {
20669 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
20670 }
20671 #[doc = "LPTIM4 Autonomous mode enable"]
20672 pub const fn lptim4amen(&self) -> super::vals::Bdmaamen {
20673 let val = (self.0 >> 11usize) & 0x01;
20674 super::vals::Bdmaamen(val as u8)
20675 }
20676 #[doc = "LPTIM4 Autonomous mode enable"]
20677 pub fn set_lptim4amen(&mut self, val: super::vals::Bdmaamen) {
20678 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
20679 }
20680 #[doc = "LPTIM5 Autonomous mode enable"]
20681 pub const fn lptim5amen(&self) -> super::vals::Bdmaamen {
20682 let val = (self.0 >> 12usize) & 0x01;
20683 super::vals::Bdmaamen(val as u8)
20684 }
20685 #[doc = "LPTIM5 Autonomous mode enable"]
20686 pub fn set_lptim5amen(&mut self, val: super::vals::Bdmaamen) {
20687 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
13104 } 20688 }
20689 #[doc = "COMP12 Autonomous mode enable"]
20690 pub const fn comp12amen(&self) -> super::vals::Bdmaamen {
20691 let val = (self.0 >> 14usize) & 0x01;
20692 super::vals::Bdmaamen(val as u8)
20693 }
20694 #[doc = "COMP12 Autonomous mode enable"]
20695 pub fn set_comp12amen(&mut self, val: super::vals::Bdmaamen) {
20696 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
20697 }
20698 #[doc = "VREF Autonomous mode enable"]
20699 pub const fn vrefamen(&self) -> super::vals::Bdmaamen {
20700 let val = (self.0 >> 15usize) & 0x01;
20701 super::vals::Bdmaamen(val as u8)
20702 }
20703 #[doc = "VREF Autonomous mode enable"]
20704 pub fn set_vrefamen(&mut self, val: super::vals::Bdmaamen) {
20705 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
20706 }
20707 #[doc = "RTC Autonomous mode enable"]
20708 pub const fn rtcamen(&self) -> super::vals::Bdmaamen {
20709 let val = (self.0 >> 16usize) & 0x01;
20710 super::vals::Bdmaamen(val as u8)
20711 }
20712 #[doc = "RTC Autonomous mode enable"]
20713 pub fn set_rtcamen(&mut self, val: super::vals::Bdmaamen) {
20714 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
20715 }
20716 #[doc = "CRC Autonomous mode enable"]
20717 pub const fn crcamen(&self) -> super::vals::Bdmaamen {
20718 let val = (self.0 >> 19usize) & 0x01;
20719 super::vals::Bdmaamen(val as u8)
20720 }
20721 #[doc = "CRC Autonomous mode enable"]
20722 pub fn set_crcamen(&mut self, val: super::vals::Bdmaamen) {
20723 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
20724 }
20725 #[doc = "SAI4 Autonomous mode enable"]
20726 pub const fn sai4amen(&self) -> super::vals::Bdmaamen {
20727 let val = (self.0 >> 21usize) & 0x01;
20728 super::vals::Bdmaamen(val as u8)
20729 }
20730 #[doc = "SAI4 Autonomous mode enable"]
20731 pub fn set_sai4amen(&mut self, val: super::vals::Bdmaamen) {
20732 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
20733 }
20734 #[doc = "ADC3 Autonomous mode enable"]
20735 pub const fn adc3amen(&self) -> super::vals::Bdmaamen {
20736 let val = (self.0 >> 24usize) & 0x01;
20737 super::vals::Bdmaamen(val as u8)
20738 }
20739 #[doc = "ADC3 Autonomous mode enable"]
20740 pub fn set_adc3amen(&mut self, val: super::vals::Bdmaamen) {
20741 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
20742 }
20743 #[doc = "Backup RAM Autonomous mode enable"]
20744 pub const fn bkpramamen(&self) -> super::vals::Bdmaamen {
20745 let val = (self.0 >> 28usize) & 0x01;
20746 super::vals::Bdmaamen(val as u8)
20747 }
20748 #[doc = "Backup RAM Autonomous mode enable"]
20749 pub fn set_bkpramamen(&mut self, val: super::vals::Bdmaamen) {
20750 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
20751 }
20752 #[doc = "SRAM4 Autonomous mode enable"]
20753 pub const fn sram4amen(&self) -> super::vals::Bdmaamen {
20754 let val = (self.0 >> 29usize) & 0x01;
20755 super::vals::Bdmaamen(val as u8)
20756 }
20757 #[doc = "SRAM4 Autonomous mode enable"]
20758 pub fn set_sram4amen(&mut self, val: super::vals::Bdmaamen) {
20759 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
20760 }
20761 }
20762 impl Default for D3amr {
20763 fn default() -> D3amr {
20764 D3amr(0)
20765 }
20766 }
20767 #[doc = "RCC APB3 Sleep Clock Register"]
20768 #[repr(transparent)]
20769 #[derive(Copy, Clone, Eq, PartialEq)]
20770 pub struct C1Apb3lpenr(pub u32);
20771 impl C1Apb3lpenr {
20772 #[doc = "LTDC peripheral clock enable during CSleep mode"]
20773 pub const fn ltdclpen(&self) -> super::vals::C1Apb3lpenrLtdclpen {
20774 let val = (self.0 >> 3usize) & 0x01;
20775 super::vals::C1Apb3lpenrLtdclpen(val as u8)
20776 }
20777 #[doc = "LTDC peripheral clock enable during CSleep mode"]
20778 pub fn set_ltdclpen(&mut self, val: super::vals::C1Apb3lpenrLtdclpen) {
20779 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
20780 }
20781 #[doc = "WWDG1 Clock Enable During CSleep Mode"]
20782 pub const fn wwdg1lpen(&self) -> super::vals::C1Apb3lpenrLtdclpen {
20783 let val = (self.0 >> 6usize) & 0x01;
20784 super::vals::C1Apb3lpenrLtdclpen(val as u8)
20785 }
20786 #[doc = "WWDG1 Clock Enable During CSleep Mode"]
20787 pub fn set_wwdg1lpen(&mut self, val: super::vals::C1Apb3lpenrLtdclpen) {
20788 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
20789 }
20790 }
20791 impl Default for C1Apb3lpenr {
20792 fn default() -> C1Apb3lpenr {
20793 C1Apb3lpenr(0)
20794 }
20795 }
20796 #[doc = "RCC Domain 3 Kernel Clock Configuration Register"]
20797 #[repr(transparent)]
20798 #[derive(Copy, Clone, Eq, PartialEq)]
20799 pub struct D3ccipr(pub u32);
20800 impl D3ccipr {
20801 #[doc = "LPUART1 kernel clock source selection"]
20802 pub const fn lpuart1sel(&self) -> super::vals::Lpuart1sel {
20803 let val = (self.0 >> 0usize) & 0x07;
20804 super::vals::Lpuart1sel(val as u8)
20805 }
20806 #[doc = "LPUART1 kernel clock source selection"]
20807 pub fn set_lpuart1sel(&mut self, val: super::vals::Lpuart1sel) {
20808 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
20809 }
20810 #[doc = "I2C4 kernel clock source selection"]
20811 pub const fn i2c4sel(&self) -> super::vals::I2c4sel {
20812 let val = (self.0 >> 8usize) & 0x03;
20813 super::vals::I2c4sel(val as u8)
20814 }
20815 #[doc = "I2C4 kernel clock source selection"]
20816 pub fn set_i2c4sel(&mut self, val: super::vals::I2c4sel) {
20817 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
20818 }
20819 #[doc = "LPTIM2 kernel clock source selection"]
20820 pub const fn lptim2sel(&self) -> super::vals::Lptim2sel {
20821 let val = (self.0 >> 10usize) & 0x07;
20822 super::vals::Lptim2sel(val as u8)
20823 }
20824 #[doc = "LPTIM2 kernel clock source selection"]
20825 pub fn set_lptim2sel(&mut self, val: super::vals::Lptim2sel) {
20826 self.0 = (self.0 & !(0x07 << 10usize)) | (((val.0 as u32) & 0x07) << 10usize);
20827 }
20828 #[doc = "LPTIM3,4,5 kernel clock source selection"]
20829 pub const fn lptim345sel(&self) -> super::vals::Lptim2sel {
20830 let val = (self.0 >> 13usize) & 0x07;
20831 super::vals::Lptim2sel(val as u8)
20832 }
20833 #[doc = "LPTIM3,4,5 kernel clock source selection"]
20834 pub fn set_lptim345sel(&mut self, val: super::vals::Lptim2sel) {
20835 self.0 = (self.0 & !(0x07 << 13usize)) | (((val.0 as u32) & 0x07) << 13usize);
20836 }
20837 #[doc = "SAR ADC kernel clock source selection"]
20838 pub const fn adcsel(&self) -> super::vals::Adcsel {
20839 let val = (self.0 >> 16usize) & 0x03;
20840 super::vals::Adcsel(val as u8)
20841 }
20842 #[doc = "SAR ADC kernel clock source selection"]
20843 pub fn set_adcsel(&mut self, val: super::vals::Adcsel) {
20844 self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize);
20845 }
20846 #[doc = "Sub-Block A of SAI4 kernel clock source selection"]
20847 pub const fn sai4asel(&self) -> super::vals::Sai4asel {
20848 let val = (self.0 >> 21usize) & 0x07;
20849 super::vals::Sai4asel(val as u8)
20850 }
20851 #[doc = "Sub-Block A of SAI4 kernel clock source selection"]
20852 pub fn set_sai4asel(&mut self, val: super::vals::Sai4asel) {
20853 self.0 = (self.0 & !(0x07 << 21usize)) | (((val.0 as u32) & 0x07) << 21usize);
20854 }
20855 #[doc = "Sub-Block B of SAI4 kernel clock source selection"]
20856 pub const fn sai4bsel(&self) -> super::vals::Sai4asel {
20857 let val = (self.0 >> 24usize) & 0x07;
20858 super::vals::Sai4asel(val as u8)
20859 }
20860 #[doc = "Sub-Block B of SAI4 kernel clock source selection"]
20861 pub fn set_sai4bsel(&mut self, val: super::vals::Sai4asel) {
20862 self.0 = (self.0 & !(0x07 << 24usize)) | (((val.0 as u32) & 0x07) << 24usize);
20863 }
20864 #[doc = "SPI6 kernel clock source selection"]
20865 pub const fn spi6sel(&self) -> super::vals::Spi6sel {
20866 let val = (self.0 >> 28usize) & 0x07;
20867 super::vals::Spi6sel(val as u8)
20868 }
20869 #[doc = "SPI6 kernel clock source selection"]
20870 pub fn set_spi6sel(&mut self, val: super::vals::Spi6sel) {
20871 self.0 = (self.0 & !(0x07 << 28usize)) | (((val.0 as u32) & 0x07) << 28usize);
20872 }
20873 }
20874 impl Default for D3ccipr {
20875 fn default() -> D3ccipr {
20876 D3ccipr(0)
20877 }
20878 }
20879 #[doc = "RCC APB1 High Sleep Clock Register"]
20880 #[repr(transparent)]
20881 #[derive(Copy, Clone, Eq, PartialEq)]
20882 pub struct Apb1hlpenr(pub u32);
20883 impl Apb1hlpenr {
20884 #[doc = "Clock Recovery System peripheral clock enable during CSleep mode"]
20885 pub const fn crslpen(&self) -> super::vals::Apb1hlpenrCrslpen {
20886 let val = (self.0 >> 1usize) & 0x01;
20887 super::vals::Apb1hlpenrCrslpen(val as u8)
20888 }
20889 #[doc = "Clock Recovery System peripheral clock enable during CSleep mode"]
20890 pub fn set_crslpen(&mut self, val: super::vals::Apb1hlpenrCrslpen) {
20891 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
20892 }
20893 #[doc = "SWPMI Peripheral Clocks Enable During CSleep Mode"]
20894 pub const fn swplpen(&self) -> super::vals::Apb1hlpenrCrslpen {
20895 let val = (self.0 >> 2usize) & 0x01;
20896 super::vals::Apb1hlpenrCrslpen(val as u8)
20897 }
20898 #[doc = "SWPMI Peripheral Clocks Enable During CSleep Mode"]
20899 pub fn set_swplpen(&mut self, val: super::vals::Apb1hlpenrCrslpen) {
20900 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
20901 }
20902 #[doc = "OPAMP peripheral clock enable during CSleep mode"]
20903 pub const fn opamplpen(&self) -> super::vals::Apb1hlpenrCrslpen {
20904 let val = (self.0 >> 4usize) & 0x01;
20905 super::vals::Apb1hlpenrCrslpen(val as u8)
20906 }
20907 #[doc = "OPAMP peripheral clock enable during CSleep mode"]
20908 pub fn set_opamplpen(&mut self, val: super::vals::Apb1hlpenrCrslpen) {
20909 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
20910 }
20911 #[doc = "MDIOS peripheral clock enable during CSleep mode"]
20912 pub const fn mdioslpen(&self) -> super::vals::Apb1hlpenrCrslpen {
20913 let val = (self.0 >> 5usize) & 0x01;
20914 super::vals::Apb1hlpenrCrslpen(val as u8)
20915 }
20916 #[doc = "MDIOS peripheral clock enable during CSleep mode"]
20917 pub fn set_mdioslpen(&mut self, val: super::vals::Apb1hlpenrCrslpen) {
20918 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
20919 }
20920 #[doc = "FDCAN Peripheral Clocks Enable During CSleep Mode"]
20921 pub const fn fdcanlpen(&self) -> super::vals::Apb1hlpenrCrslpen {
20922 let val = (self.0 >> 8usize) & 0x01;
20923 super::vals::Apb1hlpenrCrslpen(val as u8)
20924 }
20925 #[doc = "FDCAN Peripheral Clocks Enable During CSleep Mode"]
20926 pub fn set_fdcanlpen(&mut self, val: super::vals::Apb1hlpenrCrslpen) {
20927 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
20928 }
20929 }
20930 impl Default for Apb1hlpenr {
20931 fn default() -> Apb1hlpenr {
20932 Apb1hlpenr(0)
20933 }
20934 }
20935 #[doc = "RCC APB2 Sleep Clock Register"]
20936 #[repr(transparent)]
20937 #[derive(Copy, Clone, Eq, PartialEq)]
20938 pub struct C1Apb2lpenr(pub u32);
20939 impl C1Apb2lpenr {
20940 #[doc = "TIM1 peripheral clock enable during CSleep mode"]
20941 pub const fn tim1lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
20942>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
20943 let val = (self.0 >> 0usize) & 0x01;
20944 super::vals::C1Apb2lpenrTim1lpen(val as u8)
20945 }
20946<<<<<<< HEAD
13105 #[doc = "Stream enable / flag stream ready when read low"] 20947 #[doc = "Stream enable / flag stream ready when read low"]
13106 pub fn set_en(&mut self, val: bool) { 20948 pub fn set_en(&mut self, val: bool) {
13107 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); 20949 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
13108 } 20950 }
13109 #[doc = "Direct mode error interrupt enable"] 20951 #[doc = "Direct mode error interrupt enable"]
13110 pub const fn dmeie(&self) -> bool { 20952 pub const fn dmeie(&self) -> bool {
20953=======
20954 #[doc = "TIM1 peripheral clock enable during CSleep mode"]
20955 pub fn set_tim1lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
20956 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
20957 }
20958 #[doc = "TIM8 peripheral clock enable during CSleep mode"]
20959 pub const fn tim8lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
20960>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
13111 let val = (self.0 >> 1usize) & 0x01; 20961 let val = (self.0 >> 1usize) & 0x01;
13112 val != 0 20962 super::vals::C1Apb2lpenrTim1lpen(val as u8)
13113 } 20963 }
20964<<<<<<< HEAD
13114 #[doc = "Direct mode error interrupt enable"] 20965 #[doc = "Direct mode error interrupt enable"]
13115 pub fn set_dmeie(&mut self, val: bool) { 20966 pub fn set_dmeie(&mut self, val: bool) {
13116 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); 20967 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
@@ -13292,10 +21143,575 @@ pub mod dma_v2 {
13292 impl Default for Ndtr { 21143 impl Default for Ndtr {
13293 fn default() -> Ndtr { 21144 fn default() -> Ndtr {
13294 Ndtr(0) 21145 Ndtr(0)
21146=======
21147 #[doc = "TIM8 peripheral clock enable during CSleep mode"]
21148 pub fn set_tim8lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21149 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
21150 }
21151 #[doc = "USART1 Peripheral Clocks Enable During CSleep Mode"]
21152 pub const fn usart1lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21153 let val = (self.0 >> 4usize) & 0x01;
21154 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21155 }
21156 #[doc = "USART1 Peripheral Clocks Enable During CSleep Mode"]
21157 pub fn set_usart1lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21158 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
21159 }
21160 #[doc = "USART6 Peripheral Clocks Enable During CSleep Mode"]
21161 pub const fn usart6lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21162 let val = (self.0 >> 5usize) & 0x01;
21163 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21164 }
21165 #[doc = "USART6 Peripheral Clocks Enable During CSleep Mode"]
21166 pub fn set_usart6lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21167 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
21168 }
21169 #[doc = "SPI1 Peripheral Clocks Enable During CSleep Mode"]
21170 pub const fn spi1lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21171 let val = (self.0 >> 12usize) & 0x01;
21172 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21173 }
21174 #[doc = "SPI1 Peripheral Clocks Enable During CSleep Mode"]
21175 pub fn set_spi1lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21176 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
21177 }
21178 #[doc = "SPI4 Peripheral Clocks Enable During CSleep Mode"]
21179 pub const fn spi4lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21180 let val = (self.0 >> 13usize) & 0x01;
21181 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21182 }
21183 #[doc = "SPI4 Peripheral Clocks Enable During CSleep Mode"]
21184 pub fn set_spi4lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21185 self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize);
21186 }
21187 #[doc = "TIM15 peripheral clock enable during CSleep mode"]
21188 pub const fn tim15lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21189 let val = (self.0 >> 16usize) & 0x01;
21190 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21191 }
21192 #[doc = "TIM15 peripheral clock enable during CSleep mode"]
21193 pub fn set_tim15lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21194 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
21195 }
21196 #[doc = "TIM16 peripheral clock enable during CSleep mode"]
21197 pub const fn tim16lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21198 let val = (self.0 >> 17usize) & 0x01;
21199 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21200 }
21201 #[doc = "TIM16 peripheral clock enable during CSleep mode"]
21202 pub fn set_tim16lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21203 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
21204 }
21205 #[doc = "TIM17 peripheral clock enable during CSleep mode"]
21206 pub const fn tim17lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21207 let val = (self.0 >> 18usize) & 0x01;
21208 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21209 }
21210 #[doc = "TIM17 peripheral clock enable during CSleep mode"]
21211 pub fn set_tim17lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21212 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
21213 }
21214 #[doc = "SPI5 Peripheral Clocks Enable During CSleep Mode"]
21215 pub const fn spi5lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21216 let val = (self.0 >> 20usize) & 0x01;
21217 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21218 }
21219 #[doc = "SPI5 Peripheral Clocks Enable During CSleep Mode"]
21220 pub fn set_spi5lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21221 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.0 as u32) & 0x01) << 20usize);
21222 }
21223 #[doc = "SAI1 Peripheral Clocks Enable During CSleep Mode"]
21224 pub const fn sai1lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21225 let val = (self.0 >> 22usize) & 0x01;
21226 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21227 }
21228 #[doc = "SAI1 Peripheral Clocks Enable During CSleep Mode"]
21229 pub fn set_sai1lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21230 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
21231 }
21232 #[doc = "SAI2 Peripheral Clocks Enable During CSleep Mode"]
21233 pub const fn sai2lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21234 let val = (self.0 >> 23usize) & 0x01;
21235 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21236 }
21237 #[doc = "SAI2 Peripheral Clocks Enable During CSleep Mode"]
21238 pub fn set_sai2lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21239 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
21240 }
21241 #[doc = "SAI3 Peripheral Clocks Enable During CSleep Mode"]
21242 pub const fn sai3lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21243 let val = (self.0 >> 24usize) & 0x01;
21244 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21245 }
21246 #[doc = "SAI3 Peripheral Clocks Enable During CSleep Mode"]
21247 pub fn set_sai3lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21248 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
21249 }
21250 #[doc = "DFSDM1 Peripheral Clocks Enable During CSleep Mode"]
21251 pub const fn dfsdm1lpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21252 let val = (self.0 >> 28usize) & 0x01;
21253 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21254 }
21255 #[doc = "DFSDM1 Peripheral Clocks Enable During CSleep Mode"]
21256 pub fn set_dfsdm1lpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21257 self.0 = (self.0 & !(0x01 << 28usize)) | (((val.0 as u32) & 0x01) << 28usize);
21258 }
21259 #[doc = "HRTIM peripheral clock enable during CSleep mode"]
21260 pub const fn hrtimlpen(&self) -> super::vals::C1Apb2lpenrTim1lpen {
21261 let val = (self.0 >> 29usize) & 0x01;
21262 super::vals::C1Apb2lpenrTim1lpen(val as u8)
21263 }
21264 #[doc = "HRTIM peripheral clock enable during CSleep mode"]
21265 pub fn set_hrtimlpen(&mut self, val: super::vals::C1Apb2lpenrTim1lpen) {
21266 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
21267 }
21268 }
21269 impl Default for C1Apb2lpenr {
21270 fn default() -> C1Apb2lpenr {
21271 C1Apb2lpenr(0)
21272 }
21273 }
21274 #[doc = "RCC Domain 1 Clock Configuration Register"]
21275 #[repr(transparent)]
21276 #[derive(Copy, Clone, Eq, PartialEq)]
21277 pub struct D1cfgr(pub u32);
21278 impl D1cfgr {
21279 #[doc = "D1 domain AHB prescaler"]
21280 pub const fn hpre(&self) -> super::vals::Hpre {
21281 let val = (self.0 >> 0usize) & 0x0f;
21282 super::vals::Hpre(val as u8)
21283 }
21284 #[doc = "D1 domain AHB prescaler"]
21285 pub fn set_hpre(&mut self, val: super::vals::Hpre) {
21286 self.0 = (self.0 & !(0x0f << 0usize)) | (((val.0 as u32) & 0x0f) << 0usize);
21287 }
21288 #[doc = "D1 domain APB3 prescaler"]
21289 pub const fn d1ppre(&self) -> super::vals::D1ppre {
21290 let val = (self.0 >> 4usize) & 0x07;
21291 super::vals::D1ppre(val as u8)
21292 }
21293 #[doc = "D1 domain APB3 prescaler"]
21294 pub fn set_d1ppre(&mut self, val: super::vals::D1ppre) {
21295 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
21296 }
21297 #[doc = "D1 domain Core prescaler"]
21298 pub const fn d1cpre(&self) -> super::vals::Hpre {
21299 let val = (self.0 >> 8usize) & 0x0f;
21300 super::vals::Hpre(val as u8)
21301 }
21302 #[doc = "D1 domain Core prescaler"]
21303 pub fn set_d1cpre(&mut self, val: super::vals::Hpre) {
21304 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize);
21305 }
21306 }
21307 impl Default for D1cfgr {
21308 fn default() -> D1cfgr {
21309 D1cfgr(0)
21310 }
21311 }
21312 #[doc = "RCC APB1 Peripheral Reset Register"]
21313 #[repr(transparent)]
21314 #[derive(Copy, Clone, Eq, PartialEq)]
21315 pub struct Apb1hrstr(pub u32);
21316 impl Apb1hrstr {
21317 #[doc = "Clock Recovery System reset"]
21318 pub const fn crsrst(&self) -> super::vals::Crsrst {
21319 let val = (self.0 >> 1usize) & 0x01;
21320 super::vals::Crsrst(val as u8)
21321 }
21322 #[doc = "Clock Recovery System reset"]
21323 pub fn set_crsrst(&mut self, val: super::vals::Crsrst) {
21324 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
21325 }
21326 #[doc = "SWPMI block reset"]
21327 pub const fn swprst(&self) -> super::vals::Crsrst {
21328 let val = (self.0 >> 2usize) & 0x01;
21329 super::vals::Crsrst(val as u8)
21330 }
21331 #[doc = "SWPMI block reset"]
21332 pub fn set_swprst(&mut self, val: super::vals::Crsrst) {
21333 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
21334 }
21335 #[doc = "OPAMP block reset"]
21336 pub const fn opamprst(&self) -> super::vals::Crsrst {
21337 let val = (self.0 >> 4usize) & 0x01;
21338 super::vals::Crsrst(val as u8)
21339 }
21340 #[doc = "OPAMP block reset"]
21341 pub fn set_opamprst(&mut self, val: super::vals::Crsrst) {
21342 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
21343 }
21344 #[doc = "MDIOS block reset"]
21345 pub const fn mdiosrst(&self) -> super::vals::Crsrst {
21346 let val = (self.0 >> 5usize) & 0x01;
21347 super::vals::Crsrst(val as u8)
21348 }
21349 #[doc = "MDIOS block reset"]
21350 pub fn set_mdiosrst(&mut self, val: super::vals::Crsrst) {
21351 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
21352 }
21353 #[doc = "FDCAN block reset"]
21354 pub const fn fdcanrst(&self) -> super::vals::Crsrst {
21355 let val = (self.0 >> 8usize) & 0x01;
21356 super::vals::Crsrst(val as u8)
21357 }
21358 #[doc = "FDCAN block reset"]
21359 pub fn set_fdcanrst(&mut self, val: super::vals::Crsrst) {
21360 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
21361 }
21362 }
21363 impl Default for Apb1hrstr {
21364 fn default() -> Apb1hrstr {
21365 Apb1hrstr(0)
21366 }
21367 }
21368 #[doc = "RCC APB1 Peripheral Reset Register"]
21369 #[repr(transparent)]
21370 #[derive(Copy, Clone, Eq, PartialEq)]
21371 pub struct Apb1lrstr(pub u32);
21372 impl Apb1lrstr {
21373 #[doc = "TIM block reset"]
21374 pub const fn tim2rst(&self) -> super::vals::Tim2rst {
21375 let val = (self.0 >> 0usize) & 0x01;
21376 super::vals::Tim2rst(val as u8)
21377 }
21378 #[doc = "TIM block reset"]
21379 pub fn set_tim2rst(&mut self, val: super::vals::Tim2rst) {
21380 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
21381 }
21382 #[doc = "TIM block reset"]
21383 pub const fn tim3rst(&self) -> super::vals::Tim2rst {
21384 let val = (self.0 >> 1usize) & 0x01;
21385 super::vals::Tim2rst(val as u8)
21386 }
21387 #[doc = "TIM block reset"]
21388 pub fn set_tim3rst(&mut self, val: super::vals::Tim2rst) {
21389 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
21390 }
21391 #[doc = "TIM block reset"]
21392 pub const fn tim4rst(&self) -> super::vals::Tim2rst {
21393 let val = (self.0 >> 2usize) & 0x01;
21394 super::vals::Tim2rst(val as u8)
21395 }
21396 #[doc = "TIM block reset"]
21397 pub fn set_tim4rst(&mut self, val: super::vals::Tim2rst) {
21398 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
21399 }
21400 #[doc = "TIM block reset"]
21401 pub const fn tim5rst(&self) -> super::vals::Tim2rst {
21402 let val = (self.0 >> 3usize) & 0x01;
21403 super::vals::Tim2rst(val as u8)
21404 }
21405 #[doc = "TIM block reset"]
21406 pub fn set_tim5rst(&mut self, val: super::vals::Tim2rst) {
21407 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
21408 }
21409 #[doc = "TIM block reset"]
21410 pub const fn tim6rst(&self) -> super::vals::Tim2rst {
21411 let val = (self.0 >> 4usize) & 0x01;
21412 super::vals::Tim2rst(val as u8)
21413 }
21414 #[doc = "TIM block reset"]
21415 pub fn set_tim6rst(&mut self, val: super::vals::Tim2rst) {
21416 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
21417 }
21418 #[doc = "TIM block reset"]
21419 pub const fn tim7rst(&self) -> super::vals::Tim2rst {
21420 let val = (self.0 >> 5usize) & 0x01;
21421 super::vals::Tim2rst(val as u8)
21422 }
21423 #[doc = "TIM block reset"]
21424 pub fn set_tim7rst(&mut self, val: super::vals::Tim2rst) {
21425 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
21426 }
21427 #[doc = "TIM block reset"]
21428 pub const fn tim12rst(&self) -> super::vals::Tim2rst {
21429 let val = (self.0 >> 6usize) & 0x01;
21430 super::vals::Tim2rst(val as u8)
21431 }
21432 #[doc = "TIM block reset"]
21433 pub fn set_tim12rst(&mut self, val: super::vals::Tim2rst) {
21434 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
21435 }
21436 #[doc = "TIM block reset"]
21437 pub const fn tim13rst(&self) -> super::vals::Tim2rst {
21438 let val = (self.0 >> 7usize) & 0x01;
21439 super::vals::Tim2rst(val as u8)
21440 }
21441 #[doc = "TIM block reset"]
21442 pub fn set_tim13rst(&mut self, val: super::vals::Tim2rst) {
21443 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
21444 }
21445 #[doc = "TIM block reset"]
21446 pub const fn tim14rst(&self) -> super::vals::Tim2rst {
21447 let val = (self.0 >> 8usize) & 0x01;
21448 super::vals::Tim2rst(val as u8)
21449 }
21450 #[doc = "TIM block reset"]
21451 pub fn set_tim14rst(&mut self, val: super::vals::Tim2rst) {
21452 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
21453 }
21454 #[doc = "TIM block reset"]
21455 pub const fn lptim1rst(&self) -> super::vals::Tim2rst {
21456 let val = (self.0 >> 9usize) & 0x01;
21457 super::vals::Tim2rst(val as u8)
21458 }
21459 #[doc = "TIM block reset"]
21460 pub fn set_lptim1rst(&mut self, val: super::vals::Tim2rst) {
21461 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
21462 }
21463 #[doc = "SPI2 block reset"]
21464 pub const fn spi2rst(&self) -> super::vals::Tim2rst {
21465 let val = (self.0 >> 14usize) & 0x01;
21466 super::vals::Tim2rst(val as u8)
21467 }
21468 #[doc = "SPI2 block reset"]
21469 pub fn set_spi2rst(&mut self, val: super::vals::Tim2rst) {
21470 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
21471 }
21472 #[doc = "SPI3 block reset"]
21473 pub const fn spi3rst(&self) -> super::vals::Tim2rst {
21474 let val = (self.0 >> 15usize) & 0x01;
21475 super::vals::Tim2rst(val as u8)
21476 }
21477 #[doc = "SPI3 block reset"]
21478 pub fn set_spi3rst(&mut self, val: super::vals::Tim2rst) {
21479 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
21480 }
21481 #[doc = "SPDIFRX block reset"]
21482 pub const fn spdifrxrst(&self) -> super::vals::Tim2rst {
21483 let val = (self.0 >> 16usize) & 0x01;
21484 super::vals::Tim2rst(val as u8)
21485 }
21486 #[doc = "SPDIFRX block reset"]
21487 pub fn set_spdifrxrst(&mut self, val: super::vals::Tim2rst) {
21488 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
21489 }
21490 #[doc = "USART2 block reset"]
21491 pub const fn usart2rst(&self) -> super::vals::Tim2rst {
21492 let val = (self.0 >> 17usize) & 0x01;
21493 super::vals::Tim2rst(val as u8)
21494 }
21495 #[doc = "USART2 block reset"]
21496 pub fn set_usart2rst(&mut self, val: super::vals::Tim2rst) {
21497 self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize);
21498 }
21499 #[doc = "USART3 block reset"]
21500 pub const fn usart3rst(&self) -> super::vals::Tim2rst {
21501 let val = (self.0 >> 18usize) & 0x01;
21502 super::vals::Tim2rst(val as u8)
21503 }
21504 #[doc = "USART3 block reset"]
21505 pub fn set_usart3rst(&mut self, val: super::vals::Tim2rst) {
21506 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
21507 }
21508 #[doc = "UART4 block reset"]
21509 pub const fn uart4rst(&self) -> super::vals::Tim2rst {
21510 let val = (self.0 >> 19usize) & 0x01;
21511 super::vals::Tim2rst(val as u8)
21512 }
21513 #[doc = "UART4 block reset"]
21514 pub fn set_uart4rst(&mut self, val: super::vals::Tim2rst) {
21515 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
21516 }
21517 #[doc = "UART5 block reset"]
21518 pub const fn uart5rst(&self) -> super::vals::Tim2rst {
21519 let val = (self.0 >> 20usize) & 0x01;
21520 super::vals::Tim2rst(val as u8)
21521 }
21522 #[doc = "UART5 block reset"]
21523 pub fn set_uart5rst(&mut self, val: super::vals::Tim2rst) {
21524 self.0 = (self.0 & !(0x01 << 20usize)) | (((val.0 as u32) & 0x01) << 20usize);
21525 }
21526 #[doc = "I2C1 block reset"]
21527 pub const fn i2c1rst(&self) -> super::vals::Tim2rst {
21528 let val = (self.0 >> 21usize) & 0x01;
21529 super::vals::Tim2rst(val as u8)
21530 }
21531 #[doc = "I2C1 block reset"]
21532 pub fn set_i2c1rst(&mut self, val: super::vals::Tim2rst) {
21533 self.0 = (self.0 & !(0x01 << 21usize)) | (((val.0 as u32) & 0x01) << 21usize);
21534 }
21535 #[doc = "I2C2 block reset"]
21536 pub const fn i2c2rst(&self) -> super::vals::Tim2rst {
21537 let val = (self.0 >> 22usize) & 0x01;
21538 super::vals::Tim2rst(val as u8)
21539 }
21540 #[doc = "I2C2 block reset"]
21541 pub fn set_i2c2rst(&mut self, val: super::vals::Tim2rst) {
21542 self.0 = (self.0 & !(0x01 << 22usize)) | (((val.0 as u32) & 0x01) << 22usize);
21543 }
21544 #[doc = "I2C3 block reset"]
21545 pub const fn i2c3rst(&self) -> super::vals::Tim2rst {
21546 let val = (self.0 >> 23usize) & 0x01;
21547 super::vals::Tim2rst(val as u8)
21548 }
21549 #[doc = "I2C3 block reset"]
21550 pub fn set_i2c3rst(&mut self, val: super::vals::Tim2rst) {
21551 self.0 = (self.0 & !(0x01 << 23usize)) | (((val.0 as u32) & 0x01) << 23usize);
21552 }
21553 #[doc = "HDMI-CEC block reset"]
21554 pub const fn cecrst(&self) -> super::vals::Tim2rst {
21555 let val = (self.0 >> 27usize) & 0x01;
21556 super::vals::Tim2rst(val as u8)
21557 }
21558 #[doc = "HDMI-CEC block reset"]
21559 pub fn set_cecrst(&mut self, val: super::vals::Tim2rst) {
21560 self.0 = (self.0 & !(0x01 << 27usize)) | (((val.0 as u32) & 0x01) << 27usize);
21561 }
21562 #[doc = "DAC1 and 2 Blocks Reset"]
21563 pub const fn dac12rst(&self) -> super::vals::Tim2rst {
21564 let val = (self.0 >> 29usize) & 0x01;
21565 super::vals::Tim2rst(val as u8)
21566 }
21567 #[doc = "DAC1 and 2 Blocks Reset"]
21568 pub fn set_dac12rst(&mut self, val: super::vals::Tim2rst) {
21569 self.0 = (self.0 & !(0x01 << 29usize)) | (((val.0 as u32) & 0x01) << 29usize);
21570 }
21571 #[doc = "UART7 block reset"]
21572 pub const fn uart7rst(&self) -> super::vals::Tim2rst {
21573 let val = (self.0 >> 30usize) & 0x01;
21574 super::vals::Tim2rst(val as u8)
21575 }
21576 #[doc = "UART7 block reset"]
21577 pub fn set_uart7rst(&mut self, val: super::vals::Tim2rst) {
21578 self.0 = (self.0 & !(0x01 << 30usize)) | (((val.0 as u32) & 0x01) << 30usize);
21579 }
21580 #[doc = "UART8 block reset"]
21581 pub const fn uart8rst(&self) -> super::vals::Tim2rst {
21582 let val = (self.0 >> 31usize) & 0x01;
21583 super::vals::Tim2rst(val as u8)
21584 }
21585 #[doc = "UART8 block reset"]
21586 pub fn set_uart8rst(&mut self, val: super::vals::Tim2rst) {
21587 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
21588 }
21589 }
21590 impl Default for Apb1lrstr {
21591 fn default() -> Apb1lrstr {
21592 Apb1lrstr(0)
21593 }
21594 }
21595 #[doc = "RCC PLLs Clock Source Selection Register"]
21596 #[repr(transparent)]
21597 #[derive(Copy, Clone, Eq, PartialEq)]
21598 pub struct Pllckselr(pub u32);
21599 impl Pllckselr {
21600 #[doc = "DIVMx and PLLs clock source selection"]
21601 pub const fn pllsrc(&self) -> super::vals::Pllsrc {
21602 let val = (self.0 >> 0usize) & 0x03;
21603 super::vals::Pllsrc(val as u8)
21604 }
21605 #[doc = "DIVMx and PLLs clock source selection"]
21606 pub fn set_pllsrc(&mut self, val: super::vals::Pllsrc) {
21607 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
21608 }
21609 #[doc = "Prescaler for PLL1"]
21610 pub fn divm(&self, n: usize) -> u8 {
21611 assert!(n < 3usize);
21612 let offs = 4usize + n * 8usize;
21613 let val = (self.0 >> offs) & 0x3f;
21614 val as u8
21615 }
21616 #[doc = "Prescaler for PLL1"]
21617 pub fn set_divm(&mut self, n: usize, val: u8) {
21618 assert!(n < 3usize);
21619 let offs = 4usize + n * 8usize;
21620 self.0 = (self.0 & !(0x3f << offs)) | (((val as u32) & 0x3f) << offs);
21621 }
21622 }
21623 impl Default for Pllckselr {
21624 fn default() -> Pllckselr {
21625 Pllckselr(0)
21626 }
21627 }
21628 #[doc = "RCC Domain 2 Kernel Clock Configuration Register"]
21629 #[repr(transparent)]
21630 #[derive(Copy, Clone, Eq, PartialEq)]
21631 pub struct D2ccip1r(pub u32);
21632 impl D2ccip1r {
21633 #[doc = "SAI1 and DFSDM1 kernel Aclk clock source selection"]
21634 pub const fn sai1sel(&self) -> super::vals::Sai1sel {
21635 let val = (self.0 >> 0usize) & 0x07;
21636 super::vals::Sai1sel(val as u8)
21637 }
21638 #[doc = "SAI1 and DFSDM1 kernel Aclk clock source selection"]
21639 pub fn set_sai1sel(&mut self, val: super::vals::Sai1sel) {
21640 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
21641 }
21642 #[doc = "SAI2 and SAI3 kernel clock source selection"]
21643 pub const fn sai23sel(&self) -> super::vals::Sai1sel {
21644 let val = (self.0 >> 6usize) & 0x07;
21645 super::vals::Sai1sel(val as u8)
21646 }
21647 #[doc = "SAI2 and SAI3 kernel clock source selection"]
21648 pub fn set_sai23sel(&mut self, val: super::vals::Sai1sel) {
21649 self.0 = (self.0 & !(0x07 << 6usize)) | (((val.0 as u32) & 0x07) << 6usize);
21650 }
21651 #[doc = "SPI/I2S1,2 and 3 kernel clock source selection"]
21652 pub const fn spi123sel(&self) -> super::vals::Sai1sel {
21653 let val = (self.0 >> 12usize) & 0x07;
21654 super::vals::Sai1sel(val as u8)
21655 }
21656 #[doc = "SPI/I2S1,2 and 3 kernel clock source selection"]
21657 pub fn set_spi123sel(&mut self, val: super::vals::Sai1sel) {
21658 self.0 = (self.0 & !(0x07 << 12usize)) | (((val.0 as u32) & 0x07) << 12usize);
21659 }
21660 #[doc = "SPI4 and 5 kernel clock source selection"]
21661 pub const fn spi45sel(&self) -> super::vals::Spi45sel {
21662 let val = (self.0 >> 16usize) & 0x07;
21663 super::vals::Spi45sel(val as u8)
21664 }
21665 #[doc = "SPI4 and 5 kernel clock source selection"]
21666 pub fn set_spi45sel(&mut self, val: super::vals::Spi45sel) {
21667 self.0 = (self.0 & !(0x07 << 16usize)) | (((val.0 as u32) & 0x07) << 16usize);
21668 }
21669 #[doc = "SPDIFRX kernel clock source selection"]
21670 pub const fn spdifsel(&self) -> super::vals::Spdifsel {
21671 let val = (self.0 >> 20usize) & 0x03;
21672 super::vals::Spdifsel(val as u8)
21673 }
21674 #[doc = "SPDIFRX kernel clock source selection"]
21675 pub fn set_spdifsel(&mut self, val: super::vals::Spdifsel) {
21676 self.0 = (self.0 & !(0x03 << 20usize)) | (((val.0 as u32) & 0x03) << 20usize);
21677 }
21678 #[doc = "DFSDM1 kernel Clk clock source selection"]
21679 pub const fn dfsdm1sel(&self) -> super::vals::Dfsdm1sel {
21680 let val = (self.0 >> 24usize) & 0x01;
21681 super::vals::Dfsdm1sel(val as u8)
21682 }
21683 #[doc = "DFSDM1 kernel Clk clock source selection"]
21684 pub fn set_dfsdm1sel(&mut self, val: super::vals::Dfsdm1sel) {
21685 self.0 = (self.0 & !(0x01 << 24usize)) | (((val.0 as u32) & 0x01) << 24usize);
21686 }
21687 #[doc = "FDCAN kernel clock source selection"]
21688 pub const fn fdcansel(&self) -> super::vals::Fdcansel {
21689 let val = (self.0 >> 28usize) & 0x03;
21690 super::vals::Fdcansel(val as u8)
21691 }
21692 #[doc = "FDCAN kernel clock source selection"]
21693 pub fn set_fdcansel(&mut self, val: super::vals::Fdcansel) {
21694 self.0 = (self.0 & !(0x03 << 28usize)) | (((val.0 as u32) & 0x03) << 28usize);
21695 }
21696 #[doc = "SWPMI kernel clock source selection"]
21697 pub const fn swpsel(&self) -> super::vals::Swpsel {
21698 let val = (self.0 >> 31usize) & 0x01;
21699 super::vals::Swpsel(val as u8)
21700 }
21701 #[doc = "SWPMI kernel clock source selection"]
21702 pub fn set_swpsel(&mut self, val: super::vals::Swpsel) {
21703 self.0 = (self.0 & !(0x01 << 31usize)) | (((val.0 as u32) & 0x01) << 31usize);
21704 }
21705 }
21706 impl Default for D2ccip1r {
21707 fn default() -> D2ccip1r {
21708 D2ccip1r(0)
21709>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
13295 } 21710 }
13296 } 21711 }
13297 } 21712 }
13298} 21713}
21714<<<<<<< HEAD
13299pub mod sdmmc_v2 { 21715pub mod sdmmc_v2 {
13300 use crate::generic::*; 21716 use crate::generic::*;
13301 #[doc = "SDMMC"] 21717 #[doc = "SDMMC"]
@@ -13310,6 +21726,92 @@ pub mod sdmmc_v2 {
13310 } 21726 }
13311 #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] 21727 #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."]
13312 pub fn clkcr(self) -> Reg<regs::Clkcr, RW> { 21728 pub fn clkcr(self) -> Reg<regs::Clkcr, RW> {
21729=======
21730pub mod generic {
21731 use core::marker::PhantomData;
21732 #[derive(Copy, Clone)]
21733 pub struct RW;
21734 #[derive(Copy, Clone)]
21735 pub struct R;
21736 #[derive(Copy, Clone)]
21737 pub struct W;
21738 mod sealed {
21739 use super::*;
21740 pub trait Access {}
21741 impl Access for R {}
21742 impl Access for W {}
21743 impl Access for RW {}
21744 }
21745 pub trait Access: sealed::Access + Copy {}
21746 impl Access for R {}
21747 impl Access for W {}
21748 impl Access for RW {}
21749 pub trait Read: Access {}
21750 impl Read for RW {}
21751 impl Read for R {}
21752 pub trait Write: Access {}
21753 impl Write for RW {}
21754 impl Write for W {}
21755 #[derive(Copy, Clone)]
21756 pub struct Reg<T: Copy, A: Access> {
21757 ptr: *mut u8,
21758 phantom: PhantomData<*mut (T, A)>,
21759 }
21760 unsafe impl<T: Copy, A: Access> Send for Reg<T, A> {}
21761 unsafe impl<T: Copy, A: Access> Sync for Reg<T, A> {}
21762 impl<T: Copy, A: Access> Reg<T, A> {
21763 pub fn from_ptr(ptr: *mut u8) -> Self {
21764 Self {
21765 ptr,
21766 phantom: PhantomData,
21767 }
21768 }
21769 pub fn ptr(&self) -> *mut T {
21770 self.ptr as _
21771 }
21772 }
21773 impl<T: Copy, A: Read> Reg<T, A> {
21774 pub unsafe fn read(&self) -> T {
21775 (self.ptr as *mut T).read_volatile()
21776 }
21777 }
21778 impl<T: Copy, A: Write> Reg<T, A> {
21779 pub unsafe fn write_value(&self, val: T) {
21780 (self.ptr as *mut T).write_volatile(val)
21781 }
21782 }
21783 impl<T: Default + Copy, A: Write> Reg<T, A> {
21784 pub unsafe fn write<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
21785 let mut val = Default::default();
21786 let res = f(&mut val);
21787 self.write_value(val);
21788 res
21789 }
21790 }
21791 impl<T: Copy, A: Read + Write> Reg<T, A> {
21792 pub unsafe fn modify<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
21793 let mut val = self.read();
21794 let res = f(&mut val);
21795 self.write_value(val);
21796 res
21797 }
21798 }
21799}
21800pub mod dma_v2 {
21801 use crate::generic::*;
21802 #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
21803 #[derive(Copy, Clone)]
21804 pub struct St(pub *mut u8);
21805 unsafe impl Send for St {}
21806 unsafe impl Sync for St {}
21807 impl St {
21808 #[doc = "stream x configuration register"]
21809 pub fn cr(self) -> Reg<regs::Cr, RW> {
21810 unsafe { Reg::from_ptr(self.0.add(0usize)) }
21811 }
21812 #[doc = "stream x number of data register"]
21813 pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
21814>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
13313 unsafe { Reg::from_ptr(self.0.add(4usize)) } 21815 unsafe { Reg::from_ptr(self.0.add(4usize)) }
13314 } 21816 }
13315 #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] 21817 #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."]
@@ -13329,6 +21831,7 @@ pub mod sdmmc_v2 {
13329 assert!(n < 4usize); 21831 assert!(n < 4usize);
13330 unsafe { Reg::from_ptr(self.0.add(20usize + n * 4usize)) } 21832 unsafe { Reg::from_ptr(self.0.add(20usize + n * 4usize)) }
13331 } 21833 }
21834<<<<<<< HEAD
13332 #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] 21835 #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."]
13333 pub fn dtimer(self) -> Reg<regs::Dtimer, RW> { 21836 pub fn dtimer(self) -> Reg<regs::Dtimer, RW> {
13334 unsafe { Reg::from_ptr(self.0.add(36usize)) } 21837 unsafe { Reg::from_ptr(self.0.add(36usize)) }
@@ -13675,6 +22178,5579 @@ pub mod sdmmc_v2 {
13675 #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] 22178 #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
13676 pub fn set_idmabndt(&mut self, val: u8) { 22179 pub fn set_idmabndt(&mut self, val: u8) {
13677 self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize); 22180 self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize);
22181=======
22182 }
22183 #[doc = "DMA controller"]
22184 #[derive(Copy, Clone)]
22185 pub struct Dma(pub *mut u8);
22186 unsafe impl Send for Dma {}
22187 unsafe impl Sync for Dma {}
22188 impl Dma {
22189 #[doc = "low interrupt status register"]
22190 pub fn isr(self, n: usize) -> Reg<regs::Isr, R> {
22191 assert!(n < 2usize);
22192 unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
22193 }
22194 #[doc = "low interrupt flag clear register"]
22195 pub fn ifcr(self, n: usize) -> Reg<regs::Ifcr, W> {
22196 assert!(n < 2usize);
22197 unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
22198 }
22199 #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"]
22200 pub fn st(self, n: usize) -> St {
22201 assert!(n < 8usize);
22202 unsafe { St(self.0.add(16usize + n * 24usize)) }
22203 }
22204 }
22205 pub mod regs {
22206 use crate::generic::*;
22207 #[doc = "stream x FIFO control register"]
22208 #[repr(transparent)]
22209 #[derive(Copy, Clone, Eq, PartialEq)]
22210 pub struct Fcr(pub u32);
22211 impl Fcr {
22212 #[doc = "FIFO threshold selection"]
22213 pub const fn fth(&self) -> super::vals::Fth {
22214 let val = (self.0 >> 0usize) & 0x03;
22215 super::vals::Fth(val as u8)
22216 }
22217 #[doc = "FIFO threshold selection"]
22218 pub fn set_fth(&mut self, val: super::vals::Fth) {
22219 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize);
22220 }
22221 #[doc = "Direct mode disable"]
22222 pub const fn dmdis(&self) -> super::vals::Dmdis {
22223 let val = (self.0 >> 2usize) & 0x01;
22224 super::vals::Dmdis(val as u8)
22225 }
22226 #[doc = "Direct mode disable"]
22227 pub fn set_dmdis(&mut self, val: super::vals::Dmdis) {
22228 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
22229 }
22230 #[doc = "FIFO status"]
22231 pub const fn fs(&self) -> super::vals::Fs {
22232 let val = (self.0 >> 3usize) & 0x07;
22233 super::vals::Fs(val as u8)
22234 }
22235 #[doc = "FIFO status"]
22236 pub fn set_fs(&mut self, val: super::vals::Fs) {
22237 self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
22238 }
22239 #[doc = "FIFO error interrupt enable"]
22240 pub const fn feie(&self) -> bool {
22241 let val = (self.0 >> 7usize) & 0x01;
22242 val != 0
22243 }
22244 #[doc = "FIFO error interrupt enable"]
22245 pub fn set_feie(&mut self, val: bool) {
22246 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
22247 }
22248 }
22249 impl Default for Fcr {
22250 fn default() -> Fcr {
22251 Fcr(0)
22252 }
22253 }
22254 #[doc = "stream x configuration register"]
22255 #[repr(transparent)]
22256 #[derive(Copy, Clone, Eq, PartialEq)]
22257 pub struct Cr(pub u32);
22258 impl Cr {
22259 #[doc = "Stream enable / flag stream ready when read low"]
22260 pub const fn en(&self) -> bool {
22261 let val = (self.0 >> 0usize) & 0x01;
22262 val != 0
22263 }
22264 #[doc = "Stream enable / flag stream ready when read low"]
22265 pub fn set_en(&mut self, val: bool) {
22266 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
22267 }
22268 #[doc = "Direct mode error interrupt enable"]
22269 pub const fn dmeie(&self) -> bool {
22270 let val = (self.0 >> 1usize) & 0x01;
22271 val != 0
22272 }
22273 #[doc = "Direct mode error interrupt enable"]
22274 pub fn set_dmeie(&mut self, val: bool) {
22275 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
22276 }
22277 #[doc = "Transfer error interrupt enable"]
22278 pub const fn teie(&self) -> bool {
22279 let val = (self.0 >> 2usize) & 0x01;
22280 val != 0
22281 }
22282 #[doc = "Transfer error interrupt enable"]
22283 pub fn set_teie(&mut self, val: bool) {
22284 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
22285 }
22286 #[doc = "Half transfer interrupt enable"]
22287 pub const fn htie(&self) -> bool {
22288 let val = (self.0 >> 3usize) & 0x01;
22289 val != 0
22290 }
22291 #[doc = "Half transfer interrupt enable"]
22292 pub fn set_htie(&mut self, val: bool) {
22293 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
22294 }
22295 #[doc = "Transfer complete interrupt enable"]
22296 pub const fn tcie(&self) -> bool {
22297 let val = (self.0 >> 4usize) & 0x01;
22298 val != 0
22299 }
22300 #[doc = "Transfer complete interrupt enable"]
22301 pub fn set_tcie(&mut self, val: bool) {
22302 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
22303 }
22304 #[doc = "Peripheral flow controller"]
22305 pub const fn pfctrl(&self) -> super::vals::Pfctrl {
22306 let val = (self.0 >> 5usize) & 0x01;
22307 super::vals::Pfctrl(val as u8)
22308 }
22309 #[doc = "Peripheral flow controller"]
22310 pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) {
22311 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
22312 }
22313 #[doc = "Data transfer direction"]
22314 pub const fn dir(&self) -> super::vals::Dir {
22315 let val = (self.0 >> 6usize) & 0x03;
22316 super::vals::Dir(val as u8)
22317 }
22318 #[doc = "Data transfer direction"]
22319 pub fn set_dir(&mut self, val: super::vals::Dir) {
22320 self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize);
22321 }
22322 #[doc = "Circular mode"]
22323 pub const fn circ(&self) -> super::vals::Circ {
22324 let val = (self.0 >> 8usize) & 0x01;
22325 super::vals::Circ(val as u8)
22326 }
22327 #[doc = "Circular mode"]
22328 pub fn set_circ(&mut self, val: super::vals::Circ) {
22329 self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize);
22330 }
22331 #[doc = "Peripheral increment mode"]
22332 pub const fn pinc(&self) -> super::vals::Inc {
22333 let val = (self.0 >> 9usize) & 0x01;
22334 super::vals::Inc(val as u8)
22335 }
22336 #[doc = "Peripheral increment mode"]
22337 pub fn set_pinc(&mut self, val: super::vals::Inc) {
22338 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
22339 }
22340 #[doc = "Memory increment mode"]
22341 pub const fn minc(&self) -> super::vals::Inc {
22342 let val = (self.0 >> 10usize) & 0x01;
22343 super::vals::Inc(val as u8)
22344 }
22345 #[doc = "Memory increment mode"]
22346 pub fn set_minc(&mut self, val: super::vals::Inc) {
22347 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
22348 }
22349 #[doc = "Peripheral data size"]
22350 pub const fn psize(&self) -> super::vals::Size {
22351 let val = (self.0 >> 11usize) & 0x03;
22352 super::vals::Size(val as u8)
22353 }
22354 #[doc = "Peripheral data size"]
22355 pub fn set_psize(&mut self, val: super::vals::Size) {
22356 self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize);
22357 }
22358 #[doc = "Memory data size"]
22359 pub const fn msize(&self) -> super::vals::Size {
22360 let val = (self.0 >> 13usize) & 0x03;
22361 super::vals::Size(val as u8)
22362 }
22363 #[doc = "Memory data size"]
22364 pub fn set_msize(&mut self, val: super::vals::Size) {
22365 self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize);
22366 }
22367 #[doc = "Peripheral increment offset size"]
22368 pub const fn pincos(&self) -> super::vals::Pincos {
22369 let val = (self.0 >> 15usize) & 0x01;
22370 super::vals::Pincos(val as u8)
22371 }
22372 #[doc = "Peripheral increment offset size"]
22373 pub fn set_pincos(&mut self, val: super::vals::Pincos) {
22374 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
22375 }
22376 #[doc = "Priority level"]
22377 pub const fn pl(&self) -> super::vals::Pl {
22378 let val = (self.0 >> 16usize) & 0x03;
22379 super::vals::Pl(val as u8)
22380 }
22381 #[doc = "Priority level"]
22382 pub fn set_pl(&mut self, val: super::vals::Pl) {
22383 self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize);
22384 }
22385 #[doc = "Double buffer mode"]
22386 pub const fn dbm(&self) -> super::vals::Dbm {
22387 let val = (self.0 >> 18usize) & 0x01;
22388 super::vals::Dbm(val as u8)
22389 }
22390 #[doc = "Double buffer mode"]
22391 pub fn set_dbm(&mut self, val: super::vals::Dbm) {
22392 self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize);
22393 }
22394 #[doc = "Current target (only in double buffer mode)"]
22395 pub const fn ct(&self) -> super::vals::Ct {
22396 let val = (self.0 >> 19usize) & 0x01;
22397 super::vals::Ct(val as u8)
22398 }
22399 #[doc = "Current target (only in double buffer mode)"]
22400 pub fn set_ct(&mut self, val: super::vals::Ct) {
22401 self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize);
22402 }
22403 #[doc = "Peripheral burst transfer configuration"]
22404 pub const fn pburst(&self) -> super::vals::Burst {
22405 let val = (self.0 >> 21usize) & 0x03;
22406 super::vals::Burst(val as u8)
22407 }
22408 #[doc = "Peripheral burst transfer configuration"]
22409 pub fn set_pburst(&mut self, val: super::vals::Burst) {
22410 self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize);
22411 }
22412 #[doc = "Memory burst transfer configuration"]
22413 pub const fn mburst(&self) -> super::vals::Burst {
22414 let val = (self.0 >> 23usize) & 0x03;
22415 super::vals::Burst(val as u8)
22416 }
22417 #[doc = "Memory burst transfer configuration"]
22418 pub fn set_mburst(&mut self, val: super::vals::Burst) {
22419 self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize);
22420 }
22421 #[doc = "Channel selection"]
22422 pub const fn chsel(&self) -> u8 {
22423 let val = (self.0 >> 25usize) & 0x0f;
22424 val as u8
22425 }
22426 #[doc = "Channel selection"]
22427 pub fn set_chsel(&mut self, val: u8) {
22428 self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize);
22429 }
22430 }
22431 impl Default for Cr {
22432 fn default() -> Cr {
22433 Cr(0)
22434 }
22435 }
22436 #[doc = "low interrupt flag clear register"]
22437 #[repr(transparent)]
22438 #[derive(Copy, Clone, Eq, PartialEq)]
22439 pub struct Ifcr(pub u32);
22440 impl Ifcr {
22441 #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"]
22442 pub fn cfeif(&self, n: usize) -> bool {
22443 assert!(n < 4usize);
22444 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22445 let val = (self.0 >> offs) & 0x01;
22446 val != 0
22447 }
22448 #[doc = "Stream x clear FIFO error interrupt flag (x = 3..0)"]
22449 pub fn set_cfeif(&mut self, n: usize, val: bool) {
22450 assert!(n < 4usize);
22451 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22452 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22453 }
22454 #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"]
22455 pub fn cdmeif(&self, n: usize) -> bool {
22456 assert!(n < 4usize);
22457 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22458 let val = (self.0 >> offs) & 0x01;
22459 val != 0
22460 }
22461 #[doc = "Stream x clear direct mode error interrupt flag (x = 3..0)"]
22462 pub fn set_cdmeif(&mut self, n: usize, val: bool) {
22463 assert!(n < 4usize);
22464 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22465 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22466 }
22467 #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"]
22468 pub fn cteif(&self, n: usize) -> bool {
22469 assert!(n < 4usize);
22470 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22471 let val = (self.0 >> offs) & 0x01;
22472 val != 0
22473 }
22474 #[doc = "Stream x clear transfer error interrupt flag (x = 3..0)"]
22475 pub fn set_cteif(&mut self, n: usize, val: bool) {
22476 assert!(n < 4usize);
22477 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22478 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22479 }
22480 #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"]
22481 pub fn chtif(&self, n: usize) -> bool {
22482 assert!(n < 4usize);
22483 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22484 let val = (self.0 >> offs) & 0x01;
22485 val != 0
22486 }
22487 #[doc = "Stream x clear half transfer interrupt flag (x = 3..0)"]
22488 pub fn set_chtif(&mut self, n: usize, val: bool) {
22489 assert!(n < 4usize);
22490 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22491 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22492 }
22493 #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"]
22494 pub fn ctcif(&self, n: usize) -> bool {
22495 assert!(n < 4usize);
22496 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22497 let val = (self.0 >> offs) & 0x01;
22498 val != 0
22499 }
22500 #[doc = "Stream x clear transfer complete interrupt flag (x = 3..0)"]
22501 pub fn set_ctcif(&mut self, n: usize, val: bool) {
22502 assert!(n < 4usize);
22503 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22504 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22505 }
22506 }
22507 impl Default for Ifcr {
22508 fn default() -> Ifcr {
22509 Ifcr(0)
22510 }
22511 }
22512 #[doc = "low interrupt status register"]
22513 #[repr(transparent)]
22514 #[derive(Copy, Clone, Eq, PartialEq)]
22515 pub struct Isr(pub u32);
22516 impl Isr {
22517 #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
22518 pub fn feif(&self, n: usize) -> bool {
22519 assert!(n < 4usize);
22520 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22521 let val = (self.0 >> offs) & 0x01;
22522 val != 0
22523 }
22524 #[doc = "Stream x FIFO error interrupt flag (x=3..0)"]
22525 pub fn set_feif(&mut self, n: usize, val: bool) {
22526 assert!(n < 4usize);
22527 let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22528 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22529 }
22530 #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
22531 pub fn dmeif(&self, n: usize) -> bool {
22532 assert!(n < 4usize);
22533 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22534 let val = (self.0 >> offs) & 0x01;
22535 val != 0
22536 }
22537 #[doc = "Stream x direct mode error interrupt flag (x=3..0)"]
22538 pub fn set_dmeif(&mut self, n: usize, val: bool) {
22539 assert!(n < 4usize);
22540 let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22541 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22542 }
22543 #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
22544 pub fn teif(&self, n: usize) -> bool {
22545 assert!(n < 4usize);
22546 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22547 let val = (self.0 >> offs) & 0x01;
22548 val != 0
22549 }
22550 #[doc = "Stream x transfer error interrupt flag (x=3..0)"]
22551 pub fn set_teif(&mut self, n: usize, val: bool) {
22552 assert!(n < 4usize);
22553 let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22554 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22555 }
22556 #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
22557 pub fn htif(&self, n: usize) -> bool {
22558 assert!(n < 4usize);
22559 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22560 let val = (self.0 >> offs) & 0x01;
22561 val != 0
22562 }
22563 #[doc = "Stream x half transfer interrupt flag (x=3..0)"]
22564 pub fn set_htif(&mut self, n: usize, val: bool) {
22565 assert!(n < 4usize);
22566 let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22567 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22568 }
22569 #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
22570 pub fn tcif(&self, n: usize) -> bool {
22571 assert!(n < 4usize);
22572 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22573 let val = (self.0 >> offs) & 0x01;
22574 val != 0
22575 }
22576 #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"]
22577 pub fn set_tcif(&mut self, n: usize, val: bool) {
22578 assert!(n < 4usize);
22579 let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize);
22580 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22581 }
22582 }
22583 impl Default for Isr {
22584 fn default() -> Isr {
22585 Isr(0)
22586 }
22587 }
22588 #[doc = "stream x number of data register"]
22589 #[repr(transparent)]
22590 #[derive(Copy, Clone, Eq, PartialEq)]
22591 pub struct Ndtr(pub u32);
22592 impl Ndtr {
22593 #[doc = "Number of data items to transfer"]
22594 pub const fn ndt(&self) -> u16 {
22595 let val = (self.0 >> 0usize) & 0xffff;
22596 val as u16
22597 }
22598 #[doc = "Number of data items to transfer"]
22599 pub fn set_ndt(&mut self, val: u16) {
22600 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
22601 }
22602 }
22603 impl Default for Ndtr {
22604 fn default() -> Ndtr {
22605 Ndtr(0)
22606 }
22607 }
22608 }
22609 pub mod vals {
22610 use crate::generic::*;
22611 #[repr(transparent)]
22612 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22613 pub struct Dbm(pub u8);
22614 impl Dbm {
22615 #[doc = "No buffer switching at the end of transfer"]
22616 pub const DISABLED: Self = Self(0);
22617 #[doc = "Memory target switched at the end of the DMA transfer"]
22618 pub const ENABLED: Self = Self(0x01);
22619 }
22620 #[repr(transparent)]
22621 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22622 pub struct Burst(pub u8);
22623 impl Burst {
22624 #[doc = "Single transfer"]
22625 pub const SINGLE: Self = Self(0);
22626 #[doc = "Incremental burst of 4 beats"]
22627 pub const INCR4: Self = Self(0x01);
22628 #[doc = "Incremental burst of 8 beats"]
22629 pub const INCR8: Self = Self(0x02);
22630 #[doc = "Incremental burst of 16 beats"]
22631 pub const INCR16: Self = Self(0x03);
22632 }
22633 #[repr(transparent)]
22634 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22635 pub struct Dmdis(pub u8);
22636 impl Dmdis {
22637 #[doc = "Direct mode is enabled"]
22638 pub const ENABLED: Self = Self(0);
22639 #[doc = "Direct mode is disabled"]
22640 pub const DISABLED: Self = Self(0x01);
22641 }
22642 #[repr(transparent)]
22643 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22644 pub struct Pl(pub u8);
22645 impl Pl {
22646 #[doc = "Low"]
22647 pub const LOW: Self = Self(0);
22648 #[doc = "Medium"]
22649 pub const MEDIUM: Self = Self(0x01);
22650 #[doc = "High"]
22651 pub const HIGH: Self = Self(0x02);
22652 #[doc = "Very high"]
22653 pub const VERYHIGH: Self = Self(0x03);
22654 }
22655 #[repr(transparent)]
22656 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22657 pub struct Pincos(pub u8);
22658 impl Pincos {
22659 #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"]
22660 pub const PSIZE: Self = Self(0);
22661 #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"]
22662 pub const FIXED4: Self = Self(0x01);
22663 }
22664 #[repr(transparent)]
22665 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22666 pub struct Pfctrl(pub u8);
22667 impl Pfctrl {
22668 #[doc = "The DMA is the flow controller"]
22669 pub const DMA: Self = Self(0);
22670 #[doc = "The peripheral is the flow controller"]
22671 pub const PERIPHERAL: Self = Self(0x01);
22672 }
22673 #[repr(transparent)]
22674 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22675 pub struct Size(pub u8);
22676 impl Size {
22677 #[doc = "Byte (8-bit)"]
22678 pub const BITS8: Self = Self(0);
22679 #[doc = "Half-word (16-bit)"]
22680 pub const BITS16: Self = Self(0x01);
22681 #[doc = "Word (32-bit)"]
22682 pub const BITS32: Self = Self(0x02);
22683 }
22684 #[repr(transparent)]
22685 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22686 pub struct Fth(pub u8);
22687 impl Fth {
22688 #[doc = "1/4 full FIFO"]
22689 pub const QUARTER: Self = Self(0);
22690 #[doc = "1/2 full FIFO"]
22691 pub const HALF: Self = Self(0x01);
22692 #[doc = "3/4 full FIFO"]
22693 pub const THREEQUARTERS: Self = Self(0x02);
22694 #[doc = "Full FIFO"]
22695 pub const FULL: Self = Self(0x03);
22696 }
22697 #[repr(transparent)]
22698 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22699 pub struct Fs(pub u8);
22700 impl Fs {
22701 #[doc = "0 < fifo_level < 1/4"]
22702 pub const QUARTER1: Self = Self(0);
22703 #[doc = "1/4 <= fifo_level < 1/2"]
22704 pub const QUARTER2: Self = Self(0x01);
22705 #[doc = "1/2 <= fifo_level < 3/4"]
22706 pub const QUARTER3: Self = Self(0x02);
22707 #[doc = "3/4 <= fifo_level < full"]
22708 pub const QUARTER4: Self = Self(0x03);
22709 #[doc = "FIFO is empty"]
22710 pub const EMPTY: Self = Self(0x04);
22711 #[doc = "FIFO is full"]
22712 pub const FULL: Self = Self(0x05);
22713 }
22714 #[repr(transparent)]
22715 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22716 pub struct Ct(pub u8);
22717 impl Ct {
22718 #[doc = "The current target memory is Memory 0"]
22719 pub const MEMORY0: Self = Self(0);
22720 #[doc = "The current target memory is Memory 1"]
22721 pub const MEMORY1: Self = Self(0x01);
22722 }
22723 #[repr(transparent)]
22724 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22725 pub struct Circ(pub u8);
22726 impl Circ {
22727 #[doc = "Circular mode disabled"]
22728 pub const DISABLED: Self = Self(0);
22729 #[doc = "Circular mode enabled"]
22730 pub const ENABLED: Self = Self(0x01);
22731 }
22732 #[repr(transparent)]
22733 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22734 pub struct Inc(pub u8);
22735 impl Inc {
22736 #[doc = "Address pointer is fixed"]
22737 pub const FIXED: Self = Self(0);
22738 #[doc = "Address pointer is incremented after each data transfer"]
22739 pub const INCREMENTED: Self = Self(0x01);
22740 }
22741 #[repr(transparent)]
22742 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22743 pub struct Dir(pub u8);
22744 impl Dir {
22745 #[doc = "Peripheral-to-memory"]
22746 pub const PERIPHERALTOMEMORY: Self = Self(0);
22747 #[doc = "Memory-to-peripheral"]
22748 pub const MEMORYTOPERIPHERAL: Self = Self(0x01);
22749 #[doc = "Memory-to-memory"]
22750 pub const MEMORYTOMEMORY: Self = Self(0x02);
22751 }
22752 }
22753}
22754pub mod exti_v1 {
22755 use crate::generic::*;
22756 #[doc = "External interrupt/event controller"]
22757 #[derive(Copy, Clone)]
22758 pub struct Exti(pub *mut u8);
22759 unsafe impl Send for Exti {}
22760 unsafe impl Sync for Exti {}
22761 impl Exti {
22762 #[doc = "Interrupt mask register (EXTI_IMR)"]
22763 pub fn imr(self) -> Reg<regs::Imr, RW> {
22764 unsafe { Reg::from_ptr(self.0.add(0usize)) }
22765 }
22766 #[doc = "Event mask register (EXTI_EMR)"]
22767 pub fn emr(self) -> Reg<regs::Emr, RW> {
22768 unsafe { Reg::from_ptr(self.0.add(4usize)) }
22769 }
22770 #[doc = "Rising Trigger selection register (EXTI_RTSR)"]
22771 pub fn rtsr(self) -> Reg<regs::Rtsr, RW> {
22772 unsafe { Reg::from_ptr(self.0.add(8usize)) }
22773 }
22774 #[doc = "Falling Trigger selection register (EXTI_FTSR)"]
22775 pub fn ftsr(self) -> Reg<regs::Ftsr, RW> {
22776 unsafe { Reg::from_ptr(self.0.add(12usize)) }
22777 }
22778 #[doc = "Software interrupt event register (EXTI_SWIER)"]
22779 pub fn swier(self) -> Reg<regs::Swier, RW> {
22780 unsafe { Reg::from_ptr(self.0.add(16usize)) }
22781 }
22782 #[doc = "Pending register (EXTI_PR)"]
22783 pub fn pr(self) -> Reg<regs::Pr, RW> {
22784 unsafe { Reg::from_ptr(self.0.add(20usize)) }
22785 }
22786 }
22787 pub mod regs {
22788 use crate::generic::*;
22789 #[doc = "Pending register (EXTI_PR)"]
22790 #[repr(transparent)]
22791 #[derive(Copy, Clone, Eq, PartialEq)]
22792 pub struct Pr(pub u32);
22793 impl Pr {
22794 #[doc = "Pending bit 0"]
22795 pub fn pr(&self, n: usize) -> bool {
22796 assert!(n < 23usize);
22797 let offs = 0usize + n * 1usize;
22798 let val = (self.0 >> offs) & 0x01;
22799 val != 0
22800 }
22801 #[doc = "Pending bit 0"]
22802 pub fn set_pr(&mut self, n: usize, val: bool) {
22803 assert!(n < 23usize);
22804 let offs = 0usize + n * 1usize;
22805 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22806 }
22807 }
22808 impl Default for Pr {
22809 fn default() -> Pr {
22810 Pr(0)
22811 }
22812 }
22813 #[doc = "Event mask register (EXTI_EMR)"]
22814 #[repr(transparent)]
22815 #[derive(Copy, Clone, Eq, PartialEq)]
22816 pub struct Emr(pub u32);
22817 impl Emr {
22818 #[doc = "Event Mask on line 0"]
22819 pub fn mr(&self, n: usize) -> super::vals::Mr {
22820 assert!(n < 23usize);
22821 let offs = 0usize + n * 1usize;
22822 let val = (self.0 >> offs) & 0x01;
22823 super::vals::Mr(val as u8)
22824 }
22825 #[doc = "Event Mask on line 0"]
22826 pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) {
22827 assert!(n < 23usize);
22828 let offs = 0usize + n * 1usize;
22829 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
22830 }
22831 }
22832 impl Default for Emr {
22833 fn default() -> Emr {
22834 Emr(0)
22835 }
22836 }
22837 #[doc = "Rising Trigger selection register (EXTI_RTSR)"]
22838 #[repr(transparent)]
22839 #[derive(Copy, Clone, Eq, PartialEq)]
22840 pub struct Rtsr(pub u32);
22841 impl Rtsr {
22842 #[doc = "Rising trigger event configuration of line 0"]
22843 pub fn tr(&self, n: usize) -> super::vals::Tr {
22844 assert!(n < 23usize);
22845 let offs = 0usize + n * 1usize;
22846 let val = (self.0 >> offs) & 0x01;
22847 super::vals::Tr(val as u8)
22848 }
22849 #[doc = "Rising trigger event configuration of line 0"]
22850 pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) {
22851 assert!(n < 23usize);
22852 let offs = 0usize + n * 1usize;
22853 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
22854 }
22855 }
22856 impl Default for Rtsr {
22857 fn default() -> Rtsr {
22858 Rtsr(0)
22859 }
22860 }
22861 #[doc = "Falling Trigger selection register (EXTI_FTSR)"]
22862 #[repr(transparent)]
22863 #[derive(Copy, Clone, Eq, PartialEq)]
22864 pub struct Ftsr(pub u32);
22865 impl Ftsr {
22866 #[doc = "Falling trigger event configuration of line 0"]
22867 pub fn tr(&self, n: usize) -> super::vals::Tr {
22868 assert!(n < 23usize);
22869 let offs = 0usize + n * 1usize;
22870 let val = (self.0 >> offs) & 0x01;
22871 super::vals::Tr(val as u8)
22872 }
22873 #[doc = "Falling trigger event configuration of line 0"]
22874 pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) {
22875 assert!(n < 23usize);
22876 let offs = 0usize + n * 1usize;
22877 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
22878 }
22879 }
22880 impl Default for Ftsr {
22881 fn default() -> Ftsr {
22882 Ftsr(0)
22883 }
22884 }
22885 #[doc = "Software interrupt event register (EXTI_SWIER)"]
22886 #[repr(transparent)]
22887 #[derive(Copy, Clone, Eq, PartialEq)]
22888 pub struct Swier(pub u32);
22889 impl Swier {
22890 #[doc = "Software Interrupt on line 0"]
22891 pub fn swier(&self, n: usize) -> bool {
22892 assert!(n < 23usize);
22893 let offs = 0usize + n * 1usize;
22894 let val = (self.0 >> offs) & 0x01;
22895 val != 0
22896 }
22897 #[doc = "Software Interrupt on line 0"]
22898 pub fn set_swier(&mut self, n: usize, val: bool) {
22899 assert!(n < 23usize);
22900 let offs = 0usize + n * 1usize;
22901 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
22902 }
22903 }
22904 impl Default for Swier {
22905 fn default() -> Swier {
22906 Swier(0)
22907 }
22908 }
22909 #[doc = "Interrupt mask register (EXTI_IMR)"]
22910 #[repr(transparent)]
22911 #[derive(Copy, Clone, Eq, PartialEq)]
22912 pub struct Imr(pub u32);
22913 impl Imr {
22914 #[doc = "Interrupt Mask on line 0"]
22915 pub fn mr(&self, n: usize) -> super::vals::Mr {
22916 assert!(n < 23usize);
22917 let offs = 0usize + n * 1usize;
22918 let val = (self.0 >> offs) & 0x01;
22919 super::vals::Mr(val as u8)
22920 }
22921 #[doc = "Interrupt Mask on line 0"]
22922 pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) {
22923 assert!(n < 23usize);
22924 let offs = 0usize + n * 1usize;
22925 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
22926 }
22927 }
22928 impl Default for Imr {
22929 fn default() -> Imr {
22930 Imr(0)
22931 }
22932 }
22933 }
22934 pub mod vals {
22935 use crate::generic::*;
22936 #[repr(transparent)]
22937 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22938 pub struct Swierw(pub u8);
22939 impl Swierw {
22940 #[doc = "Generates an interrupt request"]
22941 pub const PEND: Self = Self(0x01);
22942 }
22943 #[repr(transparent)]
22944 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22945 pub struct Tr(pub u8);
22946 impl Tr {
22947 #[doc = "Falling edge trigger is disabled"]
22948 pub const DISABLED: Self = Self(0);
22949 #[doc = "Falling edge trigger is enabled"]
22950 pub const ENABLED: Self = Self(0x01);
22951 }
22952 #[repr(transparent)]
22953 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22954 pub struct Mr(pub u8);
22955 impl Mr {
22956 #[doc = "Interrupt request line is masked"]
22957 pub const MASKED: Self = Self(0);
22958 #[doc = "Interrupt request line is unmasked"]
22959 pub const UNMASKED: Self = Self(0x01);
22960 }
22961 #[repr(transparent)]
22962 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22963 pub struct Prr(pub u8);
22964 impl Prr {
22965 #[doc = "No trigger request occurred"]
22966 pub const NOTPENDING: Self = Self(0);
22967 #[doc = "Selected trigger request occurred"]
22968 pub const PENDING: Self = Self(0x01);
22969 }
22970 #[repr(transparent)]
22971 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
22972 pub struct Prw(pub u8);
22973 impl Prw {
22974 #[doc = "Clears pending bit"]
22975 pub const CLEAR: Self = Self(0x01);
22976 }
22977 }
22978}
22979pub mod spi_v1 {
22980 use crate::generic::*;
22981 #[doc = "Serial peripheral interface"]
22982 #[derive(Copy, Clone)]
22983 pub struct Spi(pub *mut u8);
22984 unsafe impl Send for Spi {}
22985 unsafe impl Sync for Spi {}
22986 impl Spi {
22987 #[doc = "control register 1"]
22988 pub fn cr1(self) -> Reg<regs::Cr1, RW> {
22989 unsafe { Reg::from_ptr(self.0.add(0usize)) }
22990 }
22991 #[doc = "control register 2"]
22992 pub fn cr2(self) -> Reg<regs::Cr2, RW> {
22993 unsafe { Reg::from_ptr(self.0.add(4usize)) }
22994 }
22995 #[doc = "status register"]
22996 pub fn sr(self) -> Reg<regs::Sr, RW> {
22997 unsafe { Reg::from_ptr(self.0.add(8usize)) }
22998 }
22999 #[doc = "data register"]
23000 pub fn dr(self) -> Reg<regs::Dr, RW> {
23001 unsafe { Reg::from_ptr(self.0.add(12usize)) }
23002 }
23003 #[doc = "CRC polynomial register"]
23004 pub fn crcpr(self) -> Reg<regs::Crcpr, RW> {
23005 unsafe { Reg::from_ptr(self.0.add(16usize)) }
23006 }
23007 #[doc = "RX CRC register"]
23008 pub fn rxcrcr(self) -> Reg<regs::Rxcrcr, R> {
23009 unsafe { Reg::from_ptr(self.0.add(20usize)) }
23010 }
23011 #[doc = "TX CRC register"]
23012 pub fn txcrcr(self) -> Reg<regs::Txcrcr, R> {
23013 unsafe { Reg::from_ptr(self.0.add(24usize)) }
23014 }
23015 }
23016 pub mod vals {
23017 use crate::generic::*;
23018 #[repr(transparent)]
23019 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23020 pub struct Dff(pub u8);
23021 impl Dff {
23022 #[doc = "8-bit data frame format is selected for transmission/reception"]
23023 pub const EIGHTBIT: Self = Self(0);
23024 #[doc = "16-bit data frame format is selected for transmission/reception"]
23025 pub const SIXTEENBIT: Self = Self(0x01);
23026 }
23027 #[repr(transparent)]
23028 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23029 pub struct Cpol(pub u8);
23030 impl Cpol {
23031 #[doc = "CK to 0 when idle"]
23032 pub const IDLELOW: Self = Self(0);
23033 #[doc = "CK to 1 when idle"]
23034 pub const IDLEHIGH: Self = Self(0x01);
23035 }
23036 #[repr(transparent)]
23037 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23038 pub struct Mstr(pub u8);
23039 impl Mstr {
23040 #[doc = "Slave configuration"]
23041 pub const SLAVE: Self = Self(0);
23042 #[doc = "Master configuration"]
23043 pub const MASTER: Self = Self(0x01);
23044 }
23045 #[repr(transparent)]
23046 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23047 pub struct Br(pub u8);
23048 impl Br {
23049 #[doc = "f_PCLK / 2"]
23050 pub const DIV2: Self = Self(0);
23051 #[doc = "f_PCLK / 4"]
23052 pub const DIV4: Self = Self(0x01);
23053 #[doc = "f_PCLK / 8"]
23054 pub const DIV8: Self = Self(0x02);
23055 #[doc = "f_PCLK / 16"]
23056 pub const DIV16: Self = Self(0x03);
23057 #[doc = "f_PCLK / 32"]
23058 pub const DIV32: Self = Self(0x04);
23059 #[doc = "f_PCLK / 64"]
23060 pub const DIV64: Self = Self(0x05);
23061 #[doc = "f_PCLK / 128"]
23062 pub const DIV128: Self = Self(0x06);
23063 #[doc = "f_PCLK / 256"]
23064 pub const DIV256: Self = Self(0x07);
23065 }
23066 #[repr(transparent)]
23067 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23068 pub struct Bidioe(pub u8);
23069 impl Bidioe {
23070 #[doc = "Output disabled (receive-only mode)"]
23071 pub const OUTPUTDISABLED: Self = Self(0);
23072 #[doc = "Output enabled (transmit-only mode)"]
23073 pub const OUTPUTENABLED: Self = Self(0x01);
23074 }
23075 #[repr(transparent)]
23076 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23077 pub struct Frf(pub u8);
23078 impl Frf {
23079 #[doc = "SPI Motorola mode"]
23080 pub const MOTOROLA: Self = Self(0);
23081 #[doc = "SPI TI mode"]
23082 pub const TI: Self = Self(0x01);
23083 }
23084 #[repr(transparent)]
23085 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23086 pub struct Cpha(pub u8);
23087 impl Cpha {
23088 #[doc = "The first clock transition is the first data capture edge"]
23089 pub const FIRSTEDGE: Self = Self(0);
23090 #[doc = "The second clock transition is the first data capture edge"]
23091 pub const SECONDEDGE: Self = Self(0x01);
23092 }
23093 #[repr(transparent)]
23094 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23095 pub struct Rxonly(pub u8);
23096 impl Rxonly {
23097 #[doc = "Full duplex (Transmit and receive)"]
23098 pub const FULLDUPLEX: Self = Self(0);
23099 #[doc = "Output disabled (Receive-only mode)"]
23100 pub const OUTPUTDISABLED: Self = Self(0x01);
23101 }
23102 #[repr(transparent)]
23103 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23104 pub struct Frer(pub u8);
23105 impl Frer {
23106 #[doc = "No frame format error"]
23107 pub const NOERROR: Self = Self(0);
23108 #[doc = "A frame format error occurred"]
23109 pub const ERROR: Self = Self(0x01);
23110 }
23111 #[repr(transparent)]
23112 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23113 pub struct Crcnext(pub u8);
23114 impl Crcnext {
23115 #[doc = "Next transmit value is from Tx buffer"]
23116 pub const TXBUFFER: Self = Self(0);
23117 #[doc = "Next transmit value is from Tx CRC register"]
23118 pub const CRC: Self = Self(0x01);
23119 }
23120 #[repr(transparent)]
23121 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23122 pub struct Bidimode(pub u8);
23123 impl Bidimode {
23124 #[doc = "2-line unidirectional data mode selected"]
23125 pub const UNIDIRECTIONAL: Self = Self(0);
23126 #[doc = "1-line bidirectional data mode selected"]
23127 pub const BIDIRECTIONAL: Self = Self(0x01);
23128 }
23129 #[repr(transparent)]
23130 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23131 pub struct Iscfg(pub u8);
23132 impl Iscfg {
23133 #[doc = "Slave - transmit"]
23134 pub const SLAVETX: Self = Self(0);
23135 #[doc = "Slave - receive"]
23136 pub const SLAVERX: Self = Self(0x01);
23137 #[doc = "Master - transmit"]
23138 pub const MASTERTX: Self = Self(0x02);
23139 #[doc = "Master - receive"]
23140 pub const MASTERRX: Self = Self(0x03);
23141 }
23142 #[repr(transparent)]
23143 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23144 pub struct Lsbfirst(pub u8);
23145 impl Lsbfirst {
23146 #[doc = "Data is transmitted/received with the MSB first"]
23147 pub const MSBFIRST: Self = Self(0);
23148 #[doc = "Data is transmitted/received with the LSB first"]
23149 pub const LSBFIRST: Self = Self(0x01);
23150 }
23151 }
23152 pub mod regs {
23153 use crate::generic::*;
23154 #[doc = "control register 1"]
23155 #[repr(transparent)]
23156 #[derive(Copy, Clone, Eq, PartialEq)]
23157 pub struct Cr1(pub u32);
23158 impl Cr1 {
23159 #[doc = "Clock phase"]
23160 pub const fn cpha(&self) -> super::vals::Cpha {
23161 let val = (self.0 >> 0usize) & 0x01;
23162 super::vals::Cpha(val as u8)
23163 }
23164 #[doc = "Clock phase"]
23165 pub fn set_cpha(&mut self, val: super::vals::Cpha) {
23166 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
23167 }
23168 #[doc = "Clock polarity"]
23169 pub const fn cpol(&self) -> super::vals::Cpol {
23170 let val = (self.0 >> 1usize) & 0x01;
23171 super::vals::Cpol(val as u8)
23172 }
23173 #[doc = "Clock polarity"]
23174 pub fn set_cpol(&mut self, val: super::vals::Cpol) {
23175 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
23176 }
23177 #[doc = "Master selection"]
23178 pub const fn mstr(&self) -> super::vals::Mstr {
23179 let val = (self.0 >> 2usize) & 0x01;
23180 super::vals::Mstr(val as u8)
23181 }
23182 #[doc = "Master selection"]
23183 pub fn set_mstr(&mut self, val: super::vals::Mstr) {
23184 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
23185 }
23186 #[doc = "Baud rate control"]
23187 pub const fn br(&self) -> super::vals::Br {
23188 let val = (self.0 >> 3usize) & 0x07;
23189 super::vals::Br(val as u8)
23190 }
23191 #[doc = "Baud rate control"]
23192 pub fn set_br(&mut self, val: super::vals::Br) {
23193 self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
23194 }
23195 #[doc = "SPI enable"]
23196 pub const fn spe(&self) -> bool {
23197 let val = (self.0 >> 6usize) & 0x01;
23198 val != 0
23199 }
23200 #[doc = "SPI enable"]
23201 pub fn set_spe(&mut self, val: bool) {
23202 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
23203 }
23204 #[doc = "Frame format"]
23205 pub const fn lsbfirst(&self) -> super::vals::Lsbfirst {
23206 let val = (self.0 >> 7usize) & 0x01;
23207 super::vals::Lsbfirst(val as u8)
23208 }
23209 #[doc = "Frame format"]
23210 pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) {
23211 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
23212 }
23213 #[doc = "Internal slave select"]
23214 pub const fn ssi(&self) -> bool {
23215 let val = (self.0 >> 8usize) & 0x01;
23216 val != 0
23217 }
23218 #[doc = "Internal slave select"]
23219 pub fn set_ssi(&mut self, val: bool) {
23220 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
23221 }
23222 #[doc = "Software slave management"]
23223 pub const fn ssm(&self) -> bool {
23224 let val = (self.0 >> 9usize) & 0x01;
23225 val != 0
23226 }
23227 #[doc = "Software slave management"]
23228 pub fn set_ssm(&mut self, val: bool) {
23229 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
23230 }
23231 #[doc = "Receive only"]
23232 pub const fn rxonly(&self) -> super::vals::Rxonly {
23233 let val = (self.0 >> 10usize) & 0x01;
23234 super::vals::Rxonly(val as u8)
23235 }
23236 #[doc = "Receive only"]
23237 pub fn set_rxonly(&mut self, val: super::vals::Rxonly) {
23238 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
23239 }
23240 #[doc = "Data frame format"]
23241 pub const fn dff(&self) -> super::vals::Dff {
23242 let val = (self.0 >> 11usize) & 0x01;
23243 super::vals::Dff(val as u8)
23244 }
23245 #[doc = "Data frame format"]
23246 pub fn set_dff(&mut self, val: super::vals::Dff) {
23247 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
23248 }
23249 #[doc = "CRC transfer next"]
23250 pub const fn crcnext(&self) -> super::vals::Crcnext {
23251 let val = (self.0 >> 12usize) & 0x01;
23252 super::vals::Crcnext(val as u8)
23253 }
23254 #[doc = "CRC transfer next"]
23255 pub fn set_crcnext(&mut self, val: super::vals::Crcnext) {
23256 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
23257 }
23258 #[doc = "Hardware CRC calculation enable"]
23259 pub const fn crcen(&self) -> bool {
23260 let val = (self.0 >> 13usize) & 0x01;
23261 val != 0
23262 }
23263 #[doc = "Hardware CRC calculation enable"]
23264 pub fn set_crcen(&mut self, val: bool) {
23265 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
23266 }
23267 #[doc = "Output enable in bidirectional mode"]
23268 pub const fn bidioe(&self) -> super::vals::Bidioe {
23269 let val = (self.0 >> 14usize) & 0x01;
23270 super::vals::Bidioe(val as u8)
23271 }
23272 #[doc = "Output enable in bidirectional mode"]
23273 pub fn set_bidioe(&mut self, val: super::vals::Bidioe) {
23274 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
23275 }
23276 #[doc = "Bidirectional data mode enable"]
23277 pub const fn bidimode(&self) -> super::vals::Bidimode {
23278 let val = (self.0 >> 15usize) & 0x01;
23279 super::vals::Bidimode(val as u8)
23280 }
23281 #[doc = "Bidirectional data mode enable"]
23282 pub fn set_bidimode(&mut self, val: super::vals::Bidimode) {
23283 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
23284 }
23285 }
23286 impl Default for Cr1 {
23287 fn default() -> Cr1 {
23288 Cr1(0)
23289 }
23290 }
23291 #[doc = "control register 2"]
23292 #[repr(transparent)]
23293 #[derive(Copy, Clone, Eq, PartialEq)]
23294 pub struct Cr2(pub u32);
23295 impl Cr2 {
23296 #[doc = "Rx buffer DMA enable"]
23297 pub const fn rxdmaen(&self) -> bool {
23298 let val = (self.0 >> 0usize) & 0x01;
23299 val != 0
23300 }
23301 #[doc = "Rx buffer DMA enable"]
23302 pub fn set_rxdmaen(&mut self, val: bool) {
23303 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
23304 }
23305 #[doc = "Tx buffer DMA enable"]
23306 pub const fn txdmaen(&self) -> bool {
23307 let val = (self.0 >> 1usize) & 0x01;
23308 val != 0
23309 }
23310 #[doc = "Tx buffer DMA enable"]
23311 pub fn set_txdmaen(&mut self, val: bool) {
23312 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
23313 }
23314 #[doc = "SS output enable"]
23315 pub const fn ssoe(&self) -> bool {
23316 let val = (self.0 >> 2usize) & 0x01;
23317 val != 0
23318 }
23319 #[doc = "SS output enable"]
23320 pub fn set_ssoe(&mut self, val: bool) {
23321 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
23322 }
23323 #[doc = "Frame format"]
23324 pub const fn frf(&self) -> super::vals::Frf {
23325 let val = (self.0 >> 4usize) & 0x01;
23326 super::vals::Frf(val as u8)
23327 }
23328 #[doc = "Frame format"]
23329 pub fn set_frf(&mut self, val: super::vals::Frf) {
23330 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
23331 }
23332 #[doc = "Error interrupt enable"]
23333 pub const fn errie(&self) -> bool {
23334 let val = (self.0 >> 5usize) & 0x01;
23335 val != 0
23336 }
23337 #[doc = "Error interrupt enable"]
23338 pub fn set_errie(&mut self, val: bool) {
23339 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
23340 }
23341 #[doc = "RX buffer not empty interrupt enable"]
23342 pub const fn rxneie(&self) -> bool {
23343 let val = (self.0 >> 6usize) & 0x01;
23344 val != 0
23345 }
23346 #[doc = "RX buffer not empty interrupt enable"]
23347 pub fn set_rxneie(&mut self, val: bool) {
23348 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
23349 }
23350 #[doc = "Tx buffer empty interrupt enable"]
23351 pub const fn txeie(&self) -> bool {
23352 let val = (self.0 >> 7usize) & 0x01;
23353 val != 0
23354 }
23355 #[doc = "Tx buffer empty interrupt enable"]
23356 pub fn set_txeie(&mut self, val: bool) {
23357 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
23358 }
23359 }
23360 impl Default for Cr2 {
23361 fn default() -> Cr2 {
23362 Cr2(0)
23363 }
23364 }
23365 #[doc = "data register"]
23366 #[repr(transparent)]
23367 #[derive(Copy, Clone, Eq, PartialEq)]
23368 pub struct Dr(pub u32);
23369 impl Dr {
23370 #[doc = "Data register"]
23371 pub const fn dr(&self) -> u16 {
23372 let val = (self.0 >> 0usize) & 0xffff;
23373 val as u16
23374 }
23375 #[doc = "Data register"]
23376 pub fn set_dr(&mut self, val: u16) {
23377 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
23378 }
23379 }
23380 impl Default for Dr {
23381 fn default() -> Dr {
23382 Dr(0)
23383 }
23384 }
23385 #[doc = "status register"]
23386 #[repr(transparent)]
23387 #[derive(Copy, Clone, Eq, PartialEq)]
23388 pub struct Sr(pub u32);
23389 impl Sr {
23390 #[doc = "Receive buffer not empty"]
23391 pub const fn rxne(&self) -> bool {
23392 let val = (self.0 >> 0usize) & 0x01;
23393 val != 0
23394 }
23395 #[doc = "Receive buffer not empty"]
23396 pub fn set_rxne(&mut self, val: bool) {
23397 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
23398 }
23399 #[doc = "Transmit buffer empty"]
23400 pub const fn txe(&self) -> bool {
23401 let val = (self.0 >> 1usize) & 0x01;
23402 val != 0
23403 }
23404 #[doc = "Transmit buffer empty"]
23405 pub fn set_txe(&mut self, val: bool) {
23406 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
23407 }
23408 #[doc = "CRC error flag"]
23409 pub const fn crcerr(&self) -> bool {
23410 let val = (self.0 >> 4usize) & 0x01;
23411 val != 0
23412 }
23413 #[doc = "CRC error flag"]
23414 pub fn set_crcerr(&mut self, val: bool) {
23415 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
23416 }
23417 #[doc = "Mode fault"]
23418 pub const fn modf(&self) -> bool {
23419 let val = (self.0 >> 5usize) & 0x01;
23420 val != 0
23421 }
23422 #[doc = "Mode fault"]
23423 pub fn set_modf(&mut self, val: bool) {
23424 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
23425 }
23426 #[doc = "Overrun flag"]
23427 pub const fn ovr(&self) -> bool {
23428 let val = (self.0 >> 6usize) & 0x01;
23429 val != 0
23430 }
23431 #[doc = "Overrun flag"]
23432 pub fn set_ovr(&mut self, val: bool) {
23433 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
23434 }
23435 #[doc = "Busy flag"]
23436 pub const fn bsy(&self) -> bool {
23437 let val = (self.0 >> 7usize) & 0x01;
23438 val != 0
23439 }
23440 #[doc = "Busy flag"]
23441 pub fn set_bsy(&mut self, val: bool) {
23442 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
23443 }
23444 #[doc = "TI frame format error"]
23445 pub const fn fre(&self) -> bool {
23446 let val = (self.0 >> 8usize) & 0x01;
23447 val != 0
23448 }
23449 #[doc = "TI frame format error"]
23450 pub fn set_fre(&mut self, val: bool) {
23451 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
23452 }
23453 }
23454 impl Default for Sr {
23455 fn default() -> Sr {
23456 Sr(0)
23457 }
23458 }
23459 #[doc = "RX CRC register"]
23460 #[repr(transparent)]
23461 #[derive(Copy, Clone, Eq, PartialEq)]
23462 pub struct Rxcrcr(pub u32);
23463 impl Rxcrcr {
23464 #[doc = "Rx CRC register"]
23465 pub const fn rx_crc(&self) -> u16 {
23466 let val = (self.0 >> 0usize) & 0xffff;
23467 val as u16
23468 }
23469 #[doc = "Rx CRC register"]
23470 pub fn set_rx_crc(&mut self, val: u16) {
23471 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
23472 }
23473 }
23474 impl Default for Rxcrcr {
23475 fn default() -> Rxcrcr {
23476 Rxcrcr(0)
23477 }
23478 }
23479 #[doc = "CRC polynomial register"]
23480 #[repr(transparent)]
23481 #[derive(Copy, Clone, Eq, PartialEq)]
23482 pub struct Crcpr(pub u32);
23483 impl Crcpr {
23484 #[doc = "CRC polynomial register"]
23485 pub const fn crcpoly(&self) -> u16 {
23486 let val = (self.0 >> 0usize) & 0xffff;
23487 val as u16
23488 }
23489 #[doc = "CRC polynomial register"]
23490 pub fn set_crcpoly(&mut self, val: u16) {
23491 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
23492 }
23493 }
23494 impl Default for Crcpr {
23495 fn default() -> Crcpr {
23496 Crcpr(0)
23497 }
23498 }
23499 #[doc = "TX CRC register"]
23500 #[repr(transparent)]
23501 #[derive(Copy, Clone, Eq, PartialEq)]
23502 pub struct Txcrcr(pub u32);
23503 impl Txcrcr {
23504 #[doc = "Tx CRC register"]
23505 pub const fn tx_crc(&self) -> u16 {
23506 let val = (self.0 >> 0usize) & 0xffff;
23507 val as u16
23508 }
23509 #[doc = "Tx CRC register"]
23510 pub fn set_tx_crc(&mut self, val: u16) {
23511 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
23512 }
23513 }
23514 impl Default for Txcrcr {
23515 fn default() -> Txcrcr {
23516 Txcrcr(0)
23517 }
23518 }
23519 }
23520}
23521pub mod dma_v1 {
23522 use crate::generic::*;
23523 #[doc = "DMA controller"]
23524 #[derive(Copy, Clone)]
23525 pub struct Dma(pub *mut u8);
23526 unsafe impl Send for Dma {}
23527 unsafe impl Sync for Dma {}
23528 impl Dma {
23529 #[doc = "DMA interrupt status register (DMA_ISR)"]
23530 pub fn isr(self) -> Reg<regs::Isr, R> {
23531 unsafe { Reg::from_ptr(self.0.add(0usize)) }
23532 }
23533 #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
23534 pub fn ifcr(self) -> Reg<regs::Ifcr, W> {
23535 unsafe { Reg::from_ptr(self.0.add(4usize)) }
23536 }
23537 #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
23538 pub fn ch(self, n: usize) -> Ch {
23539 assert!(n < 7usize);
23540 unsafe { Ch(self.0.add(8usize + n * 20usize)) }
23541 }
23542 }
23543 #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
23544 #[derive(Copy, Clone)]
23545 pub struct Ch(pub *mut u8);
23546 unsafe impl Send for Ch {}
23547 unsafe impl Sync for Ch {}
23548 impl Ch {
23549 #[doc = "DMA channel configuration register (DMA_CCR)"]
23550 pub fn cr(self) -> Reg<regs::Cr, RW> {
23551 unsafe { Reg::from_ptr(self.0.add(0usize)) }
23552 }
23553 #[doc = "DMA channel 1 number of data register"]
23554 pub fn ndtr(self) -> Reg<regs::Ndtr, RW> {
23555 unsafe { Reg::from_ptr(self.0.add(4usize)) }
23556 }
23557 #[doc = "DMA channel 1 peripheral address register"]
23558 pub fn par(self) -> Reg<u32, RW> {
23559 unsafe { Reg::from_ptr(self.0.add(8usize)) }
23560 }
23561 #[doc = "DMA channel 1 memory address register"]
23562 pub fn mar(self) -> Reg<u32, RW> {
23563 unsafe { Reg::from_ptr(self.0.add(12usize)) }
23564 }
23565 }
23566 pub mod regs {
23567 use crate::generic::*;
23568 #[doc = "DMA interrupt status register (DMA_ISR)"]
23569 #[repr(transparent)]
23570 #[derive(Copy, Clone, Eq, PartialEq)]
23571 pub struct Isr(pub u32);
23572 impl Isr {
23573 #[doc = "Channel 1 Global interrupt flag"]
23574 pub fn gif(&self, n: usize) -> bool {
23575 assert!(n < 7usize);
23576 let offs = 0usize + n * 4usize;
23577 let val = (self.0 >> offs) & 0x01;
23578 val != 0
23579 }
23580 #[doc = "Channel 1 Global interrupt flag"]
23581 pub fn set_gif(&mut self, n: usize, val: bool) {
23582 assert!(n < 7usize);
23583 let offs = 0usize + n * 4usize;
23584 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
23585 }
23586 #[doc = "Channel 1 Transfer Complete flag"]
23587 pub fn tcif(&self, n: usize) -> bool {
23588 assert!(n < 7usize);
23589 let offs = 1usize + n * 4usize;
23590 let val = (self.0 >> offs) & 0x01;
23591 val != 0
23592 }
23593 #[doc = "Channel 1 Transfer Complete flag"]
23594 pub fn set_tcif(&mut self, n: usize, val: bool) {
23595 assert!(n < 7usize);
23596 let offs = 1usize + n * 4usize;
23597 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
23598 }
23599 #[doc = "Channel 1 Half Transfer Complete flag"]
23600 pub fn htif(&self, n: usize) -> bool {
23601 assert!(n < 7usize);
23602 let offs = 2usize + n * 4usize;
23603 let val = (self.0 >> offs) & 0x01;
23604 val != 0
23605 }
23606 #[doc = "Channel 1 Half Transfer Complete flag"]
23607 pub fn set_htif(&mut self, n: usize, val: bool) {
23608 assert!(n < 7usize);
23609 let offs = 2usize + n * 4usize;
23610 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
23611 }
23612 #[doc = "Channel 1 Transfer Error flag"]
23613 pub fn teif(&self, n: usize) -> bool {
23614 assert!(n < 7usize);
23615 let offs = 3usize + n * 4usize;
23616 let val = (self.0 >> offs) & 0x01;
23617 val != 0
23618 }
23619 #[doc = "Channel 1 Transfer Error flag"]
23620 pub fn set_teif(&mut self, n: usize, val: bool) {
23621 assert!(n < 7usize);
23622 let offs = 3usize + n * 4usize;
23623 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
23624 }
23625 }
23626 impl Default for Isr {
23627 fn default() -> Isr {
23628 Isr(0)
23629 }
23630 }
23631 #[doc = "DMA channel configuration register (DMA_CCR)"]
23632 #[repr(transparent)]
23633 #[derive(Copy, Clone, Eq, PartialEq)]
23634 pub struct Cr(pub u32);
23635 impl Cr {
23636 #[doc = "Channel enable"]
23637 pub const fn en(&self) -> bool {
23638 let val = (self.0 >> 0usize) & 0x01;
23639 val != 0
23640 }
23641 #[doc = "Channel enable"]
23642 pub fn set_en(&mut self, val: bool) {
23643 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
23644 }
23645 #[doc = "Transfer complete interrupt enable"]
23646 pub const fn tcie(&self) -> bool {
23647 let val = (self.0 >> 1usize) & 0x01;
23648 val != 0
23649 }
23650 #[doc = "Transfer complete interrupt enable"]
23651 pub fn set_tcie(&mut self, val: bool) {
23652 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
23653 }
23654 #[doc = "Half Transfer interrupt enable"]
23655 pub const fn htie(&self) -> bool {
23656 let val = (self.0 >> 2usize) & 0x01;
23657 val != 0
23658 }
23659 #[doc = "Half Transfer interrupt enable"]
23660 pub fn set_htie(&mut self, val: bool) {
23661 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
23662 }
23663 #[doc = "Transfer error interrupt enable"]
23664 pub const fn teie(&self) -> bool {
23665 let val = (self.0 >> 3usize) & 0x01;
23666 val != 0
23667 }
23668 #[doc = "Transfer error interrupt enable"]
23669 pub fn set_teie(&mut self, val: bool) {
23670 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
23671 }
23672 #[doc = "Data transfer direction"]
23673 pub const fn dir(&self) -> super::vals::Dir {
23674 let val = (self.0 >> 4usize) & 0x01;
23675 super::vals::Dir(val as u8)
23676 }
23677 #[doc = "Data transfer direction"]
23678 pub fn set_dir(&mut self, val: super::vals::Dir) {
23679 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
23680 }
23681 #[doc = "Circular mode"]
23682 pub const fn circ(&self) -> super::vals::Circ {
23683 let val = (self.0 >> 5usize) & 0x01;
23684 super::vals::Circ(val as u8)
23685 }
23686 #[doc = "Circular mode"]
23687 pub fn set_circ(&mut self, val: super::vals::Circ) {
23688 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
23689 }
23690 #[doc = "Peripheral increment mode"]
23691 pub const fn pinc(&self) -> super::vals::Inc {
23692 let val = (self.0 >> 6usize) & 0x01;
23693 super::vals::Inc(val as u8)
23694 }
23695 #[doc = "Peripheral increment mode"]
23696 pub fn set_pinc(&mut self, val: super::vals::Inc) {
23697 self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize);
23698 }
23699 #[doc = "Memory increment mode"]
23700 pub const fn minc(&self) -> super::vals::Inc {
23701 let val = (self.0 >> 7usize) & 0x01;
23702 super::vals::Inc(val as u8)
23703 }
23704 #[doc = "Memory increment mode"]
23705 pub fn set_minc(&mut self, val: super::vals::Inc) {
23706 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
23707 }
23708 #[doc = "Peripheral size"]
23709 pub const fn psize(&self) -> super::vals::Size {
23710 let val = (self.0 >> 8usize) & 0x03;
23711 super::vals::Size(val as u8)
23712 }
23713 #[doc = "Peripheral size"]
23714 pub fn set_psize(&mut self, val: super::vals::Size) {
23715 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
23716 }
23717 #[doc = "Memory size"]
23718 pub const fn msize(&self) -> super::vals::Size {
23719 let val = (self.0 >> 10usize) & 0x03;
23720 super::vals::Size(val as u8)
23721 }
23722 #[doc = "Memory size"]
23723 pub fn set_msize(&mut self, val: super::vals::Size) {
23724 self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize);
23725 }
23726 #[doc = "Channel Priority level"]
23727 pub const fn pl(&self) -> super::vals::Pl {
23728 let val = (self.0 >> 12usize) & 0x03;
23729 super::vals::Pl(val as u8)
23730 }
23731 #[doc = "Channel Priority level"]
23732 pub fn set_pl(&mut self, val: super::vals::Pl) {
23733 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
23734 }
23735 #[doc = "Memory to memory mode"]
23736 pub const fn mem2mem(&self) -> super::vals::Memmem {
23737 let val = (self.0 >> 14usize) & 0x01;
23738 super::vals::Memmem(val as u8)
23739 }
23740 #[doc = "Memory to memory mode"]
23741 pub fn set_mem2mem(&mut self, val: super::vals::Memmem) {
23742 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
23743 }
23744 }
23745 impl Default for Cr {
23746 fn default() -> Cr {
23747 Cr(0)
23748 }
23749 }
23750 #[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
23751 #[repr(transparent)]
23752 #[derive(Copy, Clone, Eq, PartialEq)]
23753 pub struct Ifcr(pub u32);
23754 impl Ifcr {
23755 #[doc = "Channel 1 Global interrupt clear"]
23756 pub fn cgif(&self, n: usize) -> bool {
23757 assert!(n < 7usize);
23758 let offs = 0usize + n * 4usize;
23759 let val = (self.0 >> offs) & 0x01;
23760 val != 0
23761 }
23762 #[doc = "Channel 1 Global interrupt clear"]
23763 pub fn set_cgif(&mut self, n: usize, val: bool) {
23764 assert!(n < 7usize);
23765 let offs = 0usize + n * 4usize;
23766 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
23767 }
23768 #[doc = "Channel 1 Transfer Complete clear"]
23769 pub fn ctcif(&self, n: usize) -> bool {
23770 assert!(n < 7usize);
23771 let offs = 1usize + n * 4usize;
23772 let val = (self.0 >> offs) & 0x01;
23773 val != 0
23774 }
23775 #[doc = "Channel 1 Transfer Complete clear"]
23776 pub fn set_ctcif(&mut self, n: usize, val: bool) {
23777 assert!(n < 7usize);
23778 let offs = 1usize + n * 4usize;
23779 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
23780 }
23781 #[doc = "Channel 1 Half Transfer clear"]
23782 pub fn chtif(&self, n: usize) -> bool {
23783 assert!(n < 7usize);
23784 let offs = 2usize + n * 4usize;
23785 let val = (self.0 >> offs) & 0x01;
23786 val != 0
23787 }
23788 #[doc = "Channel 1 Half Transfer clear"]
23789 pub fn set_chtif(&mut self, n: usize, val: bool) {
23790 assert!(n < 7usize);
23791 let offs = 2usize + n * 4usize;
23792 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
23793 }
23794 #[doc = "Channel 1 Transfer Error clear"]
23795 pub fn cteif(&self, n: usize) -> bool {
23796 assert!(n < 7usize);
23797 let offs = 3usize + n * 4usize;
23798 let val = (self.0 >> offs) & 0x01;
23799 val != 0
23800 }
23801 #[doc = "Channel 1 Transfer Error clear"]
23802 pub fn set_cteif(&mut self, n: usize, val: bool) {
23803 assert!(n < 7usize);
23804 let offs = 3usize + n * 4usize;
23805 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
23806 }
23807 }
23808 impl Default for Ifcr {
23809 fn default() -> Ifcr {
23810 Ifcr(0)
23811 }
23812 }
23813 #[doc = "DMA channel 1 number of data register"]
23814 #[repr(transparent)]
23815 #[derive(Copy, Clone, Eq, PartialEq)]
23816 pub struct Ndtr(pub u32);
23817 impl Ndtr {
23818 #[doc = "Number of data to transfer"]
23819 pub const fn ndt(&self) -> u16 {
23820 let val = (self.0 >> 0usize) & 0xffff;
23821 val as u16
23822 }
23823 #[doc = "Number of data to transfer"]
23824 pub fn set_ndt(&mut self, val: u16) {
23825 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
23826 }
23827 }
23828 impl Default for Ndtr {
23829 fn default() -> Ndtr {
23830 Ndtr(0)
23831 }
23832 }
23833 }
23834 pub mod vals {
23835 use crate::generic::*;
23836 #[repr(transparent)]
23837 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23838 pub struct Dir(pub u8);
23839 impl Dir {
23840 #[doc = "Read from peripheral"]
23841 pub const FROMPERIPHERAL: Self = Self(0);
23842 #[doc = "Read from memory"]
23843 pub const FROMMEMORY: Self = Self(0x01);
23844 }
23845 #[repr(transparent)]
23846 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23847 pub struct Size(pub u8);
23848 impl Size {
23849 #[doc = "8-bit size"]
23850 pub const BITS8: Self = Self(0);
23851 #[doc = "16-bit size"]
23852 pub const BITS16: Self = Self(0x01);
23853 #[doc = "32-bit size"]
23854 pub const BITS32: Self = Self(0x02);
23855 }
23856 #[repr(transparent)]
23857 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23858 pub struct Inc(pub u8);
23859 impl Inc {
23860 #[doc = "Increment mode disabled"]
23861 pub const DISABLED: Self = Self(0);
23862 #[doc = "Increment mode enabled"]
23863 pub const ENABLED: Self = Self(0x01);
23864 }
23865 #[repr(transparent)]
23866 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23867 pub struct Memmem(pub u8);
23868 impl Memmem {
23869 #[doc = "Memory to memory mode disabled"]
23870 pub const DISABLED: Self = Self(0);
23871 #[doc = "Memory to memory mode enabled"]
23872 pub const ENABLED: Self = Self(0x01);
23873 }
23874 #[repr(transparent)]
23875 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23876 pub struct Circ(pub u8);
23877 impl Circ {
23878 #[doc = "Circular buffer disabled"]
23879 pub const DISABLED: Self = Self(0);
23880 #[doc = "Circular buffer enabled"]
23881 pub const ENABLED: Self = Self(0x01);
23882 }
23883 #[repr(transparent)]
23884 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
23885 pub struct Pl(pub u8);
23886 impl Pl {
23887 #[doc = "Low priority"]
23888 pub const LOW: Self = Self(0);
23889 #[doc = "Medium priority"]
23890 pub const MEDIUM: Self = Self(0x01);
23891 #[doc = "High priority"]
23892 pub const HIGH: Self = Self(0x02);
23893 #[doc = "Very high priority"]
23894 pub const VERYHIGH: Self = Self(0x03);
23895 }
23896 }
23897}
23898pub mod syscfg_f4 {
23899 use crate::generic::*;
23900 #[doc = "System configuration controller"]
23901 #[derive(Copy, Clone)]
23902 pub struct Syscfg(pub *mut u8);
23903 unsafe impl Send for Syscfg {}
23904 unsafe impl Sync for Syscfg {}
23905 impl Syscfg {
23906 #[doc = "memory remap register"]
23907 pub fn memrm(self) -> Reg<regs::Memrm, RW> {
23908 unsafe { Reg::from_ptr(self.0.add(0usize)) }
23909 }
23910 #[doc = "peripheral mode configuration register"]
23911 pub fn pmc(self) -> Reg<regs::Pmc, RW> {
23912 unsafe { Reg::from_ptr(self.0.add(4usize)) }
23913 }
23914 #[doc = "external interrupt configuration register"]
23915 pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
23916 assert!(n < 4usize);
23917 unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
23918 }
23919 #[doc = "Compensation cell control register"]
23920 pub fn cmpcr(self) -> Reg<regs::Cmpcr, R> {
23921 unsafe { Reg::from_ptr(self.0.add(32usize)) }
23922 }
23923 }
23924 pub mod regs {
23925 use crate::generic::*;
23926 #[doc = "external interrupt configuration register"]
23927 #[repr(transparent)]
23928 #[derive(Copy, Clone, Eq, PartialEq)]
23929 pub struct Exticr(pub u32);
23930 impl Exticr {
23931 #[doc = "EXTI x configuration"]
23932 pub fn exti(&self, n: usize) -> u8 {
23933 assert!(n < 4usize);
23934 let offs = 0usize + n * 4usize;
23935 let val = (self.0 >> offs) & 0x0f;
23936 val as u8
23937 }
23938 #[doc = "EXTI x configuration"]
23939 pub fn set_exti(&mut self, n: usize, val: u8) {
23940 assert!(n < 4usize);
23941 let offs = 0usize + n * 4usize;
23942 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
23943 }
23944 }
23945 impl Default for Exticr {
23946 fn default() -> Exticr {
23947 Exticr(0)
23948 }
23949 }
23950 #[doc = "Compensation cell control register"]
23951 #[repr(transparent)]
23952 #[derive(Copy, Clone, Eq, PartialEq)]
23953 pub struct Cmpcr(pub u32);
23954 impl Cmpcr {
23955 #[doc = "Compensation cell power-down"]
23956 pub const fn cmp_pd(&self) -> bool {
23957 let val = (self.0 >> 0usize) & 0x01;
23958 val != 0
23959 }
23960 #[doc = "Compensation cell power-down"]
23961 pub fn set_cmp_pd(&mut self, val: bool) {
23962 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
23963 }
23964 #[doc = "READY"]
23965 pub const fn ready(&self) -> bool {
23966 let val = (self.0 >> 8usize) & 0x01;
23967 val != 0
23968 }
23969 #[doc = "READY"]
23970 pub fn set_ready(&mut self, val: bool) {
23971 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
23972 }
23973 }
23974 impl Default for Cmpcr {
23975 fn default() -> Cmpcr {
23976 Cmpcr(0)
23977 }
23978 }
23979 #[doc = "memory remap register"]
23980 #[repr(transparent)]
23981 #[derive(Copy, Clone, Eq, PartialEq)]
23982 pub struct Memrm(pub u32);
23983 impl Memrm {
23984 #[doc = "Memory mapping selection"]
23985 pub const fn mem_mode(&self) -> u8 {
23986 let val = (self.0 >> 0usize) & 0x07;
23987 val as u8
23988 }
23989 #[doc = "Memory mapping selection"]
23990 pub fn set_mem_mode(&mut self, val: u8) {
23991 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
23992 }
23993 #[doc = "Flash bank mode selection"]
23994 pub const fn fb_mode(&self) -> bool {
23995 let val = (self.0 >> 8usize) & 0x01;
23996 val != 0
23997 }
23998 #[doc = "Flash bank mode selection"]
23999 pub fn set_fb_mode(&mut self, val: bool) {
24000 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
24001 }
24002 #[doc = "FMC memory mapping swap"]
24003 pub const fn swp_fmc(&self) -> u8 {
24004 let val = (self.0 >> 10usize) & 0x03;
24005 val as u8
24006 }
24007 #[doc = "FMC memory mapping swap"]
24008 pub fn set_swp_fmc(&mut self, val: u8) {
24009 self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
24010 }
24011 }
24012 impl Default for Memrm {
24013 fn default() -> Memrm {
24014 Memrm(0)
24015 }
24016 }
24017 #[doc = "peripheral mode configuration register"]
24018 #[repr(transparent)]
24019 #[derive(Copy, Clone, Eq, PartialEq)]
24020 pub struct Pmc(pub u32);
24021 impl Pmc {
24022 #[doc = "ADC1DC2"]
24023 pub const fn adc1dc2(&self) -> bool {
24024 let val = (self.0 >> 16usize) & 0x01;
24025 val != 0
24026 }
24027 #[doc = "ADC1DC2"]
24028 pub fn set_adc1dc2(&mut self, val: bool) {
24029 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
24030 }
24031 #[doc = "ADC2DC2"]
24032 pub const fn adc2dc2(&self) -> bool {
24033 let val = (self.0 >> 17usize) & 0x01;
24034 val != 0
24035 }
24036 #[doc = "ADC2DC2"]
24037 pub fn set_adc2dc2(&mut self, val: bool) {
24038 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
24039 }
24040 #[doc = "ADC3DC2"]
24041 pub const fn adc3dc2(&self) -> bool {
24042 let val = (self.0 >> 18usize) & 0x01;
24043 val != 0
24044 }
24045 #[doc = "ADC3DC2"]
24046 pub fn set_adc3dc2(&mut self, val: bool) {
24047 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
24048 }
24049 #[doc = "Ethernet PHY interface selection"]
24050 pub const fn mii_rmii_sel(&self) -> bool {
24051 let val = (self.0 >> 23usize) & 0x01;
24052 val != 0
24053 }
24054 #[doc = "Ethernet PHY interface selection"]
24055 pub fn set_mii_rmii_sel(&mut self, val: bool) {
24056 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
24057 }
24058 }
24059 impl Default for Pmc {
24060 fn default() -> Pmc {
24061 Pmc(0)
24062 }
24063 }
24064 }
24065}
24066pub mod timer_v1 {
24067 use crate::generic::*;
24068 #[doc = "General purpose 32-bit timer"]
24069 #[derive(Copy, Clone)]
24070 pub struct TimGp32(pub *mut u8);
24071 unsafe impl Send for TimGp32 {}
24072 unsafe impl Sync for TimGp32 {}
24073 impl TimGp32 {
24074 #[doc = "control register 1"]
24075 pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
24076 unsafe { Reg::from_ptr(self.0.add(0usize)) }
24077 }
24078 #[doc = "control register 2"]
24079 pub fn cr2(self) -> Reg<regs::Cr2Gp, RW> {
24080 unsafe { Reg::from_ptr(self.0.add(4usize)) }
24081 }
24082 #[doc = "slave mode control register"]
24083 pub fn smcr(self) -> Reg<regs::Smcr, RW> {
24084 unsafe { Reg::from_ptr(self.0.add(8usize)) }
24085 }
24086 #[doc = "DMA/Interrupt enable register"]
24087 pub fn dier(self) -> Reg<regs::DierGp, RW> {
24088 unsafe { Reg::from_ptr(self.0.add(12usize)) }
24089 }
24090 #[doc = "status register"]
24091 pub fn sr(self) -> Reg<regs::SrGp, RW> {
24092 unsafe { Reg::from_ptr(self.0.add(16usize)) }
24093 }
24094 #[doc = "event generation register"]
24095 pub fn egr(self) -> Reg<regs::EgrGp, W> {
24096 unsafe { Reg::from_ptr(self.0.add(20usize)) }
24097 }
24098 #[doc = "capture/compare mode register 1 (input mode)"]
24099 pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
24100 assert!(n < 2usize);
24101 unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
24102 }
24103 #[doc = "capture/compare mode register 1 (output mode)"]
24104 pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
24105 assert!(n < 2usize);
24106 unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
24107 }
24108 #[doc = "capture/compare enable register"]
24109 pub fn ccer(self) -> Reg<regs::CcerGp, RW> {
24110 unsafe { Reg::from_ptr(self.0.add(32usize)) }
24111 }
24112 #[doc = "counter"]
24113 pub fn cnt(self) -> Reg<regs::Cnt32, RW> {
24114 unsafe { Reg::from_ptr(self.0.add(36usize)) }
24115 }
24116 #[doc = "prescaler"]
24117 pub fn psc(self) -> Reg<regs::Psc, RW> {
24118 unsafe { Reg::from_ptr(self.0.add(40usize)) }
24119 }
24120 #[doc = "auto-reload register"]
24121 pub fn arr(self) -> Reg<regs::Arr32, RW> {
24122 unsafe { Reg::from_ptr(self.0.add(44usize)) }
24123 }
24124 #[doc = "capture/compare register"]
24125 pub fn ccr(self, n: usize) -> Reg<regs::Ccr32, RW> {
24126 assert!(n < 4usize);
24127 unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
24128 }
24129 #[doc = "DMA control register"]
24130 pub fn dcr(self) -> Reg<regs::Dcr, RW> {
24131 unsafe { Reg::from_ptr(self.0.add(72usize)) }
24132 }
24133 #[doc = "DMA address for full transfer"]
24134 pub fn dmar(self) -> Reg<regs::Dmar, RW> {
24135 unsafe { Reg::from_ptr(self.0.add(76usize)) }
24136 }
24137 }
24138 #[doc = "Advanced-timers"]
24139 #[derive(Copy, Clone)]
24140 pub struct TimAdv(pub *mut u8);
24141 unsafe impl Send for TimAdv {}
24142 unsafe impl Sync for TimAdv {}
24143 impl TimAdv {
24144 #[doc = "control register 1"]
24145 pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
24146 unsafe { Reg::from_ptr(self.0.add(0usize)) }
24147 }
24148 #[doc = "control register 2"]
24149 pub fn cr2(self) -> Reg<regs::Cr2Adv, RW> {
24150 unsafe { Reg::from_ptr(self.0.add(4usize)) }
24151 }
24152 #[doc = "slave mode control register"]
24153 pub fn smcr(self) -> Reg<regs::Smcr, RW> {
24154 unsafe { Reg::from_ptr(self.0.add(8usize)) }
24155 }
24156 #[doc = "DMA/Interrupt enable register"]
24157 pub fn dier(self) -> Reg<regs::DierAdv, RW> {
24158 unsafe { Reg::from_ptr(self.0.add(12usize)) }
24159 }
24160 #[doc = "status register"]
24161 pub fn sr(self) -> Reg<regs::SrAdv, RW> {
24162 unsafe { Reg::from_ptr(self.0.add(16usize)) }
24163 }
24164 #[doc = "event generation register"]
24165 pub fn egr(self) -> Reg<regs::EgrAdv, W> {
24166 unsafe { Reg::from_ptr(self.0.add(20usize)) }
24167 }
24168 #[doc = "capture/compare mode register 1 (input mode)"]
24169 pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
24170 assert!(n < 2usize);
24171 unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
24172 }
24173 #[doc = "capture/compare mode register 1 (output mode)"]
24174 pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
24175 assert!(n < 2usize);
24176 unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
24177 }
24178 #[doc = "capture/compare enable register"]
24179 pub fn ccer(self) -> Reg<regs::CcerAdv, RW> {
24180 unsafe { Reg::from_ptr(self.0.add(32usize)) }
24181 }
24182 #[doc = "counter"]
24183 pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
24184 unsafe { Reg::from_ptr(self.0.add(36usize)) }
24185 }
24186 #[doc = "prescaler"]
24187 pub fn psc(self) -> Reg<regs::Psc, RW> {
24188 unsafe { Reg::from_ptr(self.0.add(40usize)) }
24189 }
24190 #[doc = "auto-reload register"]
24191 pub fn arr(self) -> Reg<regs::Arr16, RW> {
24192 unsafe { Reg::from_ptr(self.0.add(44usize)) }
24193 }
24194 #[doc = "repetition counter register"]
24195 pub fn rcr(self) -> Reg<regs::Rcr, RW> {
24196 unsafe { Reg::from_ptr(self.0.add(48usize)) }
24197 }
24198 #[doc = "capture/compare register"]
24199 pub fn ccr(self, n: usize) -> Reg<regs::Ccr16, RW> {
24200 assert!(n < 4usize);
24201 unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
24202 }
24203 #[doc = "break and dead-time register"]
24204 pub fn bdtr(self) -> Reg<regs::Bdtr, RW> {
24205 unsafe { Reg::from_ptr(self.0.add(68usize)) }
24206 }
24207 #[doc = "DMA control register"]
24208 pub fn dcr(self) -> Reg<regs::Dcr, RW> {
24209 unsafe { Reg::from_ptr(self.0.add(72usize)) }
24210 }
24211 #[doc = "DMA address for full transfer"]
24212 pub fn dmar(self) -> Reg<regs::Dmar, RW> {
24213 unsafe { Reg::from_ptr(self.0.add(76usize)) }
24214 }
24215 }
24216 #[doc = "General purpose 16-bit timer"]
24217 #[derive(Copy, Clone)]
24218 pub struct TimGp16(pub *mut u8);
24219 unsafe impl Send for TimGp16 {}
24220 unsafe impl Sync for TimGp16 {}
24221 impl TimGp16 {
24222 #[doc = "control register 1"]
24223 pub fn cr1(self) -> Reg<regs::Cr1Gp, RW> {
24224 unsafe { Reg::from_ptr(self.0.add(0usize)) }
24225 }
24226 #[doc = "control register 2"]
24227 pub fn cr2(self) -> Reg<regs::Cr2Gp, RW> {
24228 unsafe { Reg::from_ptr(self.0.add(4usize)) }
24229 }
24230 #[doc = "slave mode control register"]
24231 pub fn smcr(self) -> Reg<regs::Smcr, RW> {
24232 unsafe { Reg::from_ptr(self.0.add(8usize)) }
24233 }
24234 #[doc = "DMA/Interrupt enable register"]
24235 pub fn dier(self) -> Reg<regs::DierGp, RW> {
24236 unsafe { Reg::from_ptr(self.0.add(12usize)) }
24237 }
24238 #[doc = "status register"]
24239 pub fn sr(self) -> Reg<regs::SrGp, RW> {
24240 unsafe { Reg::from_ptr(self.0.add(16usize)) }
24241 }
24242 #[doc = "event generation register"]
24243 pub fn egr(self) -> Reg<regs::EgrGp, W> {
24244 unsafe { Reg::from_ptr(self.0.add(20usize)) }
24245 }
24246 #[doc = "capture/compare mode register 1 (input mode)"]
24247 pub fn ccmr_input(self, n: usize) -> Reg<regs::CcmrInput, RW> {
24248 assert!(n < 2usize);
24249 unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
24250 }
24251 #[doc = "capture/compare mode register 1 (output mode)"]
24252 pub fn ccmr_output(self, n: usize) -> Reg<regs::CcmrOutput, RW> {
24253 assert!(n < 2usize);
24254 unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) }
24255 }
24256 #[doc = "capture/compare enable register"]
24257 pub fn ccer(self) -> Reg<regs::CcerGp, RW> {
24258 unsafe { Reg::from_ptr(self.0.add(32usize)) }
24259 }
24260 #[doc = "counter"]
24261 pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
24262 unsafe { Reg::from_ptr(self.0.add(36usize)) }
24263 }
24264 #[doc = "prescaler"]
24265 pub fn psc(self) -> Reg<regs::Psc, RW> {
24266 unsafe { Reg::from_ptr(self.0.add(40usize)) }
24267 }
24268 #[doc = "auto-reload register"]
24269 pub fn arr(self) -> Reg<regs::Arr16, RW> {
24270 unsafe { Reg::from_ptr(self.0.add(44usize)) }
24271 }
24272 #[doc = "capture/compare register"]
24273 pub fn ccr(self, n: usize) -> Reg<regs::Ccr16, RW> {
24274 assert!(n < 4usize);
24275 unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) }
24276 }
24277 #[doc = "DMA control register"]
24278 pub fn dcr(self) -> Reg<regs::Dcr, RW> {
24279 unsafe { Reg::from_ptr(self.0.add(72usize)) }
24280 }
24281 #[doc = "DMA address for full transfer"]
24282 pub fn dmar(self) -> Reg<regs::Dmar, RW> {
24283 unsafe { Reg::from_ptr(self.0.add(76usize)) }
24284 }
24285 }
24286 #[doc = "Basic timer"]
24287 #[derive(Copy, Clone)]
24288 pub struct TimBasic(pub *mut u8);
24289 unsafe impl Send for TimBasic {}
24290 unsafe impl Sync for TimBasic {}
24291 impl TimBasic {
24292 #[doc = "control register 1"]
24293 pub fn cr1(self) -> Reg<regs::Cr1Basic, RW> {
24294 unsafe { Reg::from_ptr(self.0.add(0usize)) }
24295 }
24296 #[doc = "control register 2"]
24297 pub fn cr2(self) -> Reg<regs::Cr2Basic, RW> {
24298 unsafe { Reg::from_ptr(self.0.add(4usize)) }
24299 }
24300 #[doc = "DMA/Interrupt enable register"]
24301 pub fn dier(self) -> Reg<regs::DierBasic, RW> {
24302 unsafe { Reg::from_ptr(self.0.add(12usize)) }
24303 }
24304 #[doc = "status register"]
24305 pub fn sr(self) -> Reg<regs::SrBasic, RW> {
24306 unsafe { Reg::from_ptr(self.0.add(16usize)) }
24307 }
24308 #[doc = "event generation register"]
24309 pub fn egr(self) -> Reg<regs::EgrBasic, W> {
24310 unsafe { Reg::from_ptr(self.0.add(20usize)) }
24311 }
24312 #[doc = "counter"]
24313 pub fn cnt(self) -> Reg<regs::Cnt16, RW> {
24314 unsafe { Reg::from_ptr(self.0.add(36usize)) }
24315 }
24316 #[doc = "prescaler"]
24317 pub fn psc(self) -> Reg<regs::Psc, RW> {
24318 unsafe { Reg::from_ptr(self.0.add(40usize)) }
24319 }
24320 #[doc = "auto-reload register"]
24321 pub fn arr(self) -> Reg<regs::Arr16, RW> {
24322 unsafe { Reg::from_ptr(self.0.add(44usize)) }
24323 }
24324 }
24325 pub mod regs {
24326 use crate::generic::*;
24327 #[doc = "counter"]
24328 #[repr(transparent)]
24329 #[derive(Copy, Clone, Eq, PartialEq)]
24330 pub struct Cnt32(pub u32);
24331 impl Cnt32 {
24332 #[doc = "counter value"]
24333 pub const fn cnt(&self) -> u32 {
24334 let val = (self.0 >> 0usize) & 0xffff_ffff;
24335 val as u32
24336 }
24337 #[doc = "counter value"]
24338 pub fn set_cnt(&mut self, val: u32) {
24339 self.0 =
24340 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
24341 }
24342 }
24343 impl Default for Cnt32 {
24344 fn default() -> Cnt32 {
24345 Cnt32(0)
24346 }
24347 }
24348 #[doc = "DMA address for full transfer"]
24349 #[repr(transparent)]
24350 #[derive(Copy, Clone, Eq, PartialEq)]
24351 pub struct Dmar(pub u32);
24352 impl Dmar {
24353 #[doc = "DMA register for burst accesses"]
24354 pub const fn dmab(&self) -> u16 {
24355 let val = (self.0 >> 0usize) & 0xffff;
24356 val as u16
24357 }
24358 #[doc = "DMA register for burst accesses"]
24359 pub fn set_dmab(&mut self, val: u16) {
24360 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
24361 }
24362 }
24363 impl Default for Dmar {
24364 fn default() -> Dmar {
24365 Dmar(0)
24366 }
24367 }
24368 #[doc = "capture/compare mode register 2 (output mode)"]
24369 #[repr(transparent)]
24370 #[derive(Copy, Clone, Eq, PartialEq)]
24371 pub struct CcmrOutput(pub u32);
24372 impl CcmrOutput {
24373 #[doc = "Capture/Compare 3 selection"]
24374 pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs {
24375 assert!(n < 2usize);
24376 let offs = 0usize + n * 8usize;
24377 let val = (self.0 >> offs) & 0x03;
24378 super::vals::CcmrOutputCcs(val as u8)
24379 }
24380 #[doc = "Capture/Compare 3 selection"]
24381 pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) {
24382 assert!(n < 2usize);
24383 let offs = 0usize + n * 8usize;
24384 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
24385 }
24386 #[doc = "Output compare 3 fast enable"]
24387 pub fn ocfe(&self, n: usize) -> bool {
24388 assert!(n < 2usize);
24389 let offs = 2usize + n * 8usize;
24390 let val = (self.0 >> offs) & 0x01;
24391 val != 0
24392 }
24393 #[doc = "Output compare 3 fast enable"]
24394 pub fn set_ocfe(&mut self, n: usize, val: bool) {
24395 assert!(n < 2usize);
24396 let offs = 2usize + n * 8usize;
24397 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
24398 }
24399 #[doc = "Output compare 3 preload enable"]
24400 pub fn ocpe(&self, n: usize) -> super::vals::Ocpe {
24401 assert!(n < 2usize);
24402 let offs = 3usize + n * 8usize;
24403 let val = (self.0 >> offs) & 0x01;
24404 super::vals::Ocpe(val as u8)
24405 }
24406 #[doc = "Output compare 3 preload enable"]
24407 pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) {
24408 assert!(n < 2usize);
24409 let offs = 3usize + n * 8usize;
24410 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
24411 }
24412 #[doc = "Output compare 3 mode"]
24413 pub fn ocm(&self, n: usize) -> super::vals::Ocm {
24414 assert!(n < 2usize);
24415 let offs = 4usize + n * 8usize;
24416 let val = (self.0 >> offs) & 0x07;
24417 super::vals::Ocm(val as u8)
24418 }
24419 #[doc = "Output compare 3 mode"]
24420 pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) {
24421 assert!(n < 2usize);
24422 let offs = 4usize + n * 8usize;
24423 self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs);
24424 }
24425 #[doc = "Output compare 3 clear enable"]
24426 pub fn occe(&self, n: usize) -> bool {
24427 assert!(n < 2usize);
24428 let offs = 7usize + n * 8usize;
24429 let val = (self.0 >> offs) & 0x01;
24430 val != 0
24431 }
24432 #[doc = "Output compare 3 clear enable"]
24433 pub fn set_occe(&mut self, n: usize, val: bool) {
24434 assert!(n < 2usize);
24435 let offs = 7usize + n * 8usize;
24436 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
24437 }
24438 }
24439 impl Default for CcmrOutput {
24440 fn default() -> CcmrOutput {
24441 CcmrOutput(0)
24442 }
24443 }
24444 #[doc = "DMA/Interrupt enable register"]
24445 #[repr(transparent)]
24446 #[derive(Copy, Clone, Eq, PartialEq)]
24447 pub struct DierAdv(pub u32);
24448 impl DierAdv {
24449 #[doc = "Update interrupt enable"]
24450 pub const fn uie(&self) -> bool {
24451 let val = (self.0 >> 0usize) & 0x01;
24452 val != 0
24453 }
24454 #[doc = "Update interrupt enable"]
24455 pub fn set_uie(&mut self, val: bool) {
24456 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
24457 }
24458 #[doc = "Capture/Compare 1 interrupt enable"]
24459 pub fn ccie(&self, n: usize) -> bool {
24460 assert!(n < 4usize);
24461 let offs = 1usize + n * 1usize;
24462 let val = (self.0 >> offs) & 0x01;
24463 val != 0
24464 }
24465 #[doc = "Capture/Compare 1 interrupt enable"]
24466 pub fn set_ccie(&mut self, n: usize, val: bool) {
24467 assert!(n < 4usize);
24468 let offs = 1usize + n * 1usize;
24469 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
24470 }
24471 #[doc = "COM interrupt enable"]
24472 pub const fn comie(&self) -> bool {
24473 let val = (self.0 >> 5usize) & 0x01;
24474 val != 0
24475 }
24476 #[doc = "COM interrupt enable"]
24477 pub fn set_comie(&mut self, val: bool) {
24478 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
24479 }
24480 #[doc = "Trigger interrupt enable"]
24481 pub const fn tie(&self) -> bool {
24482 let val = (self.0 >> 6usize) & 0x01;
24483 val != 0
24484 }
24485 #[doc = "Trigger interrupt enable"]
24486 pub fn set_tie(&mut self, val: bool) {
24487 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
24488 }
24489 #[doc = "Break interrupt enable"]
24490 pub const fn bie(&self) -> bool {
24491 let val = (self.0 >> 7usize) & 0x01;
24492 val != 0
24493 }
24494 #[doc = "Break interrupt enable"]
24495 pub fn set_bie(&mut self, val: bool) {
24496 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
24497 }
24498 #[doc = "Update DMA request enable"]
24499 pub const fn ude(&self) -> bool {
24500 let val = (self.0 >> 8usize) & 0x01;
24501 val != 0
24502 }
24503 #[doc = "Update DMA request enable"]
24504 pub fn set_ude(&mut self, val: bool) {
24505 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
24506 }
24507 #[doc = "Capture/Compare 1 DMA request enable"]
24508 pub fn ccde(&self, n: usize) -> bool {
24509 assert!(n < 4usize);
24510 let offs = 9usize + n * 1usize;
24511 let val = (self.0 >> offs) & 0x01;
24512 val != 0
24513 }
24514 #[doc = "Capture/Compare 1 DMA request enable"]
24515 pub fn set_ccde(&mut self, n: usize, val: bool) {
24516 assert!(n < 4usize);
24517 let offs = 9usize + n * 1usize;
24518 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
24519 }
24520 #[doc = "COM DMA request enable"]
24521 pub const fn comde(&self) -> bool {
24522 let val = (self.0 >> 13usize) & 0x01;
24523 val != 0
24524 }
24525 #[doc = "COM DMA request enable"]
24526 pub fn set_comde(&mut self, val: bool) {
24527 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
24528 }
24529 #[doc = "Trigger DMA request enable"]
24530 pub const fn tde(&self) -> bool {
24531 let val = (self.0 >> 14usize) & 0x01;
24532 val != 0
24533 }
24534 #[doc = "Trigger DMA request enable"]
24535 pub fn set_tde(&mut self, val: bool) {
24536 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
24537 }
24538 }
24539 impl Default for DierAdv {
24540 fn default() -> DierAdv {
24541 DierAdv(0)
24542 }
24543 }
24544 #[doc = "capture/compare enable register"]
24545 #[repr(transparent)]
24546 #[derive(Copy, Clone, Eq, PartialEq)]
24547 pub struct CcerAdv(pub u32);
24548 impl CcerAdv {
24549 #[doc = "Capture/Compare 1 output enable"]
24550 pub fn cce(&self, n: usize) -> bool {
24551 assert!(n < 4usize);
24552 let offs = 0usize + n * 4usize;
24553 let val = (self.0 >> offs) & 0x01;
24554 val != 0
24555 }
24556 #[doc = "Capture/Compare 1 output enable"]
24557 pub fn set_cce(&mut self, n: usize, val: bool) {
24558 assert!(n < 4usize);
24559 let offs = 0usize + n * 4usize;
24560 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
24561 }
24562 #[doc = "Capture/Compare 1 output Polarity"]
24563 pub fn ccp(&self, n: usize) -> bool {
24564 assert!(n < 4usize);
24565 let offs = 1usize + n * 4usize;
24566 let val = (self.0 >> offs) & 0x01;
24567 val != 0
24568 }
24569 #[doc = "Capture/Compare 1 output Polarity"]
24570 pub fn set_ccp(&mut self, n: usize, val: bool) {
24571 assert!(n < 4usize);
24572 let offs = 1usize + n * 4usize;
24573 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
24574 }
24575 #[doc = "Capture/Compare 1 complementary output enable"]
24576 pub fn ccne(&self, n: usize) -> bool {
24577 assert!(n < 4usize);
24578 let offs = 2usize + n * 4usize;
24579 let val = (self.0 >> offs) & 0x01;
24580 val != 0
24581 }
24582 #[doc = "Capture/Compare 1 complementary output enable"]
24583 pub fn set_ccne(&mut self, n: usize, val: bool) {
24584 assert!(n < 4usize);
24585 let offs = 2usize + n * 4usize;
24586 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
24587 }
24588 #[doc = "Capture/Compare 1 output Polarity"]
24589 pub fn ccnp(&self, n: usize) -> bool {
24590 assert!(n < 4usize);
24591 let offs = 3usize + n * 4usize;
24592 let val = (self.0 >> offs) & 0x01;
24593 val != 0
24594 }
24595 #[doc = "Capture/Compare 1 output Polarity"]
24596 pub fn set_ccnp(&mut self, n: usize, val: bool) {
24597 assert!(n < 4usize);
24598 let offs = 3usize + n * 4usize;
24599 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
24600 }
24601 }
24602 impl Default for CcerAdv {
24603 fn default() -> CcerAdv {
24604 CcerAdv(0)
24605 }
24606 }
24607 #[doc = "capture/compare register 1"]
24608 #[repr(transparent)]
24609 #[derive(Copy, Clone, Eq, PartialEq)]
24610 pub struct Ccr32(pub u32);
24611 impl Ccr32 {
24612 #[doc = "Capture/Compare 1 value"]
24613 pub const fn ccr(&self) -> u32 {
24614 let val = (self.0 >> 0usize) & 0xffff_ffff;
24615 val as u32
24616 }
24617 #[doc = "Capture/Compare 1 value"]
24618 pub fn set_ccr(&mut self, val: u32) {
24619 self.0 =
24620 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
24621 }
24622 }
24623 impl Default for Ccr32 {
24624 fn default() -> Ccr32 {
24625 Ccr32(0)
24626 }
24627 }
24628 #[doc = "auto-reload register"]
24629 #[repr(transparent)]
24630 #[derive(Copy, Clone, Eq, PartialEq)]
24631 pub struct Arr32(pub u32);
24632 impl Arr32 {
24633 #[doc = "Auto-reload value"]
24634 pub const fn arr(&self) -> u32 {
24635 let val = (self.0 >> 0usize) & 0xffff_ffff;
24636 val as u32
24637 }
24638 #[doc = "Auto-reload value"]
24639 pub fn set_arr(&mut self, val: u32) {
24640 self.0 =
24641 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
24642 }
24643 }
24644 impl Default for Arr32 {
24645 fn default() -> Arr32 {
24646 Arr32(0)
24647 }
24648 }
24649 #[doc = "slave mode control register"]
24650 #[repr(transparent)]
24651 #[derive(Copy, Clone, Eq, PartialEq)]
24652 pub struct Smcr(pub u32);
24653 impl Smcr {
24654 #[doc = "Slave mode selection"]
24655 pub const fn sms(&self) -> super::vals::Sms {
24656 let val = (self.0 >> 0usize) & 0x07;
24657 super::vals::Sms(val as u8)
24658 }
24659 #[doc = "Slave mode selection"]
24660 pub fn set_sms(&mut self, val: super::vals::Sms) {
24661 self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize);
24662 }
24663 #[doc = "Trigger selection"]
24664 pub const fn ts(&self) -> super::vals::Ts {
24665 let val = (self.0 >> 4usize) & 0x07;
24666 super::vals::Ts(val as u8)
24667 }
24668 #[doc = "Trigger selection"]
24669 pub fn set_ts(&mut self, val: super::vals::Ts) {
24670 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
24671 }
24672 #[doc = "Master/Slave mode"]
24673 pub const fn msm(&self) -> super::vals::Msm {
24674 let val = (self.0 >> 7usize) & 0x01;
24675 super::vals::Msm(val as u8)
24676 }
24677 #[doc = "Master/Slave mode"]
24678 pub fn set_msm(&mut self, val: super::vals::Msm) {
24679 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
24680 }
24681 #[doc = "External trigger filter"]
24682 pub const fn etf(&self) -> super::vals::Etf {
24683 let val = (self.0 >> 8usize) & 0x0f;
24684 super::vals::Etf(val as u8)
24685 }
24686 #[doc = "External trigger filter"]
24687 pub fn set_etf(&mut self, val: super::vals::Etf) {
24688 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize);
24689 }
24690 #[doc = "External trigger prescaler"]
24691 pub const fn etps(&self) -> super::vals::Etps {
24692 let val = (self.0 >> 12usize) & 0x03;
24693 super::vals::Etps(val as u8)
24694 }
24695 #[doc = "External trigger prescaler"]
24696 pub fn set_etps(&mut self, val: super::vals::Etps) {
24697 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
24698 }
24699 #[doc = "External clock enable"]
24700 pub const fn ece(&self) -> super::vals::Ece {
24701 let val = (self.0 >> 14usize) & 0x01;
24702 super::vals::Ece(val as u8)
24703 }
24704 #[doc = "External clock enable"]
24705 pub fn set_ece(&mut self, val: super::vals::Ece) {
24706 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
24707 }
24708 #[doc = "External trigger polarity"]
24709 pub const fn etp(&self) -> super::vals::Etp {
24710 let val = (self.0 >> 15usize) & 0x01;
24711 super::vals::Etp(val as u8)
24712 }
24713 #[doc = "External trigger polarity"]
24714 pub fn set_etp(&mut self, val: super::vals::Etp) {
24715 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
24716 }
24717 }
24718 impl Default for Smcr {
24719 fn default() -> Smcr {
24720 Smcr(0)
24721 }
24722 }
24723 #[doc = "capture/compare mode register 1 (input mode)"]
24724 #[repr(transparent)]
24725 #[derive(Copy, Clone, Eq, PartialEq)]
24726 pub struct CcmrInput(pub u32);
24727 impl CcmrInput {
24728 #[doc = "Capture/Compare 1 selection"]
24729 pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs {
24730 assert!(n < 2usize);
24731 let offs = 0usize + n * 8usize;
24732 let val = (self.0 >> offs) & 0x03;
24733 super::vals::CcmrInputCcs(val as u8)
24734 }
24735 #[doc = "Capture/Compare 1 selection"]
24736 pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) {
24737 assert!(n < 2usize);
24738 let offs = 0usize + n * 8usize;
24739 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
24740 }
24741 #[doc = "Input capture 1 prescaler"]
24742 pub fn icpsc(&self, n: usize) -> u8 {
24743 assert!(n < 2usize);
24744 let offs = 2usize + n * 8usize;
24745 let val = (self.0 >> offs) & 0x03;
24746 val as u8
24747 }
24748 #[doc = "Input capture 1 prescaler"]
24749 pub fn set_icpsc(&mut self, n: usize, val: u8) {
24750 assert!(n < 2usize);
24751 let offs = 2usize + n * 8usize;
24752 self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs);
24753 }
24754 #[doc = "Input capture 1 filter"]
24755 pub fn icf(&self, n: usize) -> super::vals::Icf {
24756 assert!(n < 2usize);
24757 let offs = 4usize + n * 8usize;
24758 let val = (self.0 >> offs) & 0x0f;
24759 super::vals::Icf(val as u8)
24760 }
24761 #[doc = "Input capture 1 filter"]
24762 pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) {
24763 assert!(n < 2usize);
24764 let offs = 4usize + n * 8usize;
24765 self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
24766 }
24767 }
24768 impl Default for CcmrInput {
24769 fn default() -> CcmrInput {
24770 CcmrInput(0)
24771 }
24772 }
24773 #[doc = "control register 2"]
24774 #[repr(transparent)]
24775 #[derive(Copy, Clone, Eq, PartialEq)]
24776 pub struct Cr2Gp(pub u32);
24777 impl Cr2Gp {
24778 #[doc = "Capture/compare DMA selection"]
24779 pub const fn ccds(&self) -> super::vals::Ccds {
24780 let val = (self.0 >> 3usize) & 0x01;
24781 super::vals::Ccds(val as u8)
24782 }
24783 #[doc = "Capture/compare DMA selection"]
24784 pub fn set_ccds(&mut self, val: super::vals::Ccds) {
24785 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
24786 }
24787 #[doc = "Master mode selection"]
24788 pub const fn mms(&self) -> super::vals::Mms {
24789 let val = (self.0 >> 4usize) & 0x07;
24790 super::vals::Mms(val as u8)
24791 }
24792 #[doc = "Master mode selection"]
24793 pub fn set_mms(&mut self, val: super::vals::Mms) {
24794 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
24795 }
24796 #[doc = "TI1 selection"]
24797 pub const fn ti1s(&self) -> super::vals::Tis {
24798 let val = (self.0 >> 7usize) & 0x01;
24799 super::vals::Tis(val as u8)
24800 }
24801 #[doc = "TI1 selection"]
24802 pub fn set_ti1s(&mut self, val: super::vals::Tis) {
24803 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
24804 }
24805 }
24806 impl Default for Cr2Gp {
24807 fn default() -> Cr2Gp {
24808 Cr2Gp(0)
24809 }
24810 }
24811 #[doc = "capture/compare register 1"]
24812 #[repr(transparent)]
24813 #[derive(Copy, Clone, Eq, PartialEq)]
24814 pub struct Ccr16(pub u32);
24815 impl Ccr16 {
24816 #[doc = "Capture/Compare 1 value"]
24817 pub const fn ccr(&self) -> u16 {
24818 let val = (self.0 >> 0usize) & 0xffff;
24819 val as u16
24820 }
24821 #[doc = "Capture/Compare 1 value"]
24822 pub fn set_ccr(&mut self, val: u16) {
24823 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
24824 }
24825 }
24826 impl Default for Ccr16 {
24827 fn default() -> Ccr16 {
24828 Ccr16(0)
24829 }
24830 }
24831 #[doc = "auto-reload register"]
24832 #[repr(transparent)]
24833 #[derive(Copy, Clone, Eq, PartialEq)]
24834 pub struct Arr16(pub u32);
24835 impl Arr16 {
24836 #[doc = "Auto-reload value"]
24837 pub const fn arr(&self) -> u16 {
24838 let val = (self.0 >> 0usize) & 0xffff;
24839 val as u16
24840 }
24841 #[doc = "Auto-reload value"]
24842 pub fn set_arr(&mut self, val: u16) {
24843 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
24844 }
24845 }
24846 impl Default for Arr16 {
24847 fn default() -> Arr16 {
24848 Arr16(0)
24849 }
24850 }
24851 #[doc = "break and dead-time register"]
24852 #[repr(transparent)]
24853 #[derive(Copy, Clone, Eq, PartialEq)]
24854 pub struct Bdtr(pub u32);
24855 impl Bdtr {
24856 #[doc = "Dead-time generator setup"]
24857 pub const fn dtg(&self) -> u8 {
24858 let val = (self.0 >> 0usize) & 0xff;
24859 val as u8
24860 }
24861 #[doc = "Dead-time generator setup"]
24862 pub fn set_dtg(&mut self, val: u8) {
24863 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
24864 }
24865 #[doc = "Lock configuration"]
24866 pub const fn lock(&self) -> u8 {
24867 let val = (self.0 >> 8usize) & 0x03;
24868 val as u8
24869 }
24870 #[doc = "Lock configuration"]
24871 pub fn set_lock(&mut self, val: u8) {
24872 self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
24873 }
24874 #[doc = "Off-state selection for Idle mode"]
24875 pub const fn ossi(&self) -> super::vals::Ossi {
24876 let val = (self.0 >> 10usize) & 0x01;
24877 super::vals::Ossi(val as u8)
24878 }
24879 #[doc = "Off-state selection for Idle mode"]
24880 pub fn set_ossi(&mut self, val: super::vals::Ossi) {
24881 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
24882 }
24883 #[doc = "Off-state selection for Run mode"]
24884 pub const fn ossr(&self) -> super::vals::Ossr {
24885 let val = (self.0 >> 11usize) & 0x01;
24886 super::vals::Ossr(val as u8)
24887 }
24888 #[doc = "Off-state selection for Run mode"]
24889 pub fn set_ossr(&mut self, val: super::vals::Ossr) {
24890 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
24891 }
24892 #[doc = "Break enable"]
24893 pub const fn bke(&self) -> bool {
24894 let val = (self.0 >> 12usize) & 0x01;
24895 val != 0
24896 }
24897 #[doc = "Break enable"]
24898 pub fn set_bke(&mut self, val: bool) {
24899 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
24900 }
24901 #[doc = "Break polarity"]
24902 pub const fn bkp(&self) -> bool {
24903 let val = (self.0 >> 13usize) & 0x01;
24904 val != 0
24905 }
24906 #[doc = "Break polarity"]
24907 pub fn set_bkp(&mut self, val: bool) {
24908 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
24909 }
24910 #[doc = "Automatic output enable"]
24911 pub const fn aoe(&self) -> bool {
24912 let val = (self.0 >> 14usize) & 0x01;
24913 val != 0
24914 }
24915 #[doc = "Automatic output enable"]
24916 pub fn set_aoe(&mut self, val: bool) {
24917 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
24918 }
24919 #[doc = "Main output enable"]
24920 pub const fn moe(&self) -> bool {
24921 let val = (self.0 >> 15usize) & 0x01;
24922 val != 0
24923 }
24924 #[doc = "Main output enable"]
24925 pub fn set_moe(&mut self, val: bool) {
24926 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
24927 }
24928 }
24929 impl Default for Bdtr {
24930 fn default() -> Bdtr {
24931 Bdtr(0)
24932 }
24933 }
24934 #[doc = "control register 2"]
24935 #[repr(transparent)]
24936 #[derive(Copy, Clone, Eq, PartialEq)]
24937 pub struct Cr2Basic(pub u32);
24938 impl Cr2Basic {
24939 #[doc = "Master mode selection"]
24940 pub const fn mms(&self) -> super::vals::Mms {
24941 let val = (self.0 >> 4usize) & 0x07;
24942 super::vals::Mms(val as u8)
24943 }
24944 #[doc = "Master mode selection"]
24945 pub fn set_mms(&mut self, val: super::vals::Mms) {
24946 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
24947 }
24948 }
24949 impl Default for Cr2Basic {
24950 fn default() -> Cr2Basic {
24951 Cr2Basic(0)
24952 }
24953 }
24954 #[doc = "event generation register"]
24955 #[repr(transparent)]
24956 #[derive(Copy, Clone, Eq, PartialEq)]
24957 pub struct EgrGp(pub u32);
24958 impl EgrGp {
24959 #[doc = "Update generation"]
24960 pub const fn ug(&self) -> bool {
24961 let val = (self.0 >> 0usize) & 0x01;
24962 val != 0
24963 }
24964 #[doc = "Update generation"]
24965 pub fn set_ug(&mut self, val: bool) {
24966 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
24967 }
24968 #[doc = "Capture/compare 1 generation"]
24969 pub fn ccg(&self, n: usize) -> bool {
24970 assert!(n < 4usize);
24971 let offs = 1usize + n * 1usize;
24972 let val = (self.0 >> offs) & 0x01;
24973 val != 0
24974 }
24975 #[doc = "Capture/compare 1 generation"]
24976 pub fn set_ccg(&mut self, n: usize, val: bool) {
24977 assert!(n < 4usize);
24978 let offs = 1usize + n * 1usize;
24979 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
24980 }
24981 #[doc = "Capture/Compare control update generation"]
24982 pub const fn comg(&self) -> bool {
24983 let val = (self.0 >> 5usize) & 0x01;
24984 val != 0
24985 }
24986 #[doc = "Capture/Compare control update generation"]
24987 pub fn set_comg(&mut self, val: bool) {
24988 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
24989 }
24990 #[doc = "Trigger generation"]
24991 pub const fn tg(&self) -> bool {
24992 let val = (self.0 >> 6usize) & 0x01;
24993 val != 0
24994 }
24995 #[doc = "Trigger generation"]
24996 pub fn set_tg(&mut self, val: bool) {
24997 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
24998 }
24999 #[doc = "Break generation"]
25000 pub const fn bg(&self) -> bool {
25001 let val = (self.0 >> 7usize) & 0x01;
25002 val != 0
25003 }
25004 #[doc = "Break generation"]
25005 pub fn set_bg(&mut self, val: bool) {
25006 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
25007 }
25008 }
25009 impl Default for EgrGp {
25010 fn default() -> EgrGp {
25011 EgrGp(0)
25012 }
25013 }
25014 #[doc = "DMA/Interrupt enable register"]
25015 #[repr(transparent)]
25016 #[derive(Copy, Clone, Eq, PartialEq)]
25017 pub struct DierBasic(pub u32);
25018 impl DierBasic {
25019 #[doc = "Update interrupt enable"]
25020 pub const fn uie(&self) -> bool {
25021 let val = (self.0 >> 0usize) & 0x01;
25022 val != 0
25023 }
25024 #[doc = "Update interrupt enable"]
25025 pub fn set_uie(&mut self, val: bool) {
25026 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
25027 }
25028 #[doc = "Update DMA request enable"]
25029 pub const fn ude(&self) -> bool {
25030 let val = (self.0 >> 8usize) & 0x01;
25031 val != 0
25032 }
25033 #[doc = "Update DMA request enable"]
25034 pub fn set_ude(&mut self, val: bool) {
25035 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
25036 }
25037 }
25038 impl Default for DierBasic {
25039 fn default() -> DierBasic {
25040 DierBasic(0)
25041 }
25042 }
25043 #[doc = "capture/compare enable register"]
25044 #[repr(transparent)]
25045 #[derive(Copy, Clone, Eq, PartialEq)]
25046 pub struct CcerGp(pub u32);
25047 impl CcerGp {
25048 #[doc = "Capture/Compare 1 output enable"]
25049 pub fn cce(&self, n: usize) -> bool {
25050 assert!(n < 4usize);
25051 let offs = 0usize + n * 4usize;
25052 let val = (self.0 >> offs) & 0x01;
25053 val != 0
25054 }
25055 #[doc = "Capture/Compare 1 output enable"]
25056 pub fn set_cce(&mut self, n: usize, val: bool) {
25057 assert!(n < 4usize);
25058 let offs = 0usize + n * 4usize;
25059 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25060 }
25061 #[doc = "Capture/Compare 1 output Polarity"]
25062 pub fn ccp(&self, n: usize) -> bool {
25063 assert!(n < 4usize);
25064 let offs = 1usize + n * 4usize;
25065 let val = (self.0 >> offs) & 0x01;
25066 val != 0
25067 }
25068 #[doc = "Capture/Compare 1 output Polarity"]
25069 pub fn set_ccp(&mut self, n: usize, val: bool) {
25070 assert!(n < 4usize);
25071 let offs = 1usize + n * 4usize;
25072 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25073 }
25074 #[doc = "Capture/Compare 1 output Polarity"]
25075 pub fn ccnp(&self, n: usize) -> bool {
25076 assert!(n < 4usize);
25077 let offs = 3usize + n * 4usize;
25078 let val = (self.0 >> offs) & 0x01;
25079 val != 0
25080 }
25081 #[doc = "Capture/Compare 1 output Polarity"]
25082 pub fn set_ccnp(&mut self, n: usize, val: bool) {
25083 assert!(n < 4usize);
25084 let offs = 3usize + n * 4usize;
25085 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25086 }
25087 }
25088 impl Default for CcerGp {
25089 fn default() -> CcerGp {
25090 CcerGp(0)
25091 }
25092 }
25093 #[doc = "repetition counter register"]
25094 #[repr(transparent)]
25095 #[derive(Copy, Clone, Eq, PartialEq)]
25096 pub struct Rcr(pub u32);
25097 impl Rcr {
25098 #[doc = "Repetition counter value"]
25099 pub const fn rep(&self) -> u8 {
25100 let val = (self.0 >> 0usize) & 0xff;
25101 val as u8
25102 }
25103 #[doc = "Repetition counter value"]
25104 pub fn set_rep(&mut self, val: u8) {
25105 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
25106 }
25107 }
25108 impl Default for Rcr {
25109 fn default() -> Rcr {
25110 Rcr(0)
25111 }
25112 }
25113 #[doc = "control register 1"]
25114 #[repr(transparent)]
25115 #[derive(Copy, Clone, Eq, PartialEq)]
25116 pub struct Cr1Gp(pub u32);
25117 impl Cr1Gp {
25118 #[doc = "Counter enable"]
25119 pub const fn cen(&self) -> bool {
25120 let val = (self.0 >> 0usize) & 0x01;
25121 val != 0
25122 }
25123 #[doc = "Counter enable"]
25124 pub fn set_cen(&mut self, val: bool) {
25125 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
25126 }
25127 #[doc = "Update disable"]
25128 pub const fn udis(&self) -> bool {
25129 let val = (self.0 >> 1usize) & 0x01;
25130 val != 0
25131 }
25132 #[doc = "Update disable"]
25133 pub fn set_udis(&mut self, val: bool) {
25134 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
25135 }
25136 #[doc = "Update request source"]
25137 pub const fn urs(&self) -> super::vals::Urs {
25138 let val = (self.0 >> 2usize) & 0x01;
25139 super::vals::Urs(val as u8)
25140 }
25141 #[doc = "Update request source"]
25142 pub fn set_urs(&mut self, val: super::vals::Urs) {
25143 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
25144 }
25145 #[doc = "One-pulse mode"]
25146 pub const fn opm(&self) -> super::vals::Opm {
25147 let val = (self.0 >> 3usize) & 0x01;
25148 super::vals::Opm(val as u8)
25149 }
25150 #[doc = "One-pulse mode"]
25151 pub fn set_opm(&mut self, val: super::vals::Opm) {
25152 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
25153 }
25154 #[doc = "Direction"]
25155 pub const fn dir(&self) -> super::vals::Dir {
25156 let val = (self.0 >> 4usize) & 0x01;
25157 super::vals::Dir(val as u8)
25158 }
25159 #[doc = "Direction"]
25160 pub fn set_dir(&mut self, val: super::vals::Dir) {
25161 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
25162 }
25163 #[doc = "Center-aligned mode selection"]
25164 pub const fn cms(&self) -> super::vals::Cms {
25165 let val = (self.0 >> 5usize) & 0x03;
25166 super::vals::Cms(val as u8)
25167 }
25168 #[doc = "Center-aligned mode selection"]
25169 pub fn set_cms(&mut self, val: super::vals::Cms) {
25170 self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize);
25171 }
25172 #[doc = "Auto-reload preload enable"]
25173 pub const fn arpe(&self) -> super::vals::Arpe {
25174 let val = (self.0 >> 7usize) & 0x01;
25175 super::vals::Arpe(val as u8)
25176 }
25177 #[doc = "Auto-reload preload enable"]
25178 pub fn set_arpe(&mut self, val: super::vals::Arpe) {
25179 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
25180 }
25181 #[doc = "Clock division"]
25182 pub const fn ckd(&self) -> super::vals::Ckd {
25183 let val = (self.0 >> 8usize) & 0x03;
25184 super::vals::Ckd(val as u8)
25185 }
25186 #[doc = "Clock division"]
25187 pub fn set_ckd(&mut self, val: super::vals::Ckd) {
25188 self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize);
25189 }
25190 }
25191 impl Default for Cr1Gp {
25192 fn default() -> Cr1Gp {
25193 Cr1Gp(0)
25194 }
25195 }
25196 #[doc = "status register"]
25197 #[repr(transparent)]
25198 #[derive(Copy, Clone, Eq, PartialEq)]
25199 pub struct SrBasic(pub u32);
25200 impl SrBasic {
25201 #[doc = "Update interrupt flag"]
25202 pub const fn uif(&self) -> bool {
25203 let val = (self.0 >> 0usize) & 0x01;
25204 val != 0
25205 }
25206 #[doc = "Update interrupt flag"]
25207 pub fn set_uif(&mut self, val: bool) {
25208 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
25209 }
25210 }
25211 impl Default for SrBasic {
25212 fn default() -> SrBasic {
25213 SrBasic(0)
25214 }
25215 }
25216 #[doc = "status register"]
25217 #[repr(transparent)]
25218 #[derive(Copy, Clone, Eq, PartialEq)]
25219 pub struct SrAdv(pub u32);
25220 impl SrAdv {
25221 #[doc = "Update interrupt flag"]
25222 pub const fn uif(&self) -> bool {
25223 let val = (self.0 >> 0usize) & 0x01;
25224 val != 0
25225 }
25226 #[doc = "Update interrupt flag"]
25227 pub fn set_uif(&mut self, val: bool) {
25228 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
25229 }
25230 #[doc = "Capture/compare 1 interrupt flag"]
25231 pub fn ccif(&self, n: usize) -> bool {
25232 assert!(n < 4usize);
25233 let offs = 1usize + n * 1usize;
25234 let val = (self.0 >> offs) & 0x01;
25235 val != 0
25236 }
25237 #[doc = "Capture/compare 1 interrupt flag"]
25238 pub fn set_ccif(&mut self, n: usize, val: bool) {
25239 assert!(n < 4usize);
25240 let offs = 1usize + n * 1usize;
25241 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25242 }
25243 #[doc = "COM interrupt flag"]
25244 pub const fn comif(&self) -> bool {
25245 let val = (self.0 >> 5usize) & 0x01;
25246 val != 0
25247 }
25248 #[doc = "COM interrupt flag"]
25249 pub fn set_comif(&mut self, val: bool) {
25250 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
25251 }
25252 #[doc = "Trigger interrupt flag"]
25253 pub const fn tif(&self) -> bool {
25254 let val = (self.0 >> 6usize) & 0x01;
25255 val != 0
25256 }
25257 #[doc = "Trigger interrupt flag"]
25258 pub fn set_tif(&mut self, val: bool) {
25259 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
25260 }
25261 #[doc = "Break interrupt flag"]
25262 pub const fn bif(&self) -> bool {
25263 let val = (self.0 >> 7usize) & 0x01;
25264 val != 0
25265 }
25266 #[doc = "Break interrupt flag"]
25267 pub fn set_bif(&mut self, val: bool) {
25268 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
25269 }
25270 #[doc = "Capture/Compare 1 overcapture flag"]
25271 pub fn ccof(&self, n: usize) -> bool {
25272 assert!(n < 4usize);
25273 let offs = 9usize + n * 1usize;
25274 let val = (self.0 >> offs) & 0x01;
25275 val != 0
25276 }
25277 #[doc = "Capture/Compare 1 overcapture flag"]
25278 pub fn set_ccof(&mut self, n: usize, val: bool) {
25279 assert!(n < 4usize);
25280 let offs = 9usize + n * 1usize;
25281 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25282 }
25283 }
25284 impl Default for SrAdv {
25285 fn default() -> SrAdv {
25286 SrAdv(0)
25287 }
25288 }
25289 #[doc = "DMA control register"]
25290 #[repr(transparent)]
25291 #[derive(Copy, Clone, Eq, PartialEq)]
25292 pub struct Dcr(pub u32);
25293 impl Dcr {
25294 #[doc = "DMA base address"]
25295 pub const fn dba(&self) -> u8 {
25296 let val = (self.0 >> 0usize) & 0x1f;
25297 val as u8
25298 }
25299 #[doc = "DMA base address"]
25300 pub fn set_dba(&mut self, val: u8) {
25301 self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize);
25302 }
25303 #[doc = "DMA burst length"]
25304 pub const fn dbl(&self) -> u8 {
25305 let val = (self.0 >> 8usize) & 0x1f;
25306 val as u8
25307 }
25308 #[doc = "DMA burst length"]
25309 pub fn set_dbl(&mut self, val: u8) {
25310 self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize);
25311 }
25312 }
25313 impl Default for Dcr {
25314 fn default() -> Dcr {
25315 Dcr(0)
25316 }
25317 }
25318 #[doc = "control register 1"]
25319 #[repr(transparent)]
25320 #[derive(Copy, Clone, Eq, PartialEq)]
25321 pub struct Cr1Basic(pub u32);
25322 impl Cr1Basic {
25323 #[doc = "Counter enable"]
25324 pub const fn cen(&self) -> bool {
25325 let val = (self.0 >> 0usize) & 0x01;
25326 val != 0
25327 }
25328 #[doc = "Counter enable"]
25329 pub fn set_cen(&mut self, val: bool) {
25330 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
25331 }
25332 #[doc = "Update disable"]
25333 pub const fn udis(&self) -> bool {
25334 let val = (self.0 >> 1usize) & 0x01;
25335 val != 0
25336 }
25337 #[doc = "Update disable"]
25338 pub fn set_udis(&mut self, val: bool) {
25339 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
25340 }
25341 #[doc = "Update request source"]
25342 pub const fn urs(&self) -> super::vals::Urs {
25343 let val = (self.0 >> 2usize) & 0x01;
25344 super::vals::Urs(val as u8)
25345 }
25346 #[doc = "Update request source"]
25347 pub fn set_urs(&mut self, val: super::vals::Urs) {
25348 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
25349 }
25350 #[doc = "One-pulse mode"]
25351 pub const fn opm(&self) -> super::vals::Opm {
25352 let val = (self.0 >> 3usize) & 0x01;
25353 super::vals::Opm(val as u8)
25354 }
25355 #[doc = "One-pulse mode"]
25356 pub fn set_opm(&mut self, val: super::vals::Opm) {
25357 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
25358 }
25359 #[doc = "Auto-reload preload enable"]
25360 pub const fn arpe(&self) -> super::vals::Arpe {
25361 let val = (self.0 >> 7usize) & 0x01;
25362 super::vals::Arpe(val as u8)
25363 }
25364 #[doc = "Auto-reload preload enable"]
25365 pub fn set_arpe(&mut self, val: super::vals::Arpe) {
25366 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
25367 }
25368 }
25369 impl Default for Cr1Basic {
25370 fn default() -> Cr1Basic {
25371 Cr1Basic(0)
25372 }
25373 }
25374 #[doc = "event generation register"]
25375 #[repr(transparent)]
25376 #[derive(Copy, Clone, Eq, PartialEq)]
25377 pub struct EgrAdv(pub u32);
25378 impl EgrAdv {
25379 #[doc = "Update generation"]
25380 pub const fn ug(&self) -> bool {
25381 let val = (self.0 >> 0usize) & 0x01;
25382 val != 0
25383 }
25384 #[doc = "Update generation"]
25385 pub fn set_ug(&mut self, val: bool) {
25386 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
25387 }
25388 #[doc = "Capture/compare 1 generation"]
25389 pub fn ccg(&self, n: usize) -> bool {
25390 assert!(n < 4usize);
25391 let offs = 1usize + n * 1usize;
25392 let val = (self.0 >> offs) & 0x01;
25393 val != 0
25394 }
25395 #[doc = "Capture/compare 1 generation"]
25396 pub fn set_ccg(&mut self, n: usize, val: bool) {
25397 assert!(n < 4usize);
25398 let offs = 1usize + n * 1usize;
25399 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25400 }
25401 #[doc = "Capture/Compare control update generation"]
25402 pub const fn comg(&self) -> bool {
25403 let val = (self.0 >> 5usize) & 0x01;
25404 val != 0
25405 }
25406 #[doc = "Capture/Compare control update generation"]
25407 pub fn set_comg(&mut self, val: bool) {
25408 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
25409 }
25410 #[doc = "Trigger generation"]
25411 pub const fn tg(&self) -> bool {
25412 let val = (self.0 >> 6usize) & 0x01;
25413 val != 0
25414 }
25415 #[doc = "Trigger generation"]
25416 pub fn set_tg(&mut self, val: bool) {
25417 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
25418 }
25419 #[doc = "Break generation"]
25420 pub const fn bg(&self) -> bool {
25421 let val = (self.0 >> 7usize) & 0x01;
25422 val != 0
25423 }
25424 #[doc = "Break generation"]
25425 pub fn set_bg(&mut self, val: bool) {
25426 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
25427 }
25428 }
25429 impl Default for EgrAdv {
25430 fn default() -> EgrAdv {
25431 EgrAdv(0)
25432 }
25433 }
25434 #[doc = "prescaler"]
25435 #[repr(transparent)]
25436 #[derive(Copy, Clone, Eq, PartialEq)]
25437 pub struct Psc(pub u32);
25438 impl Psc {
25439 #[doc = "Prescaler value"]
25440 pub const fn psc(&self) -> u16 {
25441 let val = (self.0 >> 0usize) & 0xffff;
25442 val as u16
25443 }
25444 #[doc = "Prescaler value"]
25445 pub fn set_psc(&mut self, val: u16) {
25446 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
25447 }
25448 }
25449 impl Default for Psc {
25450 fn default() -> Psc {
25451 Psc(0)
25452 }
25453 }
25454 #[doc = "counter"]
25455 #[repr(transparent)]
25456 #[derive(Copy, Clone, Eq, PartialEq)]
25457 pub struct Cnt16(pub u32);
25458 impl Cnt16 {
25459 #[doc = "counter value"]
25460 pub const fn cnt(&self) -> u16 {
25461 let val = (self.0 >> 0usize) & 0xffff;
25462 val as u16
25463 }
25464 #[doc = "counter value"]
25465 pub fn set_cnt(&mut self, val: u16) {
25466 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
25467 }
25468 }
25469 impl Default for Cnt16 {
25470 fn default() -> Cnt16 {
25471 Cnt16(0)
25472 }
25473 }
25474 #[doc = "status register"]
25475 #[repr(transparent)]
25476 #[derive(Copy, Clone, Eq, PartialEq)]
25477 pub struct SrGp(pub u32);
25478 impl SrGp {
25479 #[doc = "Update interrupt flag"]
25480 pub const fn uif(&self) -> bool {
25481 let val = (self.0 >> 0usize) & 0x01;
25482 val != 0
25483 }
25484 #[doc = "Update interrupt flag"]
25485 pub fn set_uif(&mut self, val: bool) {
25486 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
25487 }
25488 #[doc = "Capture/compare 1 interrupt flag"]
25489 pub fn ccif(&self, n: usize) -> bool {
25490 assert!(n < 4usize);
25491 let offs = 1usize + n * 1usize;
25492 let val = (self.0 >> offs) & 0x01;
25493 val != 0
25494 }
25495 #[doc = "Capture/compare 1 interrupt flag"]
25496 pub fn set_ccif(&mut self, n: usize, val: bool) {
25497 assert!(n < 4usize);
25498 let offs = 1usize + n * 1usize;
25499 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25500 }
25501 #[doc = "COM interrupt flag"]
25502 pub const fn comif(&self) -> bool {
25503 let val = (self.0 >> 5usize) & 0x01;
25504 val != 0
25505 }
25506 #[doc = "COM interrupt flag"]
25507 pub fn set_comif(&mut self, val: bool) {
25508 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
25509 }
25510 #[doc = "Trigger interrupt flag"]
25511 pub const fn tif(&self) -> bool {
25512 let val = (self.0 >> 6usize) & 0x01;
25513 val != 0
25514 }
25515 #[doc = "Trigger interrupt flag"]
25516 pub fn set_tif(&mut self, val: bool) {
25517 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
25518 }
25519 #[doc = "Break interrupt flag"]
25520 pub const fn bif(&self) -> bool {
25521 let val = (self.0 >> 7usize) & 0x01;
25522 val != 0
25523 }
25524 #[doc = "Break interrupt flag"]
25525 pub fn set_bif(&mut self, val: bool) {
25526 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
25527 }
25528 #[doc = "Capture/Compare 1 overcapture flag"]
25529 pub fn ccof(&self, n: usize) -> bool {
25530 assert!(n < 4usize);
25531 let offs = 9usize + n * 1usize;
25532 let val = (self.0 >> offs) & 0x01;
25533 val != 0
25534 }
25535 #[doc = "Capture/Compare 1 overcapture flag"]
25536 pub fn set_ccof(&mut self, n: usize, val: bool) {
25537 assert!(n < 4usize);
25538 let offs = 9usize + n * 1usize;
25539 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25540 }
25541 }
25542 impl Default for SrGp {
25543 fn default() -> SrGp {
25544 SrGp(0)
25545 }
25546 }
25547 #[doc = "control register 2"]
25548 #[repr(transparent)]
25549 #[derive(Copy, Clone, Eq, PartialEq)]
25550 pub struct Cr2Adv(pub u32);
25551 impl Cr2Adv {
25552 #[doc = "Capture/compare preloaded control"]
25553 pub const fn ccpc(&self) -> bool {
25554 let val = (self.0 >> 0usize) & 0x01;
25555 val != 0
25556 }
25557 #[doc = "Capture/compare preloaded control"]
25558 pub fn set_ccpc(&mut self, val: bool) {
25559 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
25560 }
25561 #[doc = "Capture/compare control update selection"]
25562 pub const fn ccus(&self) -> bool {
25563 let val = (self.0 >> 2usize) & 0x01;
25564 val != 0
25565 }
25566 #[doc = "Capture/compare control update selection"]
25567 pub fn set_ccus(&mut self, val: bool) {
25568 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
25569 }
25570 #[doc = "Capture/compare DMA selection"]
25571 pub const fn ccds(&self) -> super::vals::Ccds {
25572 let val = (self.0 >> 3usize) & 0x01;
25573 super::vals::Ccds(val as u8)
25574 }
25575 #[doc = "Capture/compare DMA selection"]
25576 pub fn set_ccds(&mut self, val: super::vals::Ccds) {
25577 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
25578 }
25579 #[doc = "Master mode selection"]
25580 pub const fn mms(&self) -> super::vals::Mms {
25581 let val = (self.0 >> 4usize) & 0x07;
25582 super::vals::Mms(val as u8)
25583 }
25584 #[doc = "Master mode selection"]
25585 pub fn set_mms(&mut self, val: super::vals::Mms) {
25586 self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize);
25587 }
25588 #[doc = "TI1 selection"]
25589 pub const fn ti1s(&self) -> super::vals::Tis {
25590 let val = (self.0 >> 7usize) & 0x01;
25591 super::vals::Tis(val as u8)
25592 }
25593 #[doc = "TI1 selection"]
25594 pub fn set_ti1s(&mut self, val: super::vals::Tis) {
25595 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
25596 }
25597 #[doc = "Output Idle state 1"]
25598 pub fn ois(&self, n: usize) -> bool {
25599 assert!(n < 4usize);
25600 let offs = 8usize + n * 2usize;
25601 let val = (self.0 >> offs) & 0x01;
25602 val != 0
25603 }
25604 #[doc = "Output Idle state 1"]
25605 pub fn set_ois(&mut self, n: usize, val: bool) {
25606 assert!(n < 4usize);
25607 let offs = 8usize + n * 2usize;
25608 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25609 }
25610 #[doc = "Output Idle state 1"]
25611 pub const fn ois1n(&self) -> bool {
25612 let val = (self.0 >> 9usize) & 0x01;
25613 val != 0
25614 }
25615 #[doc = "Output Idle state 1"]
25616 pub fn set_ois1n(&mut self, val: bool) {
25617 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
25618 }
25619 #[doc = "Output Idle state 2"]
25620 pub const fn ois2n(&self) -> bool {
25621 let val = (self.0 >> 11usize) & 0x01;
25622 val != 0
25623 }
25624 #[doc = "Output Idle state 2"]
25625 pub fn set_ois2n(&mut self, val: bool) {
25626 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
25627 }
25628 #[doc = "Output Idle state 3"]
25629 pub const fn ois3n(&self) -> bool {
25630 let val = (self.0 >> 13usize) & 0x01;
25631 val != 0
25632 }
25633 #[doc = "Output Idle state 3"]
25634 pub fn set_ois3n(&mut self, val: bool) {
25635 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
25636 }
25637 }
25638 impl Default for Cr2Adv {
25639 fn default() -> Cr2Adv {
25640 Cr2Adv(0)
25641 }
25642 }
25643 #[doc = "event generation register"]
25644 #[repr(transparent)]
25645 #[derive(Copy, Clone, Eq, PartialEq)]
25646 pub struct EgrBasic(pub u32);
25647 impl EgrBasic {
25648 #[doc = "Update generation"]
25649 pub const fn ug(&self) -> bool {
25650 let val = (self.0 >> 0usize) & 0x01;
25651 val != 0
25652 }
25653 #[doc = "Update generation"]
25654 pub fn set_ug(&mut self, val: bool) {
25655 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
25656 }
25657 }
25658 impl Default for EgrBasic {
25659 fn default() -> EgrBasic {
25660 EgrBasic(0)
25661 }
25662 }
25663 #[doc = "DMA/Interrupt enable register"]
25664 #[repr(transparent)]
25665 #[derive(Copy, Clone, Eq, PartialEq)]
25666 pub struct DierGp(pub u32);
25667 impl DierGp {
25668 #[doc = "Update interrupt enable"]
25669 pub const fn uie(&self) -> bool {
25670 let val = (self.0 >> 0usize) & 0x01;
25671 val != 0
25672 }
25673 #[doc = "Update interrupt enable"]
25674 pub fn set_uie(&mut self, val: bool) {
25675 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
25676 }
25677 #[doc = "Capture/Compare 1 interrupt enable"]
25678 pub fn ccie(&self, n: usize) -> bool {
25679 assert!(n < 4usize);
25680 let offs = 1usize + n * 1usize;
25681 let val = (self.0 >> offs) & 0x01;
25682 val != 0
25683 }
25684 #[doc = "Capture/Compare 1 interrupt enable"]
25685 pub fn set_ccie(&mut self, n: usize, val: bool) {
25686 assert!(n < 4usize);
25687 let offs = 1usize + n * 1usize;
25688 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25689 }
25690 #[doc = "Trigger interrupt enable"]
25691 pub const fn tie(&self) -> bool {
25692 let val = (self.0 >> 6usize) & 0x01;
25693 val != 0
25694 }
25695 #[doc = "Trigger interrupt enable"]
25696 pub fn set_tie(&mut self, val: bool) {
25697 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
25698 }
25699 #[doc = "Update DMA request enable"]
25700 pub const fn ude(&self) -> bool {
25701 let val = (self.0 >> 8usize) & 0x01;
25702 val != 0
25703 }
25704 #[doc = "Update DMA request enable"]
25705 pub fn set_ude(&mut self, val: bool) {
25706 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
25707 }
25708 #[doc = "Capture/Compare 1 DMA request enable"]
25709 pub fn ccde(&self, n: usize) -> bool {
25710 assert!(n < 4usize);
25711 let offs = 9usize + n * 1usize;
25712 let val = (self.0 >> offs) & 0x01;
25713 val != 0
25714 }
25715 #[doc = "Capture/Compare 1 DMA request enable"]
25716 pub fn set_ccde(&mut self, n: usize, val: bool) {
25717 assert!(n < 4usize);
25718 let offs = 9usize + n * 1usize;
25719 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
25720 }
25721 #[doc = "Trigger DMA request enable"]
25722 pub const fn tde(&self) -> bool {
25723 let val = (self.0 >> 14usize) & 0x01;
25724 val != 0
25725 }
25726 #[doc = "Trigger DMA request enable"]
25727 pub fn set_tde(&mut self, val: bool) {
25728 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
25729 }
25730 }
25731 impl Default for DierGp {
25732 fn default() -> DierGp {
25733 DierGp(0)
25734 }
25735 }
25736 }
25737 pub mod vals {
25738 use crate::generic::*;
25739 #[repr(transparent)]
25740 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25741 pub struct Dir(pub u8);
25742 impl Dir {
25743 #[doc = "Counter used as upcounter"]
25744 pub const UP: Self = Self(0);
25745 #[doc = "Counter used as downcounter"]
25746 pub const DOWN: Self = Self(0x01);
25747 }
25748 #[repr(transparent)]
25749 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25750 pub struct Ts(pub u8);
25751 impl Ts {
25752 #[doc = "Internal Trigger 0 (ITR0)"]
25753 pub const ITR0: Self = Self(0);
25754 #[doc = "Internal Trigger 1 (ITR1)"]
25755 pub const ITR1: Self = Self(0x01);
25756 #[doc = "Internal Trigger 2 (ITR2)"]
25757 pub const ITR2: Self = Self(0x02);
25758 #[doc = "TI1 Edge Detector (TI1F_ED)"]
25759 pub const TI1F_ED: Self = Self(0x04);
25760 #[doc = "Filtered Timer Input 1 (TI1FP1)"]
25761 pub const TI1FP1: Self = Self(0x05);
25762 #[doc = "Filtered Timer Input 2 (TI2FP2)"]
25763 pub const TI2FP2: Self = Self(0x06);
25764 #[doc = "External Trigger input (ETRF)"]
25765 pub const ETRF: Self = Self(0x07);
25766 }
25767 #[repr(transparent)]
25768 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25769 pub struct Opm(pub u8);
25770 impl Opm {
25771 #[doc = "Counter is not stopped at update event"]
25772 pub const DISABLED: Self = Self(0);
25773 #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"]
25774 pub const ENABLED: Self = Self(0x01);
25775 }
25776 #[repr(transparent)]
25777 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25778 pub struct CcmrInputCcs(pub u8);
25779 impl CcmrInputCcs {
25780 #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"]
25781 pub const TI4: Self = Self(0x01);
25782 #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"]
25783 pub const TI3: Self = Self(0x02);
25784 #[doc = "CCx channel is configured as input, ICx is mapped on TRC"]
25785 pub const TRC: Self = Self(0x03);
25786 }
25787 #[repr(transparent)]
25788 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25789 pub struct Etf(pub u8);
25790 impl Etf {
25791 #[doc = "No filter, sampling is done at fDTS"]
25792 pub const NOFILTER: Self = Self(0);
25793 #[doc = "fSAMPLING=fCK_INT, N=2"]
25794 pub const FCK_INT_N2: Self = Self(0x01);
25795 #[doc = "fSAMPLING=fCK_INT, N=4"]
25796 pub const FCK_INT_N4: Self = Self(0x02);
25797 #[doc = "fSAMPLING=fCK_INT, N=8"]
25798 pub const FCK_INT_N8: Self = Self(0x03);
25799 #[doc = "fSAMPLING=fDTS/2, N=6"]
25800 pub const FDTS_DIV2_N6: Self = Self(0x04);
25801 #[doc = "fSAMPLING=fDTS/2, N=8"]
25802 pub const FDTS_DIV2_N8: Self = Self(0x05);
25803 #[doc = "fSAMPLING=fDTS/4, N=6"]
25804 pub const FDTS_DIV4_N6: Self = Self(0x06);
25805 #[doc = "fSAMPLING=fDTS/4, N=8"]
25806 pub const FDTS_DIV4_N8: Self = Self(0x07);
25807 #[doc = "fSAMPLING=fDTS/8, N=6"]
25808 pub const FDTS_DIV8_N6: Self = Self(0x08);
25809 #[doc = "fSAMPLING=fDTS/8, N=8"]
25810 pub const FDTS_DIV8_N8: Self = Self(0x09);
25811 #[doc = "fSAMPLING=fDTS/16, N=5"]
25812 pub const FDTS_DIV16_N5: Self = Self(0x0a);
25813 #[doc = "fSAMPLING=fDTS/16, N=6"]
25814 pub const FDTS_DIV16_N6: Self = Self(0x0b);
25815 #[doc = "fSAMPLING=fDTS/16, N=8"]
25816 pub const FDTS_DIV16_N8: Self = Self(0x0c);
25817 #[doc = "fSAMPLING=fDTS/32, N=5"]
25818 pub const FDTS_DIV32_N5: Self = Self(0x0d);
25819 #[doc = "fSAMPLING=fDTS/32, N=6"]
25820 pub const FDTS_DIV32_N6: Self = Self(0x0e);
25821 #[doc = "fSAMPLING=fDTS/32, N=8"]
25822 pub const FDTS_DIV32_N8: Self = Self(0x0f);
25823 }
25824 #[repr(transparent)]
25825 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25826 pub struct Ccds(pub u8);
25827 impl Ccds {
25828 #[doc = "CCx DMA request sent when CCx event occurs"]
25829 pub const ONCOMPARE: Self = Self(0);
25830 #[doc = "CCx DMA request sent when update event occurs"]
25831 pub const ONUPDATE: Self = Self(0x01);
25832 }
25833 #[repr(transparent)]
25834 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25835 pub struct Sms(pub u8);
25836 impl Sms {
25837 #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."]
25838 pub const DISABLED: Self = Self(0);
25839 #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."]
25840 pub const ENCODER_MODE_1: Self = Self(0x01);
25841 #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."]
25842 pub const ENCODER_MODE_2: Self = Self(0x02);
25843 #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."]
25844 pub const ENCODER_MODE_3: Self = Self(0x03);
25845 #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."]
25846 pub const RESET_MODE: Self = Self(0x04);
25847 #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."]
25848 pub const GATED_MODE: Self = Self(0x05);
25849 #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."]
25850 pub const TRIGGER_MODE: Self = Self(0x06);
25851 #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."]
25852 pub const EXT_CLOCK_MODE: Self = Self(0x07);
25853 }
25854 #[repr(transparent)]
25855 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25856 pub struct Ossr(pub u8);
25857 impl Ossr {
25858 #[doc = "When inactive, OC/OCN outputs are disabled"]
25859 pub const DISABLED: Self = Self(0);
25860 #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"]
25861 pub const IDLELEVEL: Self = Self(0x01);
25862 }
25863 #[repr(transparent)]
25864 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25865 pub struct Ocpe(pub u8);
25866 impl Ocpe {
25867 #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"]
25868 pub const DISABLED: Self = Self(0);
25869 #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"]
25870 pub const ENABLED: Self = Self(0x01);
25871 }
25872 #[repr(transparent)]
25873 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25874 pub struct Etp(pub u8);
25875 impl Etp {
25876 #[doc = "ETR is noninverted, active at high level or rising edge"]
25877 pub const NOTINVERTED: Self = Self(0);
25878 #[doc = "ETR is inverted, active at low level or falling edge"]
25879 pub const INVERTED: Self = Self(0x01);
25880 }
25881 #[repr(transparent)]
25882 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25883 pub struct Icf(pub u8);
25884 impl Icf {
25885 #[doc = "No filter, sampling is done at fDTS"]
25886 pub const NOFILTER: Self = Self(0);
25887 #[doc = "fSAMPLING=fCK_INT, N=2"]
25888 pub const FCK_INT_N2: Self = Self(0x01);
25889 #[doc = "fSAMPLING=fCK_INT, N=4"]
25890 pub const FCK_INT_N4: Self = Self(0x02);
25891 #[doc = "fSAMPLING=fCK_INT, N=8"]
25892 pub const FCK_INT_N8: Self = Self(0x03);
25893 #[doc = "fSAMPLING=fDTS/2, N=6"]
25894 pub const FDTS_DIV2_N6: Self = Self(0x04);
25895 #[doc = "fSAMPLING=fDTS/2, N=8"]
25896 pub const FDTS_DIV2_N8: Self = Self(0x05);
25897 #[doc = "fSAMPLING=fDTS/4, N=6"]
25898 pub const FDTS_DIV4_N6: Self = Self(0x06);
25899 #[doc = "fSAMPLING=fDTS/4, N=8"]
25900 pub const FDTS_DIV4_N8: Self = Self(0x07);
25901 #[doc = "fSAMPLING=fDTS/8, N=6"]
25902 pub const FDTS_DIV8_N6: Self = Self(0x08);
25903 #[doc = "fSAMPLING=fDTS/8, N=8"]
25904 pub const FDTS_DIV8_N8: Self = Self(0x09);
25905 #[doc = "fSAMPLING=fDTS/16, N=5"]
25906 pub const FDTS_DIV16_N5: Self = Self(0x0a);
25907 #[doc = "fSAMPLING=fDTS/16, N=6"]
25908 pub const FDTS_DIV16_N6: Self = Self(0x0b);
25909 #[doc = "fSAMPLING=fDTS/16, N=8"]
25910 pub const FDTS_DIV16_N8: Self = Self(0x0c);
25911 #[doc = "fSAMPLING=fDTS/32, N=5"]
25912 pub const FDTS_DIV32_N5: Self = Self(0x0d);
25913 #[doc = "fSAMPLING=fDTS/32, N=6"]
25914 pub const FDTS_DIV32_N6: Self = Self(0x0e);
25915 #[doc = "fSAMPLING=fDTS/32, N=8"]
25916 pub const FDTS_DIV32_N8: Self = Self(0x0f);
25917 }
25918 #[repr(transparent)]
25919 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25920 pub struct Tis(pub u8);
25921 impl Tis {
25922 #[doc = "The TIMx_CH1 pin is connected to TI1 input"]
25923 pub const NORMAL: Self = Self(0);
25924 #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"]
25925 pub const XOR: Self = Self(0x01);
25926 }
25927 #[repr(transparent)]
25928 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25929 pub struct Urs(pub u8);
25930 impl Urs {
25931 #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"]
25932 pub const ANYEVENT: Self = Self(0);
25933 #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"]
25934 pub const COUNTERONLY: Self = Self(0x01);
25935 }
25936 #[repr(transparent)]
25937 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25938 pub struct Ece(pub u8);
25939 impl Ece {
25940 #[doc = "External clock mode 2 disabled"]
25941 pub const DISABLED: Self = Self(0);
25942 #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."]
25943 pub const ENABLED: Self = Self(0x01);
25944 }
25945 #[repr(transparent)]
25946 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25947 pub struct Ossi(pub u8);
25948 impl Ossi {
25949 #[doc = "When inactive, OC/OCN outputs are disabled"]
25950 pub const DISABLED: Self = Self(0);
25951 #[doc = "When inactive, OC/OCN outputs are forced to idle level"]
25952 pub const IDLELEVEL: Self = Self(0x01);
25953 }
25954 #[repr(transparent)]
25955 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25956 pub struct Cms(pub u8);
25957 impl Cms {
25958 #[doc = "The counter counts up or down depending on the direction bit"]
25959 pub const EDGEALIGNED: Self = Self(0);
25960 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."]
25961 pub const CENTERALIGNED1: Self = Self(0x01);
25962 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."]
25963 pub const CENTERALIGNED2: Self = Self(0x02);
25964 #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."]
25965 pub const CENTERALIGNED3: Self = Self(0x03);
25966 }
25967 #[repr(transparent)]
25968 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25969 pub struct Msm(pub u8);
25970 impl Msm {
25971 #[doc = "No action"]
25972 pub const NOSYNC: Self = Self(0);
25973 #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."]
25974 pub const SYNC: Self = Self(0x01);
25975 }
25976 #[repr(transparent)]
25977 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25978 pub struct Mms(pub u8);
25979 impl Mms {
25980 #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"]
25981 pub const RESET: Self = Self(0);
25982 #[doc = "The counter enable signal, CNT_EN, is used as trigger output"]
25983 pub const ENABLE: Self = Self(0x01);
25984 #[doc = "The update event is selected as trigger output"]
25985 pub const UPDATE: Self = Self(0x02);
25986 #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"]
25987 pub const COMPAREPULSE: Self = Self(0x03);
25988 #[doc = "OC1REF signal is used as trigger output"]
25989 pub const COMPAREOC1: Self = Self(0x04);
25990 #[doc = "OC2REF signal is used as trigger output"]
25991 pub const COMPAREOC2: Self = Self(0x05);
25992 #[doc = "OC3REF signal is used as trigger output"]
25993 pub const COMPAREOC3: Self = Self(0x06);
25994 #[doc = "OC4REF signal is used as trigger output"]
25995 pub const COMPAREOC4: Self = Self(0x07);
25996 }
25997 #[repr(transparent)]
25998 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
25999 pub struct Arpe(pub u8);
26000 impl Arpe {
26001 #[doc = "TIMx_APRR register is not buffered"]
26002 pub const DISABLED: Self = Self(0);
26003 #[doc = "TIMx_APRR register is buffered"]
26004 pub const ENABLED: Self = Self(0x01);
26005 }
26006 #[repr(transparent)]
26007 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26008 pub struct Ocm(pub u8);
26009 impl Ocm {
26010 #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
26011 pub const FROZEN: Self = Self(0);
26012 #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
26013 pub const ACTIVEONMATCH: Self = Self(0x01);
26014 #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
26015 pub const INACTIVEONMATCH: Self = Self(0x02);
26016 #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
26017 pub const TOGGLE: Self = Self(0x03);
26018 #[doc = "OCyREF is forced low"]
26019 pub const FORCEINACTIVE: Self = Self(0x04);
26020 #[doc = "OCyREF is forced high"]
26021 pub const FORCEACTIVE: Self = Self(0x05);
26022 #[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
26023 pub const PWMMODE1: Self = Self(0x06);
26024 #[doc = "Inversely to PwmMode1"]
26025 pub const PWMMODE2: Self = Self(0x07);
26026 }
26027 #[repr(transparent)]
26028 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26029 pub struct CcmrOutputCcs(pub u8);
26030 impl CcmrOutputCcs {
26031 #[doc = "CCx channel is configured as output"]
26032 pub const OUTPUT: Self = Self(0);
26033 }
26034 #[repr(transparent)]
26035 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26036 pub struct Ckd(pub u8);
26037 impl Ckd {
26038 #[doc = "t_DTS = t_CK_INT"]
26039 pub const DIV1: Self = Self(0);
26040 #[doc = "t_DTS = 2 × t_CK_INT"]
26041 pub const DIV2: Self = Self(0x01);
26042 #[doc = "t_DTS = 4 × t_CK_INT"]
26043 pub const DIV4: Self = Self(0x02);
26044 }
26045 #[repr(transparent)]
26046 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26047 pub struct Etps(pub u8);
26048 impl Etps {
26049 #[doc = "Prescaler OFF"]
26050 pub const DIV1: Self = Self(0);
26051 #[doc = "ETRP frequency divided by 2"]
26052 pub const DIV2: Self = Self(0x01);
26053 #[doc = "ETRP frequency divided by 4"]
26054 pub const DIV4: Self = Self(0x02);
26055 #[doc = "ETRP frequency divided by 8"]
26056 pub const DIV8: Self = Self(0x03);
26057 }
26058 }
26059}
26060pub mod spi_v2 {
26061 use crate::generic::*;
26062 #[doc = "Serial peripheral interface"]
26063 #[derive(Copy, Clone)]
26064 pub struct Spi(pub *mut u8);
26065 unsafe impl Send for Spi {}
26066 unsafe impl Sync for Spi {}
26067 impl Spi {
26068 #[doc = "control register 1"]
26069 pub fn cr1(self) -> Reg<regs::Cr1, RW> {
26070 unsafe { Reg::from_ptr(self.0.add(0usize)) }
26071 }
26072 #[doc = "control register 2"]
26073 pub fn cr2(self) -> Reg<regs::Cr2, RW> {
26074 unsafe { Reg::from_ptr(self.0.add(4usize)) }
26075 }
26076 #[doc = "status register"]
26077 pub fn sr(self) -> Reg<regs::Sr, RW> {
26078 unsafe { Reg::from_ptr(self.0.add(8usize)) }
26079 }
26080 #[doc = "data register"]
26081 pub fn dr(self) -> Reg<regs::Dr, RW> {
26082 unsafe { Reg::from_ptr(self.0.add(12usize)) }
26083 }
26084 #[doc = "CRC polynomial register"]
26085 pub fn crcpr(self) -> Reg<regs::Crcpr, RW> {
26086 unsafe { Reg::from_ptr(self.0.add(16usize)) }
26087 }
26088 #[doc = "RX CRC register"]
26089 pub fn rxcrcr(self) -> Reg<regs::Rxcrcr, R> {
26090 unsafe { Reg::from_ptr(self.0.add(20usize)) }
26091 }
26092 #[doc = "TX CRC register"]
26093 pub fn txcrcr(self) -> Reg<regs::Txcrcr, R> {
26094 unsafe { Reg::from_ptr(self.0.add(24usize)) }
26095 }
26096 }
26097 pub mod regs {
26098 use crate::generic::*;
26099 #[doc = "RX CRC register"]
26100 #[repr(transparent)]
26101 #[derive(Copy, Clone, Eq, PartialEq)]
26102 pub struct Rxcrcr(pub u32);
26103 impl Rxcrcr {
26104 #[doc = "Rx CRC register"]
26105 pub const fn rx_crc(&self) -> u16 {
26106 let val = (self.0 >> 0usize) & 0xffff;
26107 val as u16
26108 }
26109 #[doc = "Rx CRC register"]
26110 pub fn set_rx_crc(&mut self, val: u16) {
26111 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
26112 }
26113 }
26114 impl Default for Rxcrcr {
26115 fn default() -> Rxcrcr {
26116 Rxcrcr(0)
26117 }
26118 }
26119 #[doc = "data register"]
26120 #[repr(transparent)]
26121 #[derive(Copy, Clone, Eq, PartialEq)]
26122 pub struct Dr(pub u32);
26123 impl Dr {
26124 #[doc = "Data register"]
26125 pub const fn dr(&self) -> u16 {
26126 let val = (self.0 >> 0usize) & 0xffff;
26127 val as u16
26128 }
26129 #[doc = "Data register"]
26130 pub fn set_dr(&mut self, val: u16) {
26131 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
26132 }
26133 }
26134 impl Default for Dr {
26135 fn default() -> Dr {
26136 Dr(0)
26137 }
26138 }
26139 #[doc = "control register 1"]
26140 #[repr(transparent)]
26141 #[derive(Copy, Clone, Eq, PartialEq)]
26142 pub struct Cr1(pub u32);
26143 impl Cr1 {
26144 #[doc = "Clock phase"]
26145 pub const fn cpha(&self) -> super::vals::Cpha {
26146 let val = (self.0 >> 0usize) & 0x01;
26147 super::vals::Cpha(val as u8)
26148 }
26149 #[doc = "Clock phase"]
26150 pub fn set_cpha(&mut self, val: super::vals::Cpha) {
26151 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
26152 }
26153 #[doc = "Clock polarity"]
26154 pub const fn cpol(&self) -> super::vals::Cpol {
26155 let val = (self.0 >> 1usize) & 0x01;
26156 super::vals::Cpol(val as u8)
26157 }
26158 #[doc = "Clock polarity"]
26159 pub fn set_cpol(&mut self, val: super::vals::Cpol) {
26160 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
26161 }
26162 #[doc = "Master selection"]
26163 pub const fn mstr(&self) -> super::vals::Mstr {
26164 let val = (self.0 >> 2usize) & 0x01;
26165 super::vals::Mstr(val as u8)
26166 }
26167 #[doc = "Master selection"]
26168 pub fn set_mstr(&mut self, val: super::vals::Mstr) {
26169 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
26170 }
26171 #[doc = "Baud rate control"]
26172 pub const fn br(&self) -> super::vals::Br {
26173 let val = (self.0 >> 3usize) & 0x07;
26174 super::vals::Br(val as u8)
26175 }
26176 #[doc = "Baud rate control"]
26177 pub fn set_br(&mut self, val: super::vals::Br) {
26178 self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize);
26179 }
26180 #[doc = "SPI enable"]
26181 pub const fn spe(&self) -> bool {
26182 let val = (self.0 >> 6usize) & 0x01;
26183 val != 0
26184 }
26185 #[doc = "SPI enable"]
26186 pub fn set_spe(&mut self, val: bool) {
26187 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
26188 }
26189 #[doc = "Frame format"]
26190 pub const fn lsbfirst(&self) -> super::vals::Lsbfirst {
26191 let val = (self.0 >> 7usize) & 0x01;
26192 super::vals::Lsbfirst(val as u8)
26193 }
26194 #[doc = "Frame format"]
26195 pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) {
26196 self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize);
26197 }
26198 #[doc = "Internal slave select"]
26199 pub const fn ssi(&self) -> bool {
26200 let val = (self.0 >> 8usize) & 0x01;
26201 val != 0
26202 }
26203 #[doc = "Internal slave select"]
26204 pub fn set_ssi(&mut self, val: bool) {
26205 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
26206 }
26207 #[doc = "Software slave management"]
26208 pub const fn ssm(&self) -> bool {
26209 let val = (self.0 >> 9usize) & 0x01;
26210 val != 0
26211 }
26212 #[doc = "Software slave management"]
26213 pub fn set_ssm(&mut self, val: bool) {
26214 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
26215 }
26216 #[doc = "Receive only"]
26217 pub const fn rxonly(&self) -> super::vals::Rxonly {
26218 let val = (self.0 >> 10usize) & 0x01;
26219 super::vals::Rxonly(val as u8)
26220 }
26221 #[doc = "Receive only"]
26222 pub fn set_rxonly(&mut self, val: super::vals::Rxonly) {
26223 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
26224 }
26225 #[doc = "CRC length"]
26226 pub const fn crcl(&self) -> super::vals::Crcl {
26227 let val = (self.0 >> 11usize) & 0x01;
26228 super::vals::Crcl(val as u8)
26229 }
26230 #[doc = "CRC length"]
26231 pub fn set_crcl(&mut self, val: super::vals::Crcl) {
26232 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
26233 }
26234 #[doc = "CRC transfer next"]
26235 pub const fn crcnext(&self) -> super::vals::Crcnext {
26236 let val = (self.0 >> 12usize) & 0x01;
26237 super::vals::Crcnext(val as u8)
26238 }
26239 #[doc = "CRC transfer next"]
26240 pub fn set_crcnext(&mut self, val: super::vals::Crcnext) {
26241 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
26242 }
26243 #[doc = "Hardware CRC calculation enable"]
26244 pub const fn crcen(&self) -> bool {
26245 let val = (self.0 >> 13usize) & 0x01;
26246 val != 0
26247 }
26248 #[doc = "Hardware CRC calculation enable"]
26249 pub fn set_crcen(&mut self, val: bool) {
26250 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
26251 }
26252 #[doc = "Output enable in bidirectional mode"]
26253 pub const fn bidioe(&self) -> super::vals::Bidioe {
26254 let val = (self.0 >> 14usize) & 0x01;
26255 super::vals::Bidioe(val as u8)
26256 }
26257 #[doc = "Output enable in bidirectional mode"]
26258 pub fn set_bidioe(&mut self, val: super::vals::Bidioe) {
26259 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
26260 }
26261 #[doc = "Bidirectional data mode enable"]
26262 pub const fn bidimode(&self) -> super::vals::Bidimode {
26263 let val = (self.0 >> 15usize) & 0x01;
26264 super::vals::Bidimode(val as u8)
26265 }
26266 #[doc = "Bidirectional data mode enable"]
26267 pub fn set_bidimode(&mut self, val: super::vals::Bidimode) {
26268 self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize);
26269 }
26270 }
26271 impl Default for Cr1 {
26272 fn default() -> Cr1 {
26273 Cr1(0)
26274 }
26275 }
26276 #[doc = "CRC polynomial register"]
26277 #[repr(transparent)]
26278 #[derive(Copy, Clone, Eq, PartialEq)]
26279 pub struct Crcpr(pub u32);
26280 impl Crcpr {
26281 #[doc = "CRC polynomial register"]
26282 pub const fn crcpoly(&self) -> u16 {
26283 let val = (self.0 >> 0usize) & 0xffff;
26284 val as u16
26285 }
26286 #[doc = "CRC polynomial register"]
26287 pub fn set_crcpoly(&mut self, val: u16) {
26288 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
26289 }
26290 }
26291 impl Default for Crcpr {
26292 fn default() -> Crcpr {
26293 Crcpr(0)
26294 }
26295 }
26296 #[doc = "control register 2"]
26297 #[repr(transparent)]
26298 #[derive(Copy, Clone, Eq, PartialEq)]
26299 pub struct Cr2(pub u32);
26300 impl Cr2 {
26301 #[doc = "Rx buffer DMA enable"]
26302 pub const fn rxdmaen(&self) -> bool {
26303 let val = (self.0 >> 0usize) & 0x01;
26304 val != 0
26305 }
26306 #[doc = "Rx buffer DMA enable"]
26307 pub fn set_rxdmaen(&mut self, val: bool) {
26308 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
26309 }
26310 #[doc = "Tx buffer DMA enable"]
26311 pub const fn txdmaen(&self) -> bool {
26312 let val = (self.0 >> 1usize) & 0x01;
26313 val != 0
26314 }
26315 #[doc = "Tx buffer DMA enable"]
26316 pub fn set_txdmaen(&mut self, val: bool) {
26317 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
26318 }
26319 #[doc = "SS output enable"]
26320 pub const fn ssoe(&self) -> bool {
26321 let val = (self.0 >> 2usize) & 0x01;
26322 val != 0
26323 }
26324 #[doc = "SS output enable"]
26325 pub fn set_ssoe(&mut self, val: bool) {
26326 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
26327 }
26328 #[doc = "NSS pulse management"]
26329 pub const fn nssp(&self) -> bool {
26330 let val = (self.0 >> 3usize) & 0x01;
26331 val != 0
26332 }
26333 #[doc = "NSS pulse management"]
26334 pub fn set_nssp(&mut self, val: bool) {
26335 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
26336 }
26337 #[doc = "Frame format"]
26338 pub const fn frf(&self) -> super::vals::Frf {
26339 let val = (self.0 >> 4usize) & 0x01;
26340 super::vals::Frf(val as u8)
26341 }
26342 #[doc = "Frame format"]
26343 pub fn set_frf(&mut self, val: super::vals::Frf) {
26344 self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize);
26345 }
26346 #[doc = "Error interrupt enable"]
26347 pub const fn errie(&self) -> bool {
26348 let val = (self.0 >> 5usize) & 0x01;
26349 val != 0
26350 }
26351 #[doc = "Error interrupt enable"]
26352 pub fn set_errie(&mut self, val: bool) {
26353 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
26354 }
26355 #[doc = "RX buffer not empty interrupt enable"]
26356 pub const fn rxneie(&self) -> bool {
26357 let val = (self.0 >> 6usize) & 0x01;
26358 val != 0
26359 }
26360 #[doc = "RX buffer not empty interrupt enable"]
26361 pub fn set_rxneie(&mut self, val: bool) {
26362 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
26363 }
26364 #[doc = "Tx buffer empty interrupt enable"]
26365 pub const fn txeie(&self) -> bool {
26366 let val = (self.0 >> 7usize) & 0x01;
26367 val != 0
26368 }
26369 #[doc = "Tx buffer empty interrupt enable"]
26370 pub fn set_txeie(&mut self, val: bool) {
26371 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
26372 }
26373 #[doc = "Data size"]
26374 pub const fn ds(&self) -> super::vals::Ds {
26375 let val = (self.0 >> 8usize) & 0x0f;
26376 super::vals::Ds(val as u8)
26377 }
26378 #[doc = "Data size"]
26379 pub fn set_ds(&mut self, val: super::vals::Ds) {
26380 self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize);
26381 }
26382 #[doc = "FIFO reception threshold"]
26383 pub const fn frxth(&self) -> super::vals::Frxth {
26384 let val = (self.0 >> 12usize) & 0x01;
26385 super::vals::Frxth(val as u8)
26386 }
26387 #[doc = "FIFO reception threshold"]
26388 pub fn set_frxth(&mut self, val: super::vals::Frxth) {
26389 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
26390 }
26391 #[doc = "Last DMA transfer for reception"]
26392 pub const fn ldma_rx(&self) -> super::vals::LdmaRx {
26393 let val = (self.0 >> 13usize) & 0x01;
26394 super::vals::LdmaRx(val as u8)
26395 }
26396 #[doc = "Last DMA transfer for reception"]
26397 pub fn set_ldma_rx(&mut self, val: super::vals::LdmaRx) {
26398 self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize);
26399 }
26400 #[doc = "Last DMA transfer for transmission"]
26401 pub const fn ldma_tx(&self) -> super::vals::LdmaTx {
26402 let val = (self.0 >> 14usize) & 0x01;
26403 super::vals::LdmaTx(val as u8)
26404 }
26405 #[doc = "Last DMA transfer for transmission"]
26406 pub fn set_ldma_tx(&mut self, val: super::vals::LdmaTx) {
26407 self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize);
26408 }
26409 }
26410 impl Default for Cr2 {
26411 fn default() -> Cr2 {
26412 Cr2(0)
26413 }
26414 }
26415 #[doc = "status register"]
26416 #[repr(transparent)]
26417 #[derive(Copy, Clone, Eq, PartialEq)]
26418 pub struct Sr(pub u32);
26419 impl Sr {
26420 #[doc = "Receive buffer not empty"]
26421 pub const fn rxne(&self) -> bool {
26422 let val = (self.0 >> 0usize) & 0x01;
26423 val != 0
26424 }
26425 #[doc = "Receive buffer not empty"]
26426 pub fn set_rxne(&mut self, val: bool) {
26427 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
26428 }
26429 #[doc = "Transmit buffer empty"]
26430 pub const fn txe(&self) -> bool {
26431 let val = (self.0 >> 1usize) & 0x01;
26432 val != 0
26433 }
26434 #[doc = "Transmit buffer empty"]
26435 pub fn set_txe(&mut self, val: bool) {
26436 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
26437 }
26438 #[doc = "CRC error flag"]
26439 pub const fn crcerr(&self) -> bool {
26440 let val = (self.0 >> 4usize) & 0x01;
26441 val != 0
26442 }
26443 #[doc = "CRC error flag"]
26444 pub fn set_crcerr(&mut self, val: bool) {
26445 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
26446 }
26447 #[doc = "Mode fault"]
26448 pub const fn modf(&self) -> bool {
26449 let val = (self.0 >> 5usize) & 0x01;
26450 val != 0
26451 }
26452 #[doc = "Mode fault"]
26453 pub fn set_modf(&mut self, val: bool) {
26454 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
26455 }
26456 #[doc = "Overrun flag"]
26457 pub const fn ovr(&self) -> bool {
26458 let val = (self.0 >> 6usize) & 0x01;
26459 val != 0
26460 }
26461 #[doc = "Overrun flag"]
26462 pub fn set_ovr(&mut self, val: bool) {
26463 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
26464 }
26465 #[doc = "Busy flag"]
26466 pub const fn bsy(&self) -> bool {
26467 let val = (self.0 >> 7usize) & 0x01;
26468 val != 0
26469 }
26470 #[doc = "Busy flag"]
26471 pub fn set_bsy(&mut self, val: bool) {
26472 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
26473 }
26474 #[doc = "Frame format error"]
26475 pub const fn fre(&self) -> bool {
26476 let val = (self.0 >> 8usize) & 0x01;
26477 val != 0
26478 }
26479 #[doc = "Frame format error"]
26480 pub fn set_fre(&mut self, val: bool) {
26481 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
26482 }
26483 #[doc = "FIFO reception level"]
26484 pub const fn frlvl(&self) -> u8 {
26485 let val = (self.0 >> 9usize) & 0x03;
26486 val as u8
26487 }
26488 #[doc = "FIFO reception level"]
26489 pub fn set_frlvl(&mut self, val: u8) {
26490 self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize);
26491 }
26492 #[doc = "FIFO Transmission Level"]
26493 pub const fn ftlvl(&self) -> u8 {
26494 let val = (self.0 >> 11usize) & 0x03;
26495 val as u8
26496 }
26497 #[doc = "FIFO Transmission Level"]
26498 pub fn set_ftlvl(&mut self, val: u8) {
26499 self.0 = (self.0 & !(0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize);
26500 }
26501 }
26502 impl Default for Sr {
26503 fn default() -> Sr {
26504 Sr(0)
26505 }
26506 }
26507 #[doc = "TX CRC register"]
26508 #[repr(transparent)]
26509 #[derive(Copy, Clone, Eq, PartialEq)]
26510 pub struct Txcrcr(pub u32);
26511 impl Txcrcr {
26512 #[doc = "Tx CRC register"]
26513 pub const fn tx_crc(&self) -> u16 {
26514 let val = (self.0 >> 0usize) & 0xffff;
26515 val as u16
26516 }
26517 #[doc = "Tx CRC register"]
26518 pub fn set_tx_crc(&mut self, val: u16) {
26519 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
26520 }
26521 }
26522 impl Default for Txcrcr {
26523 fn default() -> Txcrcr {
26524 Txcrcr(0)
26525 }
26526 }
26527 }
26528 pub mod vals {
26529 use crate::generic::*;
26530 #[repr(transparent)]
26531 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26532 pub struct Bidioe(pub u8);
26533 impl Bidioe {
26534 #[doc = "Output disabled (receive-only mode)"]
26535 pub const OUTPUTDISABLED: Self = Self(0);
26536 #[doc = "Output enabled (transmit-only mode)"]
26537 pub const OUTPUTENABLED: Self = Self(0x01);
26538 }
26539 #[repr(transparent)]
26540 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26541 pub struct LdmaRx(pub u8);
26542 impl LdmaRx {
26543 #[doc = "Number of data to transfer for receive is even"]
26544 pub const EVEN: Self = Self(0);
26545 #[doc = "Number of data to transfer for receive is odd"]
26546 pub const ODD: Self = Self(0x01);
26547 }
26548 #[repr(transparent)]
26549 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26550 pub struct Rxonly(pub u8);
26551 impl Rxonly {
26552 #[doc = "Full duplex (Transmit and receive)"]
26553 pub const FULLDUPLEX: Self = Self(0);
26554 #[doc = "Output disabled (Receive-only mode)"]
26555 pub const OUTPUTDISABLED: Self = Self(0x01);
26556 }
26557 #[repr(transparent)]
26558 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26559 pub struct Bidimode(pub u8);
26560 impl Bidimode {
26561 #[doc = "2-line unidirectional data mode selected"]
26562 pub const UNIDIRECTIONAL: Self = Self(0);
26563 #[doc = "1-line bidirectional data mode selected"]
26564 pub const BIDIRECTIONAL: Self = Self(0x01);
26565 }
26566 #[repr(transparent)]
26567 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26568 pub struct Ftlvlr(pub u8);
26569 impl Ftlvlr {
26570 #[doc = "Tx FIFO Empty"]
26571 pub const EMPTY: Self = Self(0);
26572 #[doc = "Tx 1/4 FIFO"]
26573 pub const QUARTER: Self = Self(0x01);
26574 #[doc = "Tx 1/2 FIFO"]
26575 pub const HALF: Self = Self(0x02);
26576 #[doc = "Tx FIFO full"]
26577 pub const FULL: Self = Self(0x03);
26578 }
26579 #[repr(transparent)]
26580 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26581 pub struct Ds(pub u8);
26582 impl Ds {
26583 #[doc = "4-bit"]
26584 pub const FOURBIT: Self = Self(0x03);
26585 #[doc = "5-bit"]
26586 pub const FIVEBIT: Self = Self(0x04);
26587 #[doc = "6-bit"]
26588 pub const SIXBIT: Self = Self(0x05);
26589 #[doc = "7-bit"]
26590 pub const SEVENBIT: Self = Self(0x06);
26591 #[doc = "8-bit"]
26592 pub const EIGHTBIT: Self = Self(0x07);
26593 #[doc = "9-bit"]
26594 pub const NINEBIT: Self = Self(0x08);
26595 #[doc = "10-bit"]
26596 pub const TENBIT: Self = Self(0x09);
26597 #[doc = "11-bit"]
26598 pub const ELEVENBIT: Self = Self(0x0a);
26599 #[doc = "12-bit"]
26600 pub const TWELVEBIT: Self = Self(0x0b);
26601 #[doc = "13-bit"]
26602 pub const THIRTEENBIT: Self = Self(0x0c);
26603 #[doc = "14-bit"]
26604 pub const FOURTEENBIT: Self = Self(0x0d);
26605 #[doc = "15-bit"]
26606 pub const FIFTEENBIT: Self = Self(0x0e);
26607 #[doc = "16-bit"]
26608 pub const SIXTEENBIT: Self = Self(0x0f);
26609 }
26610 #[repr(transparent)]
26611 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26612 pub struct Frxth(pub u8);
26613 impl Frxth {
26614 #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"]
26615 pub const HALF: Self = Self(0);
26616 #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"]
26617 pub const QUARTER: Self = Self(0x01);
26618 }
26619 #[repr(transparent)]
26620 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26621 pub struct Frlvlr(pub u8);
26622 impl Frlvlr {
26623 #[doc = "Rx FIFO Empty"]
26624 pub const EMPTY: Self = Self(0);
26625 #[doc = "Rx 1/4 FIFO"]
26626 pub const QUARTER: Self = Self(0x01);
26627 #[doc = "Rx 1/2 FIFO"]
26628 pub const HALF: Self = Self(0x02);
26629 #[doc = "Rx FIFO full"]
26630 pub const FULL: Self = Self(0x03);
26631 }
26632 #[repr(transparent)]
26633 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26634 pub struct Cpol(pub u8);
26635 impl Cpol {
26636 #[doc = "CK to 0 when idle"]
26637 pub const IDLELOW: Self = Self(0);
26638 #[doc = "CK to 1 when idle"]
26639 pub const IDLEHIGH: Self = Self(0x01);
26640 }
26641 #[repr(transparent)]
26642 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26643 pub struct Br(pub u8);
26644 impl Br {
26645 #[doc = "f_PCLK / 2"]
26646 pub const DIV2: Self = Self(0);
26647 #[doc = "f_PCLK / 4"]
26648 pub const DIV4: Self = Self(0x01);
26649 #[doc = "f_PCLK / 8"]
26650 pub const DIV8: Self = Self(0x02);
26651 #[doc = "f_PCLK / 16"]
26652 pub const DIV16: Self = Self(0x03);
26653 #[doc = "f_PCLK / 32"]
26654 pub const DIV32: Self = Self(0x04);
26655 #[doc = "f_PCLK / 64"]
26656 pub const DIV64: Self = Self(0x05);
26657 #[doc = "f_PCLK / 128"]
26658 pub const DIV128: Self = Self(0x06);
26659 #[doc = "f_PCLK / 256"]
26660 pub const DIV256: Self = Self(0x07);
26661 }
26662 #[repr(transparent)]
26663 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26664 pub struct Lsbfirst(pub u8);
26665 impl Lsbfirst {
26666 #[doc = "Data is transmitted/received with the MSB first"]
26667 pub const MSBFIRST: Self = Self(0);
26668 #[doc = "Data is transmitted/received with the LSB first"]
26669 pub const LSBFIRST: Self = Self(0x01);
26670 }
26671 #[repr(transparent)]
26672 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26673 pub struct Frer(pub u8);
26674 impl Frer {
26675 #[doc = "No frame format error"]
26676 pub const NOERROR: Self = Self(0);
26677 #[doc = "A frame format error occurred"]
26678 pub const ERROR: Self = Self(0x01);
26679 }
26680 #[repr(transparent)]
26681 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26682 pub struct Crcl(pub u8);
26683 impl Crcl {
26684 #[doc = "8-bit CRC length"]
26685 pub const EIGHTBIT: Self = Self(0);
26686 #[doc = "16-bit CRC length"]
26687 pub const SIXTEENBIT: Self = Self(0x01);
26688 }
26689 #[repr(transparent)]
26690 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26691 pub struct Crcnext(pub u8);
26692 impl Crcnext {
26693 #[doc = "Next transmit value is from Tx buffer"]
26694 pub const TXBUFFER: Self = Self(0);
26695 #[doc = "Next transmit value is from Tx CRC register"]
26696 pub const CRC: Self = Self(0x01);
26697 }
26698 #[repr(transparent)]
26699 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26700 pub struct Frf(pub u8);
26701 impl Frf {
26702 #[doc = "SPI Motorola mode"]
26703 pub const MOTOROLA: Self = Self(0);
26704 #[doc = "SPI TI mode"]
26705 pub const TI: Self = Self(0x01);
26706 }
26707 #[repr(transparent)]
26708 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26709 pub struct LdmaTx(pub u8);
26710 impl LdmaTx {
26711 #[doc = "Number of data to transfer for transmit is even"]
26712 pub const EVEN: Self = Self(0);
26713 #[doc = "Number of data to transfer for transmit is odd"]
26714 pub const ODD: Self = Self(0x01);
26715 }
26716 #[repr(transparent)]
26717 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26718 pub struct Mstr(pub u8);
26719 impl Mstr {
26720 #[doc = "Slave configuration"]
26721 pub const SLAVE: Self = Self(0);
26722 #[doc = "Master configuration"]
26723 pub const MASTER: Self = Self(0x01);
26724 }
26725 #[repr(transparent)]
26726 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26727 pub struct Cpha(pub u8);
26728 impl Cpha {
26729 #[doc = "The first clock transition is the first data capture edge"]
26730 pub const FIRSTEDGE: Self = Self(0);
26731 #[doc = "The second clock transition is the first data capture edge"]
26732 pub const SECONDEDGE: Self = Self(0x01);
26733 }
26734 }
26735}
26736pub mod usart_v1 {
26737 use crate::generic::*;
26738 #[doc = "Universal asynchronous receiver transmitter"]
26739 #[derive(Copy, Clone)]
26740 pub struct Uart(pub *mut u8);
26741 unsafe impl Send for Uart {}
26742 unsafe impl Sync for Uart {}
26743 impl Uart {
26744 #[doc = "Status register"]
26745 pub fn sr(self) -> Reg<regs::Sr, RW> {
26746 unsafe { Reg::from_ptr(self.0.add(0usize)) }
26747 }
26748 #[doc = "Data register"]
26749 pub fn dr(self) -> Reg<regs::Dr, RW> {
26750 unsafe { Reg::from_ptr(self.0.add(4usize)) }
26751 }
26752 #[doc = "Baud rate register"]
26753 pub fn brr(self) -> Reg<regs::Brr, RW> {
26754 unsafe { Reg::from_ptr(self.0.add(8usize)) }
26755 }
26756 #[doc = "Control register 1"]
26757 pub fn cr1(self) -> Reg<regs::Cr1, RW> {
26758 unsafe { Reg::from_ptr(self.0.add(12usize)) }
26759 }
26760 #[doc = "Control register 2"]
26761 pub fn cr2(self) -> Reg<regs::Cr2, RW> {
26762 unsafe { Reg::from_ptr(self.0.add(16usize)) }
26763 }
26764 #[doc = "Control register 3"]
26765 pub fn cr3(self) -> Reg<regs::Cr3, RW> {
26766 unsafe { Reg::from_ptr(self.0.add(20usize)) }
26767 }
26768 }
26769 #[doc = "Universal synchronous asynchronous receiver transmitter"]
26770 #[derive(Copy, Clone)]
26771 pub struct Usart(pub *mut u8);
26772 unsafe impl Send for Usart {}
26773 unsafe impl Sync for Usart {}
26774 impl Usart {
26775 #[doc = "Status register"]
26776 pub fn sr(self) -> Reg<regs::Sr, RW> {
26777 unsafe { Reg::from_ptr(self.0.add(0usize)) }
26778 }
26779 #[doc = "Data register"]
26780 pub fn dr(self) -> Reg<regs::Dr, RW> {
26781 unsafe { Reg::from_ptr(self.0.add(4usize)) }
26782 }
26783 #[doc = "Baud rate register"]
26784 pub fn brr(self) -> Reg<regs::Brr, RW> {
26785 unsafe { Reg::from_ptr(self.0.add(8usize)) }
26786 }
26787 #[doc = "Control register 1"]
26788 pub fn cr1(self) -> Reg<regs::Cr1, RW> {
26789 unsafe { Reg::from_ptr(self.0.add(12usize)) }
26790 }
26791 #[doc = "Control register 2"]
26792 pub fn cr2(self) -> Reg<regs::Cr2Usart, RW> {
26793 unsafe { Reg::from_ptr(self.0.add(16usize)) }
26794 }
26795 #[doc = "Control register 3"]
26796 pub fn cr3(self) -> Reg<regs::Cr3Usart, RW> {
26797 unsafe { Reg::from_ptr(self.0.add(20usize)) }
26798 }
26799 #[doc = "Guard time and prescaler register"]
26800 pub fn gtpr(self) -> Reg<regs::Gtpr, RW> {
26801 unsafe { Reg::from_ptr(self.0.add(24usize)) }
26802 }
26803 }
26804 pub mod vals {
26805 use crate::generic::*;
26806 #[repr(transparent)]
26807 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26808 pub struct Ps(pub u8);
26809 impl Ps {
26810 #[doc = "Even parity"]
26811 pub const EVEN: Self = Self(0);
26812 #[doc = "Odd parity"]
26813 pub const ODD: Self = Self(0x01);
26814 }
26815 #[repr(transparent)]
26816 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26817 pub struct Cpol(pub u8);
26818 impl Cpol {
26819 #[doc = "Steady low value on CK pin outside transmission window"]
26820 pub const LOW: Self = Self(0);
26821 #[doc = "Steady high value on CK pin outside transmission window"]
26822 pub const HIGH: Self = Self(0x01);
26823 }
26824 #[repr(transparent)]
26825 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26826 pub struct Rwu(pub u8);
26827 impl Rwu {
26828 #[doc = "Receiver in active mode"]
26829 pub const ACTIVE: Self = Self(0);
26830 #[doc = "Receiver in mute mode"]
26831 pub const MUTE: Self = Self(0x01);
26832 }
26833 #[repr(transparent)]
26834 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26835 pub struct M(pub u8);
26836 impl M {
26837 #[doc = "8 data bits"]
26838 pub const M8: Self = Self(0);
26839 #[doc = "9 data bits"]
26840 pub const M9: Self = Self(0x01);
26841 }
26842 #[repr(transparent)]
26843 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26844 pub struct Hdsel(pub u8);
26845 impl Hdsel {
26846 #[doc = "Half duplex mode is not selected"]
26847 pub const FULLDUPLEX: Self = Self(0);
26848 #[doc = "Half duplex mode is selected"]
26849 pub const HALFDUPLEX: Self = Self(0x01);
26850 }
26851 #[repr(transparent)]
26852 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26853 pub struct Stop(pub u8);
26854 impl Stop {
26855 #[doc = "1 stop bit"]
26856 pub const STOP1: Self = Self(0);
26857 #[doc = "0.5 stop bits"]
26858 pub const STOP0P5: Self = Self(0x01);
26859 #[doc = "2 stop bits"]
26860 pub const STOP2: Self = Self(0x02);
26861 #[doc = "1.5 stop bits"]
26862 pub const STOP1P5: Self = Self(0x03);
26863 }
26864 #[repr(transparent)]
26865 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26866 pub struct Lbdl(pub u8);
26867 impl Lbdl {
26868 #[doc = "10-bit break detection"]
26869 pub const LBDL10: Self = Self(0);
26870 #[doc = "11-bit break detection"]
26871 pub const LBDL11: Self = Self(0x01);
26872 }
26873 #[repr(transparent)]
26874 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26875 pub struct Wake(pub u8);
26876 impl Wake {
26877 #[doc = "USART wakeup on idle line"]
26878 pub const IDLELINE: Self = Self(0);
26879 #[doc = "USART wakeup on address mark"]
26880 pub const ADDRESSMARK: Self = Self(0x01);
26881 }
26882 #[repr(transparent)]
26883 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26884 pub struct Irlp(pub u8);
26885 impl Irlp {
26886 #[doc = "Normal mode"]
26887 pub const NORMAL: Self = Self(0);
26888 #[doc = "Low-power mode"]
26889 pub const LOWPOWER: Self = Self(0x01);
26890 }
26891 #[repr(transparent)]
26892 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26893 pub struct Sbk(pub u8);
26894 impl Sbk {
26895 #[doc = "No break character is transmitted"]
26896 pub const NOBREAK: Self = Self(0);
26897 #[doc = "Break character transmitted"]
26898 pub const BREAK: Self = Self(0x01);
26899 }
26900 #[repr(transparent)]
26901 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
26902 pub struct Cpha(pub u8);
26903 impl Cpha {
26904 #[doc = "The first clock transition is the first data capture edge"]
26905 pub const FIRST: Self = Self(0);
26906 #[doc = "The second clock transition is the first data capture edge"]
26907 pub const SECOND: Self = Self(0x01);
26908 }
26909 }
26910 pub mod regs {
26911 use crate::generic::*;
26912 #[doc = "Guard time and prescaler register"]
26913 #[repr(transparent)]
26914 #[derive(Copy, Clone, Eq, PartialEq)]
26915 pub struct Gtpr(pub u32);
26916 impl Gtpr {
26917 #[doc = "Prescaler value"]
26918 pub const fn psc(&self) -> u8 {
26919 let val = (self.0 >> 0usize) & 0xff;
26920 val as u8
26921 }
26922 #[doc = "Prescaler value"]
26923 pub fn set_psc(&mut self, val: u8) {
26924 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
26925 }
26926 #[doc = "Guard time value"]
26927 pub const fn gt(&self) -> u8 {
26928 let val = (self.0 >> 8usize) & 0xff;
26929 val as u8
26930 }
26931 #[doc = "Guard time value"]
26932 pub fn set_gt(&mut self, val: u8) {
26933 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
26934 }
26935 }
26936 impl Default for Gtpr {
26937 fn default() -> Gtpr {
26938 Gtpr(0)
26939 }
26940 }
26941 #[doc = "Control register 3"]
26942 #[repr(transparent)]
26943 #[derive(Copy, Clone, Eq, PartialEq)]
26944 pub struct Cr3Usart(pub u32);
26945 impl Cr3Usart {
26946 #[doc = "Error interrupt enable"]
26947 pub const fn eie(&self) -> bool {
26948 let val = (self.0 >> 0usize) & 0x01;
26949 val != 0
26950 }
26951 #[doc = "Error interrupt enable"]
26952 pub fn set_eie(&mut self, val: bool) {
26953 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
26954 }
26955 #[doc = "IrDA mode enable"]
26956 pub const fn iren(&self) -> bool {
26957 let val = (self.0 >> 1usize) & 0x01;
26958 val != 0
26959 }
26960 #[doc = "IrDA mode enable"]
26961 pub fn set_iren(&mut self, val: bool) {
26962 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
26963 }
26964 #[doc = "IrDA low-power"]
26965 pub const fn irlp(&self) -> super::vals::Irlp {
26966 let val = (self.0 >> 2usize) & 0x01;
26967 super::vals::Irlp(val as u8)
26968 }
26969 #[doc = "IrDA low-power"]
26970 pub fn set_irlp(&mut self, val: super::vals::Irlp) {
26971 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
26972 }
26973 #[doc = "Half-duplex selection"]
26974 pub const fn hdsel(&self) -> super::vals::Hdsel {
26975 let val = (self.0 >> 3usize) & 0x01;
26976 super::vals::Hdsel(val as u8)
26977 }
26978 #[doc = "Half-duplex selection"]
26979 pub fn set_hdsel(&mut self, val: super::vals::Hdsel) {
26980 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
26981 }
26982 #[doc = "Smartcard NACK enable"]
26983 pub const fn nack(&self) -> bool {
26984 let val = (self.0 >> 4usize) & 0x01;
26985 val != 0
26986 }
26987 #[doc = "Smartcard NACK enable"]
26988 pub fn set_nack(&mut self, val: bool) {
26989 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
26990 }
26991 #[doc = "Smartcard mode enable"]
26992 pub const fn scen(&self) -> bool {
26993 let val = (self.0 >> 5usize) & 0x01;
26994 val != 0
26995 }
26996 #[doc = "Smartcard mode enable"]
26997 pub fn set_scen(&mut self, val: bool) {
26998 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
26999 }
27000 #[doc = "DMA enable receiver"]
27001 pub const fn dmar(&self) -> bool {
27002 let val = (self.0 >> 6usize) & 0x01;
27003 val != 0
27004 }
27005 #[doc = "DMA enable receiver"]
27006 pub fn set_dmar(&mut self, val: bool) {
27007 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
27008 }
27009 #[doc = "DMA enable transmitter"]
27010 pub const fn dmat(&self) -> bool {
27011 let val = (self.0 >> 7usize) & 0x01;
27012 val != 0
27013 }
27014 #[doc = "DMA enable transmitter"]
27015 pub fn set_dmat(&mut self, val: bool) {
27016 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
27017 }
27018 #[doc = "RTS enable"]
27019 pub const fn rtse(&self) -> bool {
27020 let val = (self.0 >> 8usize) & 0x01;
27021 val != 0
27022 }
27023 #[doc = "RTS enable"]
27024 pub fn set_rtse(&mut self, val: bool) {
27025 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
27026 }
27027 #[doc = "CTS enable"]
27028 pub const fn ctse(&self) -> bool {
27029 let val = (self.0 >> 9usize) & 0x01;
27030 val != 0
27031 }
27032 #[doc = "CTS enable"]
27033 pub fn set_ctse(&mut self, val: bool) {
27034 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
27035 }
27036 #[doc = "CTS interrupt enable"]
27037 pub const fn ctsie(&self) -> bool {
27038 let val = (self.0 >> 10usize) & 0x01;
27039 val != 0
27040 }
27041 #[doc = "CTS interrupt enable"]
27042 pub fn set_ctsie(&mut self, val: bool) {
27043 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
27044 }
27045 }
27046 impl Default for Cr3Usart {
27047 fn default() -> Cr3Usart {
27048 Cr3Usart(0)
27049 }
27050 }
27051 #[doc = "Data register"]
27052 #[repr(transparent)]
27053 #[derive(Copy, Clone, Eq, PartialEq)]
27054 pub struct Dr(pub u32);
27055 impl Dr {
27056 #[doc = "Data value"]
27057 pub const fn dr(&self) -> u16 {
27058 let val = (self.0 >> 0usize) & 0x01ff;
27059 val as u16
27060 }
27061 #[doc = "Data value"]
27062 pub fn set_dr(&mut self, val: u16) {
27063 self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize);
27064 }
27065 }
27066 impl Default for Dr {
27067 fn default() -> Dr {
27068 Dr(0)
27069 }
27070 }
27071 #[doc = "Baud rate register"]
27072 #[repr(transparent)]
27073 #[derive(Copy, Clone, Eq, PartialEq)]
27074 pub struct Brr(pub u32);
27075 impl Brr {
27076 #[doc = "fraction of USARTDIV"]
27077 pub const fn div_fraction(&self) -> u8 {
27078 let val = (self.0 >> 0usize) & 0x0f;
27079 val as u8
27080 }
27081 #[doc = "fraction of USARTDIV"]
27082 pub fn set_div_fraction(&mut self, val: u8) {
27083 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
27084 }
27085 #[doc = "mantissa of USARTDIV"]
27086 pub const fn div_mantissa(&self) -> u16 {
27087 let val = (self.0 >> 4usize) & 0x0fff;
27088 val as u16
27089 }
27090 #[doc = "mantissa of USARTDIV"]
27091 pub fn set_div_mantissa(&mut self, val: u16) {
27092 self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize);
27093 }
27094 }
27095 impl Default for Brr {
27096 fn default() -> Brr {
27097 Brr(0)
27098 }
27099 }
27100 #[doc = "Control register 2"]
27101 #[repr(transparent)]
27102 #[derive(Copy, Clone, Eq, PartialEq)]
27103 pub struct Cr2(pub u32);
27104 impl Cr2 {
27105 #[doc = "Address of the USART node"]
27106 pub const fn add(&self) -> u8 {
27107 let val = (self.0 >> 0usize) & 0x0f;
27108 val as u8
27109 }
27110 #[doc = "Address of the USART node"]
27111 pub fn set_add(&mut self, val: u8) {
27112 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
27113 }
27114 #[doc = "lin break detection length"]
27115 pub const fn lbdl(&self) -> super::vals::Lbdl {
27116 let val = (self.0 >> 5usize) & 0x01;
27117 super::vals::Lbdl(val as u8)
27118 }
27119 #[doc = "lin break detection length"]
27120 pub fn set_lbdl(&mut self, val: super::vals::Lbdl) {
27121 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
27122 }
27123 #[doc = "LIN break detection interrupt enable"]
27124 pub const fn lbdie(&self) -> bool {
27125 let val = (self.0 >> 6usize) & 0x01;
27126 val != 0
27127 }
27128 #[doc = "LIN break detection interrupt enable"]
27129 pub fn set_lbdie(&mut self, val: bool) {
27130 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
27131 }
27132 #[doc = "STOP bits"]
27133 pub const fn stop(&self) -> super::vals::Stop {
27134 let val = (self.0 >> 12usize) & 0x03;
27135 super::vals::Stop(val as u8)
27136 }
27137 #[doc = "STOP bits"]
27138 pub fn set_stop(&mut self, val: super::vals::Stop) {
27139 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
27140 }
27141 #[doc = "LIN mode enable"]
27142 pub const fn linen(&self) -> bool {
27143 let val = (self.0 >> 14usize) & 0x01;
27144 val != 0
27145 }
27146 #[doc = "LIN mode enable"]
27147 pub fn set_linen(&mut self, val: bool) {
27148 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
27149 }
27150 }
27151 impl Default for Cr2 {
27152 fn default() -> Cr2 {
27153 Cr2(0)
27154 }
27155 }
27156 #[doc = "Control register 1"]
27157 #[repr(transparent)]
27158 #[derive(Copy, Clone, Eq, PartialEq)]
27159 pub struct Cr1(pub u32);
27160 impl Cr1 {
27161 #[doc = "Send break"]
27162 pub const fn sbk(&self) -> super::vals::Sbk {
27163 let val = (self.0 >> 0usize) & 0x01;
27164 super::vals::Sbk(val as u8)
27165 }
27166 #[doc = "Send break"]
27167 pub fn set_sbk(&mut self, val: super::vals::Sbk) {
27168 self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize);
27169 }
27170 #[doc = "Receiver wakeup"]
27171 pub const fn rwu(&self) -> super::vals::Rwu {
27172 let val = (self.0 >> 1usize) & 0x01;
27173 super::vals::Rwu(val as u8)
27174 }
27175 #[doc = "Receiver wakeup"]
27176 pub fn set_rwu(&mut self, val: super::vals::Rwu) {
27177 self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize);
27178 }
27179 #[doc = "Receiver enable"]
27180 pub const fn re(&self) -> bool {
27181 let val = (self.0 >> 2usize) & 0x01;
27182 val != 0
27183 }
27184 #[doc = "Receiver enable"]
27185 pub fn set_re(&mut self, val: bool) {
27186 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
27187 }
27188 #[doc = "Transmitter enable"]
27189 pub const fn te(&self) -> bool {
27190 let val = (self.0 >> 3usize) & 0x01;
27191 val != 0
27192 }
27193 #[doc = "Transmitter enable"]
27194 pub fn set_te(&mut self, val: bool) {
27195 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
27196 }
27197 #[doc = "IDLE interrupt enable"]
27198 pub const fn idleie(&self) -> bool {
27199 let val = (self.0 >> 4usize) & 0x01;
27200 val != 0
27201 }
27202 #[doc = "IDLE interrupt enable"]
27203 pub fn set_idleie(&mut self, val: bool) {
27204 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
27205 }
27206 #[doc = "RXNE interrupt enable"]
27207 pub const fn rxneie(&self) -> bool {
27208 let val = (self.0 >> 5usize) & 0x01;
27209 val != 0
27210 }
27211 #[doc = "RXNE interrupt enable"]
27212 pub fn set_rxneie(&mut self, val: bool) {
27213 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
27214 }
27215 #[doc = "Transmission complete interrupt enable"]
27216 pub const fn tcie(&self) -> bool {
27217 let val = (self.0 >> 6usize) & 0x01;
27218 val != 0
27219 }
27220 #[doc = "Transmission complete interrupt enable"]
27221 pub fn set_tcie(&mut self, val: bool) {
27222 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
27223 }
27224 #[doc = "TXE interrupt enable"]
27225 pub const fn txeie(&self) -> bool {
27226 let val = (self.0 >> 7usize) & 0x01;
27227 val != 0
27228 }
27229 #[doc = "TXE interrupt enable"]
27230 pub fn set_txeie(&mut self, val: bool) {
27231 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
27232 }
27233 #[doc = "PE interrupt enable"]
27234 pub const fn peie(&self) -> bool {
27235 let val = (self.0 >> 8usize) & 0x01;
27236 val != 0
27237 }
27238 #[doc = "PE interrupt enable"]
27239 pub fn set_peie(&mut self, val: bool) {
27240 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
27241 }
27242 #[doc = "Parity selection"]
27243 pub const fn ps(&self) -> super::vals::Ps {
27244 let val = (self.0 >> 9usize) & 0x01;
27245 super::vals::Ps(val as u8)
27246 }
27247 #[doc = "Parity selection"]
27248 pub fn set_ps(&mut self, val: super::vals::Ps) {
27249 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
27250 }
27251 #[doc = "Parity control enable"]
27252 pub const fn pce(&self) -> bool {
27253 let val = (self.0 >> 10usize) & 0x01;
27254 val != 0
27255 }
27256 #[doc = "Parity control enable"]
27257 pub fn set_pce(&mut self, val: bool) {
27258 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
27259 }
27260 #[doc = "Wakeup method"]
27261 pub const fn wake(&self) -> super::vals::Wake {
27262 let val = (self.0 >> 11usize) & 0x01;
27263 super::vals::Wake(val as u8)
27264 }
27265 #[doc = "Wakeup method"]
27266 pub fn set_wake(&mut self, val: super::vals::Wake) {
27267 self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize);
27268 }
27269 #[doc = "Word length"]
27270 pub const fn m(&self) -> super::vals::M {
27271 let val = (self.0 >> 12usize) & 0x01;
27272 super::vals::M(val as u8)
27273 }
27274 #[doc = "Word length"]
27275 pub fn set_m(&mut self, val: super::vals::M) {
27276 self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize);
27277 }
27278 #[doc = "USART enable"]
27279 pub const fn ue(&self) -> bool {
27280 let val = (self.0 >> 13usize) & 0x01;
27281 val != 0
27282 }
27283 #[doc = "USART enable"]
27284 pub fn set_ue(&mut self, val: bool) {
27285 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
27286 }
27287 }
27288 impl Default for Cr1 {
27289 fn default() -> Cr1 {
27290 Cr1(0)
27291 }
27292 }
27293 #[doc = "Control register 2"]
27294 #[repr(transparent)]
27295 #[derive(Copy, Clone, Eq, PartialEq)]
27296 pub struct Cr2Usart(pub u32);
27297 impl Cr2Usart {
27298 #[doc = "Address of the USART node"]
27299 pub const fn add(&self) -> u8 {
27300 let val = (self.0 >> 0usize) & 0x0f;
27301 val as u8
27302 }
27303 #[doc = "Address of the USART node"]
27304 pub fn set_add(&mut self, val: u8) {
27305 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
27306 }
27307 #[doc = "lin break detection length"]
27308 pub const fn lbdl(&self) -> super::vals::Lbdl {
27309 let val = (self.0 >> 5usize) & 0x01;
27310 super::vals::Lbdl(val as u8)
27311 }
27312 #[doc = "lin break detection length"]
27313 pub fn set_lbdl(&mut self, val: super::vals::Lbdl) {
27314 self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize);
27315 }
27316 #[doc = "LIN break detection interrupt enable"]
27317 pub const fn lbdie(&self) -> bool {
27318 let val = (self.0 >> 6usize) & 0x01;
27319 val != 0
27320 }
27321 #[doc = "LIN break detection interrupt enable"]
27322 pub fn set_lbdie(&mut self, val: bool) {
27323 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
27324 }
27325 #[doc = "Last bit clock pulse"]
27326 pub const fn lbcl(&self) -> bool {
27327 let val = (self.0 >> 8usize) & 0x01;
27328 val != 0
27329 }
27330 #[doc = "Last bit clock pulse"]
27331 pub fn set_lbcl(&mut self, val: bool) {
27332 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
27333 }
27334 #[doc = "Clock phase"]
27335 pub const fn cpha(&self) -> super::vals::Cpha {
27336 let val = (self.0 >> 9usize) & 0x01;
27337 super::vals::Cpha(val as u8)
27338 }
27339 #[doc = "Clock phase"]
27340 pub fn set_cpha(&mut self, val: super::vals::Cpha) {
27341 self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize);
27342 }
27343 #[doc = "Clock polarity"]
27344 pub const fn cpol(&self) -> super::vals::Cpol {
27345 let val = (self.0 >> 10usize) & 0x01;
27346 super::vals::Cpol(val as u8)
27347 }
27348 #[doc = "Clock polarity"]
27349 pub fn set_cpol(&mut self, val: super::vals::Cpol) {
27350 self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize);
27351 }
27352 #[doc = "Clock enable"]
27353 pub const fn clken(&self) -> bool {
27354 let val = (self.0 >> 11usize) & 0x01;
27355 val != 0
27356 }
27357 #[doc = "Clock enable"]
27358 pub fn set_clken(&mut self, val: bool) {
27359 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
27360 }
27361 #[doc = "STOP bits"]
27362 pub const fn stop(&self) -> super::vals::Stop {
27363 let val = (self.0 >> 12usize) & 0x03;
27364 super::vals::Stop(val as u8)
27365 }
27366 #[doc = "STOP bits"]
27367 pub fn set_stop(&mut self, val: super::vals::Stop) {
27368 self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize);
27369 }
27370 #[doc = "LIN mode enable"]
27371 pub const fn linen(&self) -> bool {
27372 let val = (self.0 >> 14usize) & 0x01;
27373 val != 0
27374 }
27375 #[doc = "LIN mode enable"]
27376 pub fn set_linen(&mut self, val: bool) {
27377 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
27378 }
27379 }
27380 impl Default for Cr2Usart {
27381 fn default() -> Cr2Usart {
27382 Cr2Usart(0)
27383 }
27384 }
27385 #[doc = "Status register"]
27386 #[repr(transparent)]
27387 #[derive(Copy, Clone, Eq, PartialEq)]
27388 pub struct SrUsart(pub u32);
27389 impl SrUsart {
27390 #[doc = "Parity error"]
27391 pub const fn pe(&self) -> bool {
27392 let val = (self.0 >> 0usize) & 0x01;
27393 val != 0
27394 }
27395 #[doc = "Parity error"]
27396 pub fn set_pe(&mut self, val: bool) {
27397 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
27398 }
27399 #[doc = "Framing error"]
27400 pub const fn fe(&self) -> bool {
27401 let val = (self.0 >> 1usize) & 0x01;
27402 val != 0
27403 }
27404 #[doc = "Framing error"]
27405 pub fn set_fe(&mut self, val: bool) {
27406 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
27407 }
27408 #[doc = "Noise error flag"]
27409 pub const fn ne(&self) -> bool {
27410 let val = (self.0 >> 2usize) & 0x01;
27411 val != 0
27412 }
27413 #[doc = "Noise error flag"]
27414 pub fn set_ne(&mut self, val: bool) {
27415 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
27416 }
27417 #[doc = "Overrun error"]
27418 pub const fn ore(&self) -> bool {
27419 let val = (self.0 >> 3usize) & 0x01;
27420 val != 0
27421 }
27422 #[doc = "Overrun error"]
27423 pub fn set_ore(&mut self, val: bool) {
27424 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
27425 }
27426 #[doc = "IDLE line detected"]
27427 pub const fn idle(&self) -> bool {
27428 let val = (self.0 >> 4usize) & 0x01;
27429 val != 0
27430 }
27431 #[doc = "IDLE line detected"]
27432 pub fn set_idle(&mut self, val: bool) {
27433 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
27434 }
27435 #[doc = "Read data register not empty"]
27436 pub const fn rxne(&self) -> bool {
27437 let val = (self.0 >> 5usize) & 0x01;
27438 val != 0
27439 }
27440 #[doc = "Read data register not empty"]
27441 pub fn set_rxne(&mut self, val: bool) {
27442 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
27443 }
27444 #[doc = "Transmission complete"]
27445 pub const fn tc(&self) -> bool {
27446 let val = (self.0 >> 6usize) & 0x01;
27447 val != 0
27448 }
27449 #[doc = "Transmission complete"]
27450 pub fn set_tc(&mut self, val: bool) {
27451 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
27452 }
27453 #[doc = "Transmit data register empty"]
27454 pub const fn txe(&self) -> bool {
27455 let val = (self.0 >> 7usize) & 0x01;
27456 val != 0
27457 }
27458 #[doc = "Transmit data register empty"]
27459 pub fn set_txe(&mut self, val: bool) {
27460 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
27461 }
27462 #[doc = "LIN break detection flag"]
27463 pub const fn lbd(&self) -> bool {
27464 let val = (self.0 >> 8usize) & 0x01;
27465 val != 0
27466 }
27467 #[doc = "LIN break detection flag"]
27468 pub fn set_lbd(&mut self, val: bool) {
27469 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
27470 }
27471 #[doc = "CTS flag"]
27472 pub const fn cts(&self) -> bool {
27473 let val = (self.0 >> 9usize) & 0x01;
27474 val != 0
27475 }
27476 #[doc = "CTS flag"]
27477 pub fn set_cts(&mut self, val: bool) {
27478 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
27479 }
27480 }
27481 impl Default for SrUsart {
27482 fn default() -> SrUsart {
27483 SrUsart(0)
27484 }
27485 }
27486 #[doc = "Status register"]
27487 #[repr(transparent)]
27488 #[derive(Copy, Clone, Eq, PartialEq)]
27489 pub struct Sr(pub u32);
27490 impl Sr {
27491 #[doc = "Parity error"]
27492 pub const fn pe(&self) -> bool {
27493 let val = (self.0 >> 0usize) & 0x01;
27494 val != 0
27495 }
27496 #[doc = "Parity error"]
27497 pub fn set_pe(&mut self, val: bool) {
27498 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
27499 }
27500 #[doc = "Framing error"]
27501 pub const fn fe(&self) -> bool {
27502 let val = (self.0 >> 1usize) & 0x01;
27503 val != 0
27504 }
27505 #[doc = "Framing error"]
27506 pub fn set_fe(&mut self, val: bool) {
27507 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
27508 }
27509 #[doc = "Noise error flag"]
27510 pub const fn ne(&self) -> bool {
27511 let val = (self.0 >> 2usize) & 0x01;
27512 val != 0
27513 }
27514 #[doc = "Noise error flag"]
27515 pub fn set_ne(&mut self, val: bool) {
27516 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
27517 }
27518 #[doc = "Overrun error"]
27519 pub const fn ore(&self) -> bool {
27520 let val = (self.0 >> 3usize) & 0x01;
27521 val != 0
27522 }
27523 #[doc = "Overrun error"]
27524 pub fn set_ore(&mut self, val: bool) {
27525 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
27526 }
27527 #[doc = "IDLE line detected"]
27528 pub const fn idle(&self) -> bool {
27529 let val = (self.0 >> 4usize) & 0x01;
27530 val != 0
27531 }
27532 #[doc = "IDLE line detected"]
27533 pub fn set_idle(&mut self, val: bool) {
27534 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
27535 }
27536 #[doc = "Read data register not empty"]
27537 pub const fn rxne(&self) -> bool {
27538 let val = (self.0 >> 5usize) & 0x01;
27539 val != 0
27540 }
27541 #[doc = "Read data register not empty"]
27542 pub fn set_rxne(&mut self, val: bool) {
27543 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
27544 }
27545 #[doc = "Transmission complete"]
27546 pub const fn tc(&self) -> bool {
27547 let val = (self.0 >> 6usize) & 0x01;
27548 val != 0
27549 }
27550 #[doc = "Transmission complete"]
27551 pub fn set_tc(&mut self, val: bool) {
27552 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
27553 }
27554 #[doc = "Transmit data register empty"]
27555 pub const fn txe(&self) -> bool {
27556 let val = (self.0 >> 7usize) & 0x01;
27557 val != 0
27558 }
27559 #[doc = "Transmit data register empty"]
27560 pub fn set_txe(&mut self, val: bool) {
27561 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
27562 }
27563 #[doc = "LIN break detection flag"]
27564 pub const fn lbd(&self) -> bool {
27565 let val = (self.0 >> 8usize) & 0x01;
27566 val != 0
27567 }
27568 #[doc = "LIN break detection flag"]
27569 pub fn set_lbd(&mut self, val: bool) {
27570 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
27571 }
27572 }
27573 impl Default for Sr {
27574 fn default() -> Sr {
27575 Sr(0)
27576 }
27577 }
27578 #[doc = "Control register 3"]
27579 #[repr(transparent)]
27580 #[derive(Copy, Clone, Eq, PartialEq)]
27581 pub struct Cr3(pub u32);
27582 impl Cr3 {
27583 #[doc = "Error interrupt enable"]
27584 pub const fn eie(&self) -> bool {
27585 let val = (self.0 >> 0usize) & 0x01;
27586 val != 0
27587 }
27588 #[doc = "Error interrupt enable"]
27589 pub fn set_eie(&mut self, val: bool) {
27590 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
27591 }
27592 #[doc = "IrDA mode enable"]
27593 pub const fn iren(&self) -> bool {
27594 let val = (self.0 >> 1usize) & 0x01;
27595 val != 0
27596 }
27597 #[doc = "IrDA mode enable"]
27598 pub fn set_iren(&mut self, val: bool) {
27599 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
27600 }
27601 #[doc = "IrDA low-power"]
27602 pub const fn irlp(&self) -> super::vals::Irlp {
27603 let val = (self.0 >> 2usize) & 0x01;
27604 super::vals::Irlp(val as u8)
27605 }
27606 #[doc = "IrDA low-power"]
27607 pub fn set_irlp(&mut self, val: super::vals::Irlp) {
27608 self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize);
27609 }
27610 #[doc = "Half-duplex selection"]
27611 pub const fn hdsel(&self) -> super::vals::Hdsel {
27612 let val = (self.0 >> 3usize) & 0x01;
27613 super::vals::Hdsel(val as u8)
27614 }
27615 #[doc = "Half-duplex selection"]
27616 pub fn set_hdsel(&mut self, val: super::vals::Hdsel) {
27617 self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize);
27618 }
27619 #[doc = "DMA enable receiver"]
27620 pub const fn dmar(&self) -> bool {
27621 let val = (self.0 >> 6usize) & 0x01;
27622 val != 0
27623 }
27624 #[doc = "DMA enable receiver"]
27625 pub fn set_dmar(&mut self, val: bool) {
27626 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
27627 }
27628 #[doc = "DMA enable transmitter"]
27629 pub const fn dmat(&self) -> bool {
27630 let val = (self.0 >> 7usize) & 0x01;
27631 val != 0
27632 }
27633 #[doc = "DMA enable transmitter"]
27634 pub fn set_dmat(&mut self, val: bool) {
27635 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
27636 }
27637 }
27638 impl Default for Cr3 {
27639 fn default() -> Cr3 {
27640 Cr3(0)
27641 }
27642 }
27643 }
27644}
27645pub mod sdmmc_v2 {
27646 use crate::generic::*;
27647 #[doc = "SDMMC"]
27648 #[derive(Copy, Clone)]
27649 pub struct Sdmmc(pub *mut u8);
27650 unsafe impl Send for Sdmmc {}
27651 unsafe impl Sync for Sdmmc {}
27652 impl Sdmmc {
27653 #[doc = "SDMMC power control register"]
27654 pub fn power(self) -> Reg<regs::Power, RW> {
27655 unsafe { Reg::from_ptr(self.0.add(0usize)) }
27656 }
27657 #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."]
27658 pub fn clkcr(self) -> Reg<regs::Clkcr, RW> {
27659 unsafe { Reg::from_ptr(self.0.add(4usize)) }
27660 }
27661 #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."]
27662 pub fn argr(self) -> Reg<regs::Argr, RW> {
27663 unsafe { Reg::from_ptr(self.0.add(8usize)) }
27664 }
27665 #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."]
27666 pub fn cmdr(self) -> Reg<regs::Cmdr, RW> {
27667 unsafe { Reg::from_ptr(self.0.add(12usize)) }
27668 }
27669 #[doc = "SDMMC command response register"]
27670 pub fn respcmdr(self) -> Reg<regs::Respcmdr, R> {
27671 unsafe { Reg::from_ptr(self.0.add(16usize)) }
27672 }
27673 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
27674 pub fn respr(self, n: usize) -> Reg<regs::Resp1r, R> {
27675 assert!(n < 4usize);
27676 unsafe { Reg::from_ptr(self.0.add(20usize + n * 4usize)) }
27677 }
27678 #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."]
27679 pub fn dtimer(self) -> Reg<regs::Dtimer, RW> {
27680 unsafe { Reg::from_ptr(self.0.add(36usize)) }
27681 }
27682 #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."]
27683 pub fn dlenr(self) -> Reg<regs::Dlenr, RW> {
27684 unsafe { Reg::from_ptr(self.0.add(40usize)) }
27685 }
27686 #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."]
27687 pub fn dctrl(self) -> Reg<regs::Dctrl, RW> {
27688 unsafe { Reg::from_ptr(self.0.add(44usize)) }
27689 }
27690 #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."]
27691 pub fn dcntr(self) -> Reg<regs::Dcntr, R> {
27692 unsafe { Reg::from_ptr(self.0.add(48usize)) }
27693 }
27694 #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"]
27695 pub fn star(self) -> Reg<regs::Star, R> {
27696 unsafe { Reg::from_ptr(self.0.add(52usize)) }
27697 }
27698 #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."]
27699 pub fn icr(self) -> Reg<regs::Icr, RW> {
27700 unsafe { Reg::from_ptr(self.0.add(56usize)) }
27701 }
27702 #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."]
27703 pub fn maskr(self) -> Reg<regs::Maskr, RW> {
27704 unsafe { Reg::from_ptr(self.0.add(60usize)) }
27705 }
27706 #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."]
27707 pub fn acktimer(self) -> Reg<regs::Acktimer, RW> {
27708 unsafe { Reg::from_ptr(self.0.add(64usize)) }
27709 }
27710 #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."]
27711 pub fn idmactrlr(self) -> Reg<regs::Idmactrlr, RW> {
27712 unsafe { Reg::from_ptr(self.0.add(80usize)) }
27713 }
27714 #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."]
27715 pub fn idmabsizer(self) -> Reg<regs::Idmabsizer, RW> {
27716 unsafe { Reg::from_ptr(self.0.add(84usize)) }
27717 }
27718 #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."]
27719 pub fn idmabase0r(self) -> Reg<regs::Idmabase0r, RW> {
27720 unsafe { Reg::from_ptr(self.0.add(88usize)) }
27721 }
27722 #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."]
27723 pub fn idmabase1r(self) -> Reg<regs::Idmabase1r, RW> {
27724 unsafe { Reg::from_ptr(self.0.add(92usize)) }
27725 }
27726 #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."]
27727 pub fn fifor(self) -> Reg<regs::Fifor, RW> {
27728 unsafe { Reg::from_ptr(self.0.add(128usize)) }
27729 }
27730 #[doc = "SDMMC IP version register"]
27731 pub fn ver(self) -> Reg<regs::Ver, R> {
27732 unsafe { Reg::from_ptr(self.0.add(1012usize)) }
27733 }
27734 #[doc = "SDMMC IP identification register"]
27735 pub fn id(self) -> Reg<regs::Id, R> {
27736 unsafe { Reg::from_ptr(self.0.add(1016usize)) }
27737 }
27738 }
27739 pub mod regs {
27740 use crate::generic::*;
27741 #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."]
27742 #[repr(transparent)]
27743 #[derive(Copy, Clone, Eq, PartialEq)]
27744 pub struct Idmabsizer(pub u32);
27745 impl Idmabsizer {
27746 #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
27747 pub const fn idmabndt(&self) -> u8 {
27748 let val = (self.0 >> 5usize) & 0xff;
27749 val as u8
27750 }
27751 #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
27752 pub fn set_idmabndt(&mut self, val: u8) {
27753 self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize);
13678 } 27754 }
13679 } 27755 }
13680 impl Default for Idmabsizer { 27756 impl Default for Idmabsizer {
@@ -13682,6 +27758,73 @@ pub mod sdmmc_v2 {
13682 Idmabsizer(0) 27758 Idmabsizer(0)
13683 } 27759 }
13684 } 27760 }
27761 #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."]
27762 #[repr(transparent)]
27763 #[derive(Copy, Clone, Eq, PartialEq)]
27764 pub struct Dcntr(pub u32);
27765 impl Dcntr {
27766 #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."]
27767 pub const fn datacount(&self) -> u32 {
27768 let val = (self.0 >> 0usize) & 0x01ff_ffff;
27769 val as u32
27770 }
27771 #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."]
27772 pub fn set_datacount(&mut self, val: u32) {
27773 self.0 =
27774 (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
27775 }
27776 }
27777 impl Default for Dcntr {
27778 fn default() -> Dcntr {
27779 Dcntr(0)
27780 }
27781 }
27782 #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."]
27783 #[repr(transparent)]
27784 #[derive(Copy, Clone, Eq, PartialEq)]
27785 pub struct Idmabase0r(pub u32);
27786 impl Idmabase0r {
27787 #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0]
27788are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."]
27789 pub const fn idmabase0(&self) -> u32 {
27790 let val = (self.0 >> 0usize) & 0xffff_ffff;
27791 val as u32
27792 }
27793 #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0]
27794are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."]
27795 pub fn set_idmabase0(&mut self, val: u32) {
27796 self.0 =
27797 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
27798 }
27799 }
27800 impl Default for Idmabase0r {
27801 fn default() -> Idmabase0r {
27802 Idmabase0r(0)
27803 }
27804 }
27805 #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."]
27806 #[repr(transparent)]
27807 #[derive(Copy, Clone, Eq, PartialEq)]
27808 pub struct Idmabase1r(pub u32);
27809 impl Idmabase1r {
27810 #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0]
27811are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."]
27812 pub const fn idmabase1(&self) -> u32 {
27813 let val = (self.0 >> 0usize) & 0xffff_ffff;
27814 val as u32
27815 }
27816 #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0]
27817are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."]
27818 pub fn set_idmabase1(&mut self, val: u32) {
27819 self.0 =
27820 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
27821 }
27822 }
27823 impl Default for Idmabase1r {
27824 fn default() -> Idmabase1r {
27825 Idmabase1r(0)
27826 }
27827 }
13685 #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] 27828 #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."]
13686 #[repr(transparent)] 27829 #[repr(transparent)]
13687 #[derive(Copy, Clone, Eq, PartialEq)] 27830 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -13765,6 +27908,47 @@ pub mod sdmmc_v2 {
13765 Clkcr(0) 27908 Clkcr(0)
13766 } 27909 }
13767 } 27910 }
27911 #[doc = "SDMMC command response register"]
27912 #[repr(transparent)]
27913 #[derive(Copy, Clone, Eq, PartialEq)]
27914 pub struct Respcmdr(pub u32);
27915 impl Respcmdr {
27916 #[doc = "Response command index"]
27917 pub const fn respcmd(&self) -> u8 {
27918 let val = (self.0 >> 0usize) & 0x3f;
27919 val as u8
27920 }
27921 #[doc = "Response command index"]
27922 pub fn set_respcmd(&mut self, val: u8) {
27923 self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
27924 }
27925 }
27926 impl Default for Respcmdr {
27927 fn default() -> Respcmdr {
27928 Respcmdr(0)
27929 }
27930 }
27931 #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."]
27932 #[repr(transparent)]
27933 #[derive(Copy, Clone, Eq, PartialEq)]
27934 pub struct Dlenr(pub u32);
27935 impl Dlenr {
27936 #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."]
27937 pub const fn datalength(&self) -> u32 {
27938 let val = (self.0 >> 0usize) & 0x01ff_ffff;
27939 val as u32
27940 }
27941 #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."]
27942 pub fn set_datalength(&mut self, val: u32) {
27943 self.0 =
27944 (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
27945 }
27946 }
27947 impl Default for Dlenr {
27948 fn default() -> Dlenr {
27949 Dlenr(0)
27950 }
27951 }
13768 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] 27952 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
13769 #[repr(transparent)] 27953 #[repr(transparent)]
13770 #[derive(Copy, Clone, Eq, PartialEq)] 27954 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -13786,6 +27970,501 @@ pub mod sdmmc_v2 {
13786 Resp2r(0) 27970 Resp2r(0)
13787 } 27971 }
13788 } 27972 }
27973 #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."]
27974 #[repr(transparent)]
27975 #[derive(Copy, Clone, Eq, PartialEq)]
27976 pub struct Cmdr(pub u32);
27977 impl Cmdr {
27978 #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."]
27979 pub const fn cmdindex(&self) -> u8 {
27980 let val = (self.0 >> 0usize) & 0x3f;
27981 val as u8
27982 }
27983 #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."]
27984 pub fn set_cmdindex(&mut self, val: u8) {
27985 self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize);
27986 }
27987 #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."]
27988 pub const fn cmdtrans(&self) -> bool {
27989 let val = (self.0 >> 6usize) & 0x01;
27990 val != 0
27991 }
27992 #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."]
27993 pub fn set_cmdtrans(&mut self, val: bool) {
27994 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
27995 }
27996 #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."]
27997 pub const fn cmdstop(&self) -> bool {
27998 let val = (self.0 >> 7usize) & 0x01;
27999 val != 0
28000 }
28001 #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."]
28002 pub fn set_cmdstop(&mut self, val: bool) {
28003 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
28004 }
28005 #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."]
28006 pub const fn waitresp(&self) -> u8 {
28007 let val = (self.0 >> 8usize) & 0x03;
28008 val as u8
28009 }
28010 #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."]
28011 pub fn set_waitresp(&mut self, val: u8) {
28012 self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
28013 }
28014 #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."]
28015 pub const fn waitint(&self) -> bool {
28016 let val = (self.0 >> 10usize) & 0x01;
28017 val != 0
28018 }
28019 #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."]
28020 pub fn set_waitint(&mut self, val: bool) {
28021 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
28022 }
28023 #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."]
28024 pub const fn waitpend(&self) -> bool {
28025 let val = (self.0 >> 11usize) & 0x01;
28026 val != 0
28027 }
28028 #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."]
28029 pub fn set_waitpend(&mut self, val: bool) {
28030 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
28031 }
28032 #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."]
28033 pub const fn cpsmen(&self) -> bool {
28034 let val = (self.0 >> 12usize) & 0x01;
28035 val != 0
28036 }
28037 #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."]
28038 pub fn set_cpsmen(&mut self, val: bool) {
28039 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
28040 }
28041 #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."]
28042 pub const fn dthold(&self) -> bool {
28043 let val = (self.0 >> 13usize) & 0x01;
28044 val != 0
28045 }
28046 #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."]
28047 pub fn set_dthold(&mut self, val: bool) {
28048 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
28049 }
28050 #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"]
28051 pub const fn bootmode(&self) -> bool {
28052 let val = (self.0 >> 14usize) & 0x01;
28053 val != 0
28054 }
28055 #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"]
28056 pub fn set_bootmode(&mut self, val: bool) {
28057 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
28058 }
28059 #[doc = "Enable boot mode procedure."]
28060 pub const fn booten(&self) -> bool {
28061 let val = (self.0 >> 15usize) & 0x01;
28062 val != 0
28063 }
28064 #[doc = "Enable boot mode procedure."]
28065 pub fn set_booten(&mut self, val: bool) {
28066 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
28067 }
28068 #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."]
28069 pub const fn cmdsuspend(&self) -> bool {
28070 let val = (self.0 >> 16usize) & 0x01;
28071 val != 0
28072 }
28073 #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."]
28074 pub fn set_cmdsuspend(&mut self, val: bool) {
28075 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
28076 }
28077 }
28078 impl Default for Cmdr {
28079 fn default() -> Cmdr {
28080 Cmdr(0)
28081 }
28082 }
28083 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
28084 #[repr(transparent)]
28085 #[derive(Copy, Clone, Eq, PartialEq)]
28086 pub struct Resp3r(pub u32);
28087 impl Resp3r {
28088 #[doc = "see Table404."]
28089 pub const fn cardstatus3(&self) -> u32 {
28090 let val = (self.0 >> 0usize) & 0xffff_ffff;
28091 val as u32
28092 }
28093 #[doc = "see Table404."]
28094 pub fn set_cardstatus3(&mut self, val: u32) {
28095 self.0 =
28096 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
28097 }
28098 }
28099 impl Default for Resp3r {
28100 fn default() -> Resp3r {
28101 Resp3r(0)
28102 }
28103 }
28104 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
28105 #[repr(transparent)]
28106 #[derive(Copy, Clone, Eq, PartialEq)]
28107 pub struct Resp4r(pub u32);
28108 impl Resp4r {
28109 #[doc = "see Table404."]
28110 pub const fn cardstatus4(&self) -> u32 {
28111 let val = (self.0 >> 0usize) & 0xffff_ffff;
28112 val as u32
28113 }
28114 #[doc = "see Table404."]
28115 pub fn set_cardstatus4(&mut self, val: u32) {
28116 self.0 =
28117 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
28118 }
28119 }
28120 impl Default for Resp4r {
28121 fn default() -> Resp4r {
28122 Resp4r(0)
28123 }
28124 }
28125 #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."]
28126 #[repr(transparent)]
28127 #[derive(Copy, Clone, Eq, PartialEq)]
28128 pub struct Icr(pub u32);
28129 impl Icr {
28130 #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."]
28131 pub const fn ccrcfailc(&self) -> bool {
28132 let val = (self.0 >> 0usize) & 0x01;
28133 val != 0
28134 }
28135 #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."]
28136 pub fn set_ccrcfailc(&mut self, val: bool) {
28137 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
28138 }
28139 #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."]
28140 pub const fn dcrcfailc(&self) -> bool {
28141 let val = (self.0 >> 1usize) & 0x01;
28142 val != 0
28143 }
28144 #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."]
28145 pub fn set_dcrcfailc(&mut self, val: bool) {
28146 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
28147 }
28148 #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."]
28149 pub const fn ctimeoutc(&self) -> bool {
28150 let val = (self.0 >> 2usize) & 0x01;
28151 val != 0
28152 }
28153 #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."]
28154 pub fn set_ctimeoutc(&mut self, val: bool) {
28155 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
28156 }
28157 #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."]
28158 pub const fn dtimeoutc(&self) -> bool {
28159 let val = (self.0 >> 3usize) & 0x01;
28160 val != 0
28161 }
28162 #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."]
28163 pub fn set_dtimeoutc(&mut self, val: bool) {
28164 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
28165 }
28166 #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."]
28167 pub const fn txunderrc(&self) -> bool {
28168 let val = (self.0 >> 4usize) & 0x01;
28169 val != 0
28170 }
28171 #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."]
28172 pub fn set_txunderrc(&mut self, val: bool) {
28173 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
28174 }
28175 #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."]
28176 pub const fn rxoverrc(&self) -> bool {
28177 let val = (self.0 >> 5usize) & 0x01;
28178 val != 0
28179 }
28180 #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."]
28181 pub fn set_rxoverrc(&mut self, val: bool) {
28182 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
28183 }
28184 #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."]
28185 pub const fn cmdrendc(&self) -> bool {
28186 let val = (self.0 >> 6usize) & 0x01;
28187 val != 0
28188 }
28189 #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."]
28190 pub fn set_cmdrendc(&mut self, val: bool) {
28191 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
28192 }
28193 #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."]
28194 pub const fn cmdsentc(&self) -> bool {
28195 let val = (self.0 >> 7usize) & 0x01;
28196 val != 0
28197 }
28198 #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."]
28199 pub fn set_cmdsentc(&mut self, val: bool) {
28200 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
28201 }
28202 #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."]
28203 pub const fn dataendc(&self) -> bool {
28204 let val = (self.0 >> 8usize) & 0x01;
28205 val != 0
28206 }
28207 #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."]
28208 pub fn set_dataendc(&mut self, val: bool) {
28209 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
28210 }
28211 #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."]
28212 pub const fn dholdc(&self) -> bool {
28213 let val = (self.0 >> 9usize) & 0x01;
28214 val != 0
28215 }
28216 #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."]
28217 pub fn set_dholdc(&mut self, val: bool) {
28218 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
28219 }
28220 #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."]
28221 pub const fn dbckendc(&self) -> bool {
28222 let val = (self.0 >> 10usize) & 0x01;
28223 val != 0
28224 }
28225 #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."]
28226 pub fn set_dbckendc(&mut self, val: bool) {
28227 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
28228 }
28229 #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."]
28230 pub const fn dabortc(&self) -> bool {
28231 let val = (self.0 >> 11usize) & 0x01;
28232 val != 0
28233 }
28234 #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."]
28235 pub fn set_dabortc(&mut self, val: bool) {
28236 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
28237 }
28238 #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."]
28239 pub const fn busyd0endc(&self) -> bool {
28240 let val = (self.0 >> 21usize) & 0x01;
28241 val != 0
28242 }
28243 #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."]
28244 pub fn set_busyd0endc(&mut self, val: bool) {
28245 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
28246 }
28247 #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."]
28248 pub const fn sdioitc(&self) -> bool {
28249 let val = (self.0 >> 22usize) & 0x01;
28250 val != 0
28251 }
28252 #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."]
28253 pub fn set_sdioitc(&mut self, val: bool) {
28254 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
28255 }
28256 #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."]
28257 pub const fn ackfailc(&self) -> bool {
28258 let val = (self.0 >> 23usize) & 0x01;
28259 val != 0
28260 }
28261 #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."]
28262 pub fn set_ackfailc(&mut self, val: bool) {
28263 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
28264 }
28265 #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."]
28266 pub const fn acktimeoutc(&self) -> bool {
28267 let val = (self.0 >> 24usize) & 0x01;
28268 val != 0
28269 }
28270 #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."]
28271 pub fn set_acktimeoutc(&mut self, val: bool) {
28272 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
28273 }
28274 #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."]
28275 pub const fn vswendc(&self) -> bool {
28276 let val = (self.0 >> 25usize) & 0x01;
28277 val != 0
28278 }
28279 #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."]
28280 pub fn set_vswendc(&mut self, val: bool) {
28281 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
28282 }
28283 #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."]
28284 pub const fn ckstopc(&self) -> bool {
28285 let val = (self.0 >> 26usize) & 0x01;
28286 val != 0
28287 }
28288 #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."]
28289 pub fn set_ckstopc(&mut self, val: bool) {
28290 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
28291 }
28292 #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."]
28293 pub const fn idmatec(&self) -> bool {
28294 let val = (self.0 >> 27usize) & 0x01;
28295 val != 0
28296 }
28297 #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."]
28298 pub fn set_idmatec(&mut self, val: bool) {
28299 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
28300 }
28301 #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."]
28302 pub const fn idmabtcc(&self) -> bool {
28303 let val = (self.0 >> 28usize) & 0x01;
28304 val != 0
28305 }
28306 #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."]
28307 pub fn set_idmabtcc(&mut self, val: bool) {
28308 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
28309 }
28310 }
28311 impl Default for Icr {
28312 fn default() -> Icr {
28313 Icr(0)
28314 }
28315 }
28316 #[doc = "SDMMC IP identification register"]
28317 #[repr(transparent)]
28318 #[derive(Copy, Clone, Eq, PartialEq)]
28319 pub struct Id(pub u32);
28320 impl Id {
28321 #[doc = "SDMMC IP identification."]
28322 pub const fn ip_id(&self) -> u32 {
28323 let val = (self.0 >> 0usize) & 0xffff_ffff;
28324 val as u32
28325 }
28326 #[doc = "SDMMC IP identification."]
28327 pub fn set_ip_id(&mut self, val: u32) {
28328 self.0 =
28329 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
28330 }
28331 }
28332 impl Default for Id {
28333 fn default() -> Id {
28334 Id(0)
28335 }
28336 }
28337 #[doc = "SDMMC power control register"]
28338 #[repr(transparent)]
28339 #[derive(Copy, Clone, Eq, PartialEq)]
28340 pub struct Power(pub u32);
28341 impl Power {
28342 #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."]
28343 pub const fn pwrctrl(&self) -> u8 {
28344 let val = (self.0 >> 0usize) & 0x03;
28345 val as u8
28346 }
28347 #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."]
28348 pub fn set_pwrctrl(&mut self, val: u8) {
28349 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
28350 }
28351 #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"]
28352 pub const fn vswitch(&self) -> bool {
28353 let val = (self.0 >> 2usize) & 0x01;
28354 val != 0
28355 }
28356 #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"]
28357 pub fn set_vswitch(&mut self, val: bool) {
28358 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
28359 }
28360 #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"]
28361 pub const fn vswitchen(&self) -> bool {
28362 let val = (self.0 >> 3usize) & 0x01;
28363 val != 0
28364 }
28365 #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"]
28366 pub fn set_vswitchen(&mut self, val: bool) {
28367 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
28368 }
28369 #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."]
28370 pub const fn dirpol(&self) -> bool {
28371 let val = (self.0 >> 4usize) & 0x01;
28372 val != 0
28373 }
28374 #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."]
28375 pub fn set_dirpol(&mut self, val: bool) {
28376 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
28377 }
28378 }
28379 impl Default for Power {
28380 fn default() -> Power {
28381 Power(0)
28382 }
28383 }
28384 #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."]
28385 #[repr(transparent)]
28386 #[derive(Copy, Clone, Eq, PartialEq)]
28387 pub struct Dtimer(pub u32);
28388 impl Dtimer {
28389 #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."]
28390 pub const fn datatime(&self) -> u32 {
28391 let val = (self.0 >> 0usize) & 0xffff_ffff;
28392 val as u32
28393 }
28394 #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."]
28395 pub fn set_datatime(&mut self, val: u32) {
28396 self.0 =
28397 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
28398 }
28399 }
28400 impl Default for Dtimer {
28401 fn default() -> Dtimer {
28402 Dtimer(0)
28403 }
28404 }
28405 #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."]
28406 #[repr(transparent)]
28407 #[derive(Copy, Clone, Eq, PartialEq)]
28408 pub struct Fifor(pub u32);
28409 impl Fifor {
28410 #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."]
28411 pub const fn fifodata(&self) -> u32 {
28412 let val = (self.0 >> 0usize) & 0xffff_ffff;
28413 val as u32
28414 }
28415 #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."]
28416 pub fn set_fifodata(&mut self, val: u32) {
28417 self.0 =
28418 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
28419 }
28420 }
28421 impl Default for Fifor {
28422 fn default() -> Fifor {
28423 Fifor(0)
28424 }
28425 }
28426 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
28427 #[repr(transparent)]
28428 #[derive(Copy, Clone, Eq, PartialEq)]
28429 pub struct Resp1r(pub u32);
28430 impl Resp1r {
28431 #[doc = "see Table 432"]
28432 pub const fn cardstatus1(&self) -> u32 {
28433 let val = (self.0 >> 0usize) & 0xffff_ffff;
28434 val as u32
28435 }
28436 #[doc = "see Table 432"]
28437 pub fn set_cardstatus1(&mut self, val: u32) {
28438 self.0 =
28439 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
28440 }
28441 }
28442 impl Default for Resp1r {
28443 fn default() -> Resp1r {
28444 Resp1r(0)
28445 }
28446 }
28447 #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."]
28448 #[repr(transparent)]
28449 #[derive(Copy, Clone, Eq, PartialEq)]
28450 pub struct Argr(pub u32);
28451 impl Argr {
28452 #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."]
28453 pub const fn cmdarg(&self) -> u32 {
28454 let val = (self.0 >> 0usize) & 0xffff_ffff;
28455 val as u32
28456 }
28457 #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."]
28458 pub fn set_cmdarg(&mut self, val: u32) {
28459 self.0 =
28460 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
28461 }
28462 }
28463 impl Default for Argr {
28464 fn default() -> Argr {
28465 Argr(0)
28466 }
28467 }
13789 #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"] 28468 #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"]
13790 #[repr(transparent)] 28469 #[repr(transparent)]
13791 #[derive(Copy, Clone, Eq, PartialEq)] 28470 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -14058,6 +28737,1429 @@ pub mod sdmmc_v2 {
14058 Star(0) 28737 Star(0)
14059 } 28738 }
14060 } 28739 }
28740 #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."]
28741 #[repr(transparent)]
28742 #[derive(Copy, Clone, Eq, PartialEq)]
28743 pub struct Acktimer(pub u32);
28744 impl Acktimer {
28745 #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."]
28746 pub const fn acktime(&self) -> u32 {
28747 let val = (self.0 >> 0usize) & 0x01ff_ffff;
28748 val as u32
28749 }
28750 #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."]
28751 pub fn set_acktime(&mut self, val: u32) {
28752 self.0 =
28753 (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize);
28754 }
28755 }
28756 impl Default for Acktimer {
28757 fn default() -> Acktimer {
28758 Acktimer(0)
28759 }
28760 }
28761 #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."]
28762 #[repr(transparent)]
28763 #[derive(Copy, Clone, Eq, PartialEq)]
28764 pub struct Maskr(pub u32);
28765 impl Maskr {
28766 #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."]
28767 pub const fn ccrcfailie(&self) -> bool {
28768 let val = (self.0 >> 0usize) & 0x01;
28769 val != 0
28770 }
28771 #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."]
28772 pub fn set_ccrcfailie(&mut self, val: bool) {
28773 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
28774 }
28775 #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."]
28776 pub const fn dcrcfailie(&self) -> bool {
28777 let val = (self.0 >> 1usize) & 0x01;
28778 val != 0
28779 }
28780 #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."]
28781 pub fn set_dcrcfailie(&mut self, val: bool) {
28782 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
28783 }
28784 #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."]
28785 pub const fn ctimeoutie(&self) -> bool {
28786 let val = (self.0 >> 2usize) & 0x01;
28787 val != 0
28788 }
28789 #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."]
28790 pub fn set_ctimeoutie(&mut self, val: bool) {
28791 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
28792 }
28793 #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."]
28794 pub const fn dtimeoutie(&self) -> bool {
28795 let val = (self.0 >> 3usize) & 0x01;
28796 val != 0
28797 }
28798 #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."]
28799 pub fn set_dtimeoutie(&mut self, val: bool) {
28800 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
28801 }
28802 #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."]
28803 pub const fn txunderrie(&self) -> bool {
28804 let val = (self.0 >> 4usize) & 0x01;
28805 val != 0
28806 }
28807 #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."]
28808 pub fn set_txunderrie(&mut self, val: bool) {
28809 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
28810 }
28811 #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."]
28812 pub const fn rxoverrie(&self) -> bool {
28813 let val = (self.0 >> 5usize) & 0x01;
28814 val != 0
28815 }
28816 #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."]
28817 pub fn set_rxoverrie(&mut self, val: bool) {
28818 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
28819 }
28820 #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."]
28821 pub const fn cmdrendie(&self) -> bool {
28822 let val = (self.0 >> 6usize) & 0x01;
28823 val != 0
28824 }
28825 #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."]
28826 pub fn set_cmdrendie(&mut self, val: bool) {
28827 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
28828 }
28829 #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."]
28830 pub const fn cmdsentie(&self) -> bool {
28831 let val = (self.0 >> 7usize) & 0x01;
28832 val != 0
28833 }
28834 #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."]
28835 pub fn set_cmdsentie(&mut self, val: bool) {
28836 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
28837 }
28838 #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."]
28839 pub const fn dataendie(&self) -> bool {
28840 let val = (self.0 >> 8usize) & 0x01;
28841 val != 0
28842 }
28843 #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."]
28844 pub fn set_dataendie(&mut self, val: bool) {
28845 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
28846 }
28847 #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."]
28848 pub const fn dholdie(&self) -> bool {
28849 let val = (self.0 >> 9usize) & 0x01;
28850 val != 0
28851 }
28852 #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."]
28853 pub fn set_dholdie(&mut self, val: bool) {
28854 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
28855 }
28856 #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."]
28857 pub const fn dbckendie(&self) -> bool {
28858 let val = (self.0 >> 10usize) & 0x01;
28859 val != 0
28860 }
28861 #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."]
28862 pub fn set_dbckendie(&mut self, val: bool) {
28863 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
28864 }
28865 #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."]
28866 pub const fn dabortie(&self) -> bool {
28867 let val = (self.0 >> 11usize) & 0x01;
28868 val != 0
28869 }
28870 #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."]
28871 pub fn set_dabortie(&mut self, val: bool) {
28872 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
28873 }
28874 #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."]
28875 pub const fn txfifoheie(&self) -> bool {
28876 let val = (self.0 >> 14usize) & 0x01;
28877 val != 0
28878 }
28879 #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."]
28880 pub fn set_txfifoheie(&mut self, val: bool) {
28881 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
28882 }
28883 #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."]
28884 pub const fn rxfifohfie(&self) -> bool {
28885 let val = (self.0 >> 15usize) & 0x01;
28886 val != 0
28887 }
28888 #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."]
28889 pub fn set_rxfifohfie(&mut self, val: bool) {
28890 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
28891 }
28892 #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."]
28893 pub const fn rxfifofie(&self) -> bool {
28894 let val = (self.0 >> 17usize) & 0x01;
28895 val != 0
28896 }
28897 #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."]
28898 pub fn set_rxfifofie(&mut self, val: bool) {
28899 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
28900 }
28901 #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."]
28902 pub const fn txfifoeie(&self) -> bool {
28903 let val = (self.0 >> 18usize) & 0x01;
28904 val != 0
28905 }
28906 #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."]
28907 pub fn set_txfifoeie(&mut self, val: bool) {
28908 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
28909 }
28910 #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."]
28911 pub const fn busyd0endie(&self) -> bool {
28912 let val = (self.0 >> 21usize) & 0x01;
28913 val != 0
28914 }
28915 #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."]
28916 pub fn set_busyd0endie(&mut self, val: bool) {
28917 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
28918 }
28919 #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."]
28920 pub const fn sdioitie(&self) -> bool {
28921 let val = (self.0 >> 22usize) & 0x01;
28922 val != 0
28923 }
28924 #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."]
28925 pub fn set_sdioitie(&mut self, val: bool) {
28926 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
28927 }
28928 #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."]
28929 pub const fn ackfailie(&self) -> bool {
28930 let val = (self.0 >> 23usize) & 0x01;
28931 val != 0
28932 }
28933 #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."]
28934 pub fn set_ackfailie(&mut self, val: bool) {
28935 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
28936 }
28937 #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."]
28938 pub const fn acktimeoutie(&self) -> bool {
28939 let val = (self.0 >> 24usize) & 0x01;
28940 val != 0
28941 }
28942 #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."]
28943 pub fn set_acktimeoutie(&mut self, val: bool) {
28944 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
28945 }
28946 #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."]
28947 pub const fn vswendie(&self) -> bool {
28948 let val = (self.0 >> 25usize) & 0x01;
28949 val != 0
28950 }
28951 #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."]
28952 pub fn set_vswendie(&mut self, val: bool) {
28953 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
28954 }
28955 #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."]
28956 pub const fn ckstopie(&self) -> bool {
28957 let val = (self.0 >> 26usize) & 0x01;
28958 val != 0
28959 }
28960 #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."]
28961 pub fn set_ckstopie(&mut self, val: bool) {
28962 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
28963 }
28964 #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."]
28965 pub const fn idmabtcie(&self) -> bool {
28966 let val = (self.0 >> 28usize) & 0x01;
28967 val != 0
28968 }
28969 #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."]
28970 pub fn set_idmabtcie(&mut self, val: bool) {
28971 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
28972 }
28973 }
28974 impl Default for Maskr {
28975 fn default() -> Maskr {
28976 Maskr(0)
28977 }
28978 }
28979 #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."]
28980 #[repr(transparent)]
28981 #[derive(Copy, Clone, Eq, PartialEq)]
28982 pub struct Dctrl(pub u32);
28983 impl Dctrl {
28984 #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."]
28985 pub const fn dten(&self) -> bool {
28986 let val = (self.0 >> 0usize) & 0x01;
28987 val != 0
28988 }
28989 #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."]
28990 pub fn set_dten(&mut self, val: bool) {
28991 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
28992 }
28993 #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
28994 pub const fn dtdir(&self) -> bool {
28995 let val = (self.0 >> 1usize) & 0x01;
28996 val != 0
28997 }
28998 #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
28999 pub fn set_dtdir(&mut self, val: bool) {
29000 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
29001 }
29002 #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
29003 pub const fn dtmode(&self) -> u8 {
29004 let val = (self.0 >> 2usize) & 0x03;
29005 val as u8
29006 }
29007 #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
29008 pub fn set_dtmode(&mut self, val: u8) {
29009 self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize);
29010 }
29011 #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"]
29012 pub const fn dblocksize(&self) -> u8 {
29013 let val = (self.0 >> 4usize) & 0x0f;
29014 val as u8
29015 }
29016 #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"]
29017 pub fn set_dblocksize(&mut self, val: u8) {
29018 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
29019 }
29020 #[doc = "Read wait start. If this bit is set, read wait operation starts."]
29021 pub const fn rwstart(&self) -> bool {
29022 let val = (self.0 >> 8usize) & 0x01;
29023 val != 0
29024 }
29025 #[doc = "Read wait start. If this bit is set, read wait operation starts."]
29026 pub fn set_rwstart(&mut self, val: bool) {
29027 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
29028 }
29029 #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."]
29030 pub const fn rwstop(&self) -> bool {
29031 let val = (self.0 >> 9usize) & 0x01;
29032 val != 0
29033 }
29034 #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."]
29035 pub fn set_rwstop(&mut self, val: bool) {
29036 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
29037 }
29038 #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
29039 pub const fn rwmod(&self) -> bool {
29040 let val = (self.0 >> 10usize) & 0x01;
29041 val != 0
29042 }
29043 #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
29044 pub fn set_rwmod(&mut self, val: bool) {
29045 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
29046 }
29047 #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."]
29048 pub const fn sdioen(&self) -> bool {
29049 let val = (self.0 >> 11usize) & 0x01;
29050 val != 0
29051 }
29052 #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."]
29053 pub fn set_sdioen(&mut self, val: bool) {
29054 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
29055 }
29056 #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
29057 pub const fn bootacken(&self) -> bool {
29058 let val = (self.0 >> 12usize) & 0x01;
29059 val != 0
29060 }
29061 #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
29062 pub fn set_bootacken(&mut self, val: bool) {
29063 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
29064 }
29065 #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."]
29066 pub const fn fiforst(&self) -> bool {
29067 let val = (self.0 >> 13usize) & 0x01;
29068 val != 0
29069 }
29070 #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."]
29071 pub fn set_fiforst(&mut self, val: bool) {
29072 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
29073 }
29074 }
29075 impl Default for Dctrl {
29076 fn default() -> Dctrl {
29077 Dctrl(0)
29078 }
29079 }
29080 #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."]
29081 #[repr(transparent)]
29082 #[derive(Copy, Clone, Eq, PartialEq)]
29083 pub struct Idmactrlr(pub u32);
29084 impl Idmactrlr {
29085 #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
29086 pub const fn idmaen(&self) -> bool {
29087 let val = (self.0 >> 0usize) & 0x01;
29088 val != 0
29089 }
29090 #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
29091 pub fn set_idmaen(&mut self, val: bool) {
29092 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
29093 }
29094 #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
29095 pub const fn idmabmode(&self) -> bool {
29096 let val = (self.0 >> 1usize) & 0x01;
29097 val != 0
29098 }
29099 #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."]
29100 pub fn set_idmabmode(&mut self, val: bool) {
29101 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
29102 }
29103 #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."]
29104 pub const fn idmabact(&self) -> bool {
29105 let val = (self.0 >> 2usize) & 0x01;
29106 val != 0
29107 }
29108 #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."]
29109 pub fn set_idmabact(&mut self, val: bool) {
29110 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
29111 }
29112 }
29113 impl Default for Idmactrlr {
29114 fn default() -> Idmactrlr {
29115 Idmactrlr(0)
29116 }
29117 }
29118 #[doc = "SDMMC IP version register"]
29119 #[repr(transparent)]
29120 #[derive(Copy, Clone, Eq, PartialEq)]
29121 pub struct Ver(pub u32);
29122 impl Ver {
29123 #[doc = "IP minor revision number."]
29124 pub const fn minrev(&self) -> u8 {
29125 let val = (self.0 >> 0usize) & 0x0f;
29126 val as u8
29127 }
29128 #[doc = "IP minor revision number."]
29129 pub fn set_minrev(&mut self, val: u8) {
29130 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
29131 }
29132 #[doc = "IP major revision number."]
29133 pub const fn majrev(&self) -> u8 {
29134 let val = (self.0 >> 4usize) & 0x0f;
29135 val as u8
29136 }
29137 #[doc = "IP major revision number."]
29138 pub fn set_majrev(&mut self, val: u8) {
29139 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
29140 }
29141 }
29142 impl Default for Ver {
29143 fn default() -> Ver {
29144 Ver(0)
29145 }
29146 }
29147 }
29148}
29149pub mod gpio_v1 {
29150 use crate::generic::*;
29151 #[doc = "General purpose I/O"]
29152 #[derive(Copy, Clone)]
29153 pub struct Gpio(pub *mut u8);
29154 unsafe impl Send for Gpio {}
29155 unsafe impl Sync for Gpio {}
29156 impl Gpio {
29157 #[doc = "Port configuration register low (GPIOn_CRL)"]
29158 pub fn cr(self, n: usize) -> Reg<regs::Cr, RW> {
29159 assert!(n < 2usize);
29160 unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) }
29161 }
29162 #[doc = "Port input data register (GPIOn_IDR)"]
29163 pub fn idr(self) -> Reg<regs::Idr, R> {
29164 unsafe { Reg::from_ptr(self.0.add(8usize)) }
29165 }
29166 #[doc = "Port output data register (GPIOn_ODR)"]
29167 pub fn odr(self) -> Reg<regs::Odr, RW> {
29168 unsafe { Reg::from_ptr(self.0.add(12usize)) }
29169 }
29170 #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
29171 pub fn bsrr(self) -> Reg<regs::Bsrr, W> {
29172 unsafe { Reg::from_ptr(self.0.add(16usize)) }
29173 }
29174 #[doc = "Port bit reset register (GPIOn_BRR)"]
29175 pub fn brr(self) -> Reg<regs::Brr, W> {
29176 unsafe { Reg::from_ptr(self.0.add(20usize)) }
29177 }
29178 #[doc = "Port configuration lock register"]
29179 pub fn lckr(self) -> Reg<regs::Lckr, RW> {
29180 unsafe { Reg::from_ptr(self.0.add(24usize)) }
29181 }
29182 }
29183 pub mod regs {
29184 use crate::generic::*;
29185 #[doc = "Port output data register (GPIOn_ODR)"]
29186 #[repr(transparent)]
29187 #[derive(Copy, Clone, Eq, PartialEq)]
29188 pub struct Odr(pub u32);
29189 impl Odr {
29190 #[doc = "Port output data"]
29191 pub fn odr(&self, n: usize) -> super::vals::Odr {
29192 assert!(n < 16usize);
29193 let offs = 0usize + n * 1usize;
29194 let val = (self.0 >> offs) & 0x01;
29195 super::vals::Odr(val as u8)
29196 }
29197 #[doc = "Port output data"]
29198 pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
29199 assert!(n < 16usize);
29200 let offs = 0usize + n * 1usize;
29201 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
29202 }
29203 }
29204 impl Default for Odr {
29205 fn default() -> Odr {
29206 Odr(0)
29207 }
29208 }
29209 #[doc = "Port input data register (GPIOn_IDR)"]
29210 #[repr(transparent)]
29211 #[derive(Copy, Clone, Eq, PartialEq)]
29212 pub struct Idr(pub u32);
29213 impl Idr {
29214 #[doc = "Port input data"]
29215 pub fn idr(&self, n: usize) -> super::vals::Idr {
29216 assert!(n < 16usize);
29217 let offs = 0usize + n * 1usize;
29218 let val = (self.0 >> offs) & 0x01;
29219 super::vals::Idr(val as u8)
29220 }
29221 #[doc = "Port input data"]
29222 pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
29223 assert!(n < 16usize);
29224 let offs = 0usize + n * 1usize;
29225 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
29226 }
29227 }
29228 impl Default for Idr {
29229 fn default() -> Idr {
29230 Idr(0)
29231 }
29232 }
29233 #[doc = "Port configuration lock register"]
29234 #[repr(transparent)]
29235 #[derive(Copy, Clone, Eq, PartialEq)]
29236 pub struct Lckr(pub u32);
29237 impl Lckr {
29238 #[doc = "Port A Lock bit"]
29239 pub fn lck(&self, n: usize) -> super::vals::Lck {
29240 assert!(n < 16usize);
29241 let offs = 0usize + n * 1usize;
29242 let val = (self.0 >> offs) & 0x01;
29243 super::vals::Lck(val as u8)
29244 }
29245 #[doc = "Port A Lock bit"]
29246 pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
29247 assert!(n < 16usize);
29248 let offs = 0usize + n * 1usize;
29249 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
29250 }
29251 #[doc = "Lock key"]
29252 pub const fn lckk(&self) -> super::vals::Lckk {
29253 let val = (self.0 >> 16usize) & 0x01;
29254 super::vals::Lckk(val as u8)
29255 }
29256 #[doc = "Lock key"]
29257 pub fn set_lckk(&mut self, val: super::vals::Lckk) {
29258 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
29259 }
29260 }
29261 impl Default for Lckr {
29262 fn default() -> Lckr {
29263 Lckr(0)
29264 }
29265 }
29266 #[doc = "Port bit set/reset register (GPIOn_BSRR)"]
29267 #[repr(transparent)]
29268 #[derive(Copy, Clone, Eq, PartialEq)]
29269 pub struct Bsrr(pub u32);
29270 impl Bsrr {
29271 #[doc = "Set bit"]
29272 pub fn bs(&self, n: usize) -> bool {
29273 assert!(n < 16usize);
29274 let offs = 0usize + n * 1usize;
29275 let val = (self.0 >> offs) & 0x01;
29276 val != 0
29277 }
29278 #[doc = "Set bit"]
29279 pub fn set_bs(&mut self, n: usize, val: bool) {
29280 assert!(n < 16usize);
29281 let offs = 0usize + n * 1usize;
29282 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
29283 }
29284 #[doc = "Reset bit"]
29285 pub fn br(&self, n: usize) -> bool {
29286 assert!(n < 16usize);
29287 let offs = 16usize + n * 1usize;
29288 let val = (self.0 >> offs) & 0x01;
29289 val != 0
29290 }
29291 #[doc = "Reset bit"]
29292 pub fn set_br(&mut self, n: usize, val: bool) {
29293 assert!(n < 16usize);
29294 let offs = 16usize + n * 1usize;
29295 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
29296 }
29297 }
29298 impl Default for Bsrr {
29299 fn default() -> Bsrr {
29300 Bsrr(0)
29301 }
29302 }
29303 #[doc = "Port bit reset register (GPIOn_BRR)"]
29304 #[repr(transparent)]
29305 #[derive(Copy, Clone, Eq, PartialEq)]
29306 pub struct Brr(pub u32);
29307 impl Brr {
29308 #[doc = "Reset bit"]
29309 pub fn br(&self, n: usize) -> bool {
29310 assert!(n < 16usize);
29311 let offs = 0usize + n * 1usize;
29312 let val = (self.0 >> offs) & 0x01;
29313 val != 0
29314 }
29315 #[doc = "Reset bit"]
29316 pub fn set_br(&mut self, n: usize, val: bool) {
29317 assert!(n < 16usize);
29318 let offs = 0usize + n * 1usize;
29319 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
29320 }
29321 }
29322 impl Default for Brr {
29323 fn default() -> Brr {
29324 Brr(0)
29325 }
29326 }
29327 #[doc = "Port configuration register (GPIOn_CRx)"]
29328 #[repr(transparent)]
29329 #[derive(Copy, Clone, Eq, PartialEq)]
29330 pub struct Cr(pub u32);
29331 impl Cr {
29332 #[doc = "Port n mode bits"]
29333 pub fn mode(&self, n: usize) -> super::vals::Mode {
29334 assert!(n < 8usize);
29335 let offs = 0usize + n * 4usize;
29336 let val = (self.0 >> offs) & 0x03;
29337 super::vals::Mode(val as u8)
29338 }
29339 #[doc = "Port n mode bits"]
29340 pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) {
29341 assert!(n < 8usize);
29342 let offs = 0usize + n * 4usize;
29343 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
29344 }
29345 #[doc = "Port n configuration bits"]
29346 pub fn cnf(&self, n: usize) -> super::vals::Cnf {
29347 assert!(n < 8usize);
29348 let offs = 2usize + n * 4usize;
29349 let val = (self.0 >> offs) & 0x03;
29350 super::vals::Cnf(val as u8)
29351 }
29352 #[doc = "Port n configuration bits"]
29353 pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) {
29354 assert!(n < 8usize);
29355 let offs = 2usize + n * 4usize;
29356 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
29357 }
29358 }
29359 impl Default for Cr {
29360 fn default() -> Cr {
29361 Cr(0)
29362 }
29363 }
29364 }
29365 pub mod vals {
29366 use crate::generic::*;
29367 #[repr(transparent)]
29368 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
29369 pub struct Brw(pub u8);
29370 impl Brw {
29371 #[doc = "No action on the corresponding ODx bit"]
29372 pub const NOACTION: Self = Self(0);
29373 #[doc = "Reset the ODx bit"]
29374 pub const RESET: Self = Self(0x01);
29375 }
29376 #[repr(transparent)]
29377 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
29378 pub struct Idr(pub u8);
29379 impl Idr {
29380 #[doc = "Input is logic low"]
29381 pub const LOW: Self = Self(0);
29382 #[doc = "Input is logic high"]
29383 pub const HIGH: Self = Self(0x01);
29384 }
29385 #[repr(transparent)]
29386 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
29387 pub struct Lck(pub u8);
29388 impl Lck {
29389 #[doc = "Port configuration not locked"]
29390 pub const UNLOCKED: Self = Self(0);
29391 #[doc = "Port configuration locked"]
29392 pub const LOCKED: Self = Self(0x01);
29393 }
29394 #[repr(transparent)]
29395 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
29396 pub struct Bsw(pub u8);
29397 impl Bsw {
29398 #[doc = "No action on the corresponding ODx bit"]
29399 pub const NOACTION: Self = Self(0);
29400 #[doc = "Sets the corresponding ODRx bit"]
29401 pub const SET: Self = Self(0x01);
29402 }
29403 #[repr(transparent)]
29404 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
29405 pub struct Odr(pub u8);
29406 impl Odr {
29407 #[doc = "Set output to logic low"]
29408 pub const LOW: Self = Self(0);
29409 #[doc = "Set output to logic high"]
29410 pub const HIGH: Self = Self(0x01);
29411 }
29412 #[repr(transparent)]
29413 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
29414 pub struct Cnf(pub u8);
29415 impl Cnf {
29416 #[doc = "Analog mode / Push-Pull mode"]
29417 pub const PUSHPULL: Self = Self(0);
29418 #[doc = "Floating input (reset state) / Open Drain-Mode"]
29419 pub const OPENDRAIN: Self = Self(0x01);
29420 #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"]
29421 pub const ALTPUSHPULL: Self = Self(0x02);
29422 #[doc = "Alternate Function Open-Drain Mode"]
29423 pub const ALTOPENDRAIN: Self = Self(0x03);
29424 }
29425 #[repr(transparent)]
29426 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
29427 pub struct Lckk(pub u8);
29428 impl Lckk {
29429 #[doc = "Port configuration lock key not active"]
29430 pub const NOTACTIVE: Self = Self(0);
29431 #[doc = "Port configuration lock key active"]
29432 pub const ACTIVE: Self = Self(0x01);
29433 }
29434 #[repr(transparent)]
29435 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
29436 pub struct Mode(pub u8);
29437 impl Mode {
29438 #[doc = "Input mode (reset state)"]
29439 pub const INPUT: Self = Self(0);
29440 #[doc = "Output mode 10 MHz"]
29441 pub const OUTPUT: Self = Self(0x01);
29442 #[doc = "Output mode 2 MHz"]
29443 pub const OUTPUT2: Self = Self(0x02);
29444 #[doc = "Output mode 50 MHz"]
29445 pub const OUTPUT50: Self = Self(0x03);
29446 }
29447 }
29448}
29449pub mod rng_v1 {
29450 use crate::generic::*;
29451 #[doc = "Random number generator"]
29452 #[derive(Copy, Clone)]
29453 pub struct Rng(pub *mut u8);
29454 unsafe impl Send for Rng {}
29455 unsafe impl Sync for Rng {}
29456 impl Rng {
29457 #[doc = "control register"]
29458 pub fn cr(self) -> Reg<regs::Cr, RW> {
29459 unsafe { Reg::from_ptr(self.0.add(0usize)) }
29460 }
29461 #[doc = "status register"]
29462 pub fn sr(self) -> Reg<regs::Sr, RW> {
29463 unsafe { Reg::from_ptr(self.0.add(4usize)) }
29464 }
29465 #[doc = "data register"]
29466 pub fn dr(self) -> Reg<u32, R> {
29467 unsafe { Reg::from_ptr(self.0.add(8usize)) }
29468 }
29469 }
29470 pub mod regs {
29471 use crate::generic::*;
29472 #[doc = "control register"]
29473 #[repr(transparent)]
29474 #[derive(Copy, Clone, Eq, PartialEq)]
29475 pub struct Cr(pub u32);
29476 impl Cr {
29477 #[doc = "Random number generator enable"]
29478 pub const fn rngen(&self) -> bool {
29479 let val = (self.0 >> 2usize) & 0x01;
29480 val != 0
29481 }
29482 #[doc = "Random number generator enable"]
29483 pub fn set_rngen(&mut self, val: bool) {
29484 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
29485 }
29486 #[doc = "Interrupt enable"]
29487 pub const fn ie(&self) -> bool {
29488 let val = (self.0 >> 3usize) & 0x01;
29489 val != 0
29490 }
29491 #[doc = "Interrupt enable"]
29492 pub fn set_ie(&mut self, val: bool) {
29493 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
29494>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
29495 }
29496 }
29497 impl Default for Idmabsizer {
29498 fn default() -> Idmabsizer {
29499 Idmabsizer(0)
29500 }
29501 }
29502<<<<<<< HEAD
29503 #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."]
29504 #[repr(transparent)]
29505 #[derive(Copy, Clone, Eq, PartialEq)]
29506 pub struct Clkcr(pub u32);
29507 impl Clkcr {
29508 #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."]
29509 pub const fn clkdiv(&self) -> u16 {
29510 let val = (self.0 >> 0usize) & 0x03ff;
29511 val as u16
29512 }
29513 #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."]
29514 pub fn set_clkdiv(&mut self, val: u16) {
29515 self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize);
29516 }
29517 #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"]
29518 pub const fn pwrsav(&self) -> bool {
29519 let val = (self.0 >> 12usize) & 0x01;
29520 val != 0
29521 }
29522 #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"]
29523 pub fn set_pwrsav(&mut self, val: bool) {
29524 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
29525 }
29526 #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
29527 pub const fn widbus(&self) -> u8 {
29528 let val = (self.0 >> 14usize) & 0x03;
29529 val as u8
29530 }
29531 #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
29532 pub fn set_widbus(&mut self, val: u8) {
29533 self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize);
29534 }
29535 #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."]
29536 pub const fn negedge(&self) -> bool {
29537 let val = (self.0 >> 16usize) & 0x01;
29538 val != 0
29539 }
29540 #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."]
29541 pub fn set_negedge(&mut self, val: bool) {
29542 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
29543 }
29544 #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."]
29545 pub const fn hwfc_en(&self) -> bool {
29546 let val = (self.0 >> 17usize) & 0x01;
29547 val != 0
29548 }
29549 #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."]
29550 pub fn set_hwfc_en(&mut self, val: bool) {
29551 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
29552 }
29553 #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0)"]
29554 pub const fn ddr(&self) -> bool {
29555 let val = (self.0 >> 18usize) & 0x01;
29556 val != 0
29557 }
29558 #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0)"]
29559 pub fn set_ddr(&mut self, val: bool) {
29560 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
29561 }
29562 #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
29563 pub const fn busspeed(&self) -> bool {
29564 let val = (self.0 >> 19usize) & 0x01;
29565 val != 0
29566 }
29567 #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
29568 pub fn set_busspeed(&mut self, val: bool) {
29569 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
29570 }
29571 #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
29572 pub const fn selclkrx(&self) -> u8 {
29573 let val = (self.0 >> 20usize) & 0x03;
29574 val as u8
29575 }
29576 #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"]
29577 pub fn set_selclkrx(&mut self, val: u8) {
29578 self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
29579 }
29580 }
29581 impl Default for Clkcr {
29582 fn default() -> Clkcr {
29583 Clkcr(0)
29584 }
29585 }
29586 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
29587 #[repr(transparent)]
29588 #[derive(Copy, Clone, Eq, PartialEq)]
29589 pub struct Resp2r(pub u32);
29590 impl Resp2r {
29591 #[doc = "see Table404."]
29592 pub const fn cardstatus2(&self) -> u32 {
29593 let val = (self.0 >> 0usize) & 0xffff_ffff;
29594 val as u32
29595 }
29596 #[doc = "see Table404."]
29597 pub fn set_cardstatus2(&mut self, val: u32) {
29598 self.0 =
29599 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
29600 }
29601 }
29602 impl Default for Resp2r {
29603 fn default() -> Resp2r {
29604 Resp2r(0)
29605 }
29606 }
29607 #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"]
29608=======
29609 #[doc = "status register"]
29610 #[repr(transparent)]
29611 #[derive(Copy, Clone, Eq, PartialEq)]
29612 pub struct Sr(pub u32);
29613 impl Sr {
29614 #[doc = "Data ready"]
29615 pub const fn drdy(&self) -> bool {
29616 let val = (self.0 >> 0usize) & 0x01;
29617 val != 0
29618 }
29619 #[doc = "Data ready"]
29620 pub fn set_drdy(&mut self, val: bool) {
29621 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
29622 }
29623 #[doc = "Clock error current status"]
29624 pub const fn cecs(&self) -> bool {
29625 let val = (self.0 >> 1usize) & 0x01;
29626 val != 0
29627 }
29628 #[doc = "Clock error current status"]
29629 pub fn set_cecs(&mut self, val: bool) {
29630 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
29631 }
29632 #[doc = "Seed error current status"]
29633 pub const fn secs(&self) -> bool {
29634 let val = (self.0 >> 2usize) & 0x01;
29635 val != 0
29636 }
29637 #[doc = "Seed error current status"]
29638 pub fn set_secs(&mut self, val: bool) {
29639 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
29640 }
29641 #[doc = "Clock error interrupt status"]
29642 pub const fn ceis(&self) -> bool {
29643 let val = (self.0 >> 5usize) & 0x01;
29644 val != 0
29645 }
29646 #[doc = "Clock error interrupt status"]
29647 pub fn set_ceis(&mut self, val: bool) {
29648 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
29649 }
29650 #[doc = "Seed error interrupt status"]
29651 pub const fn seis(&self) -> bool {
29652 let val = (self.0 >> 6usize) & 0x01;
29653 val != 0
29654 }
29655 #[doc = "Seed error interrupt status"]
29656 pub fn set_seis(&mut self, val: bool) {
29657 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
29658 }
29659 }
29660 impl Default for Sr {
29661 fn default() -> Sr {
29662 Sr(0)
29663 }
29664 }
29665 }
29666}
29667pub mod syscfg_l4 {
29668 use crate::generic::*;
29669 #[doc = "System configuration controller"]
29670 #[derive(Copy, Clone)]
29671 pub struct Syscfg(pub *mut u8);
29672 unsafe impl Send for Syscfg {}
29673 unsafe impl Sync for Syscfg {}
29674 impl Syscfg {
29675 #[doc = "memory remap register"]
29676 pub fn memrmp(self) -> Reg<regs::Memrmp, RW> {
29677 unsafe { Reg::from_ptr(self.0.add(0usize)) }
29678 }
29679 #[doc = "configuration register 1"]
29680 pub fn cfgr1(self) -> Reg<regs::Cfgr1, RW> {
29681 unsafe { Reg::from_ptr(self.0.add(4usize)) }
29682 }
29683 #[doc = "external interrupt configuration register 1"]
29684 pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
29685 assert!(n < 4usize);
29686 unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
29687 }
29688 #[doc = "SCSR"]
29689 pub fn scsr(self) -> Reg<regs::Scsr, RW> {
29690 unsafe { Reg::from_ptr(self.0.add(24usize)) }
29691 }
29692 #[doc = "CFGR2"]
29693 pub fn cfgr2(self) -> Reg<regs::Cfgr2, RW> {
29694 unsafe { Reg::from_ptr(self.0.add(28usize)) }
29695 }
29696 #[doc = "SWPR"]
29697 pub fn swpr(self) -> Reg<regs::Swpr, W> {
29698 unsafe { Reg::from_ptr(self.0.add(32usize)) }
29699 }
29700 #[doc = "SKR"]
29701 pub fn skr(self) -> Reg<regs::Skr, W> {
29702 unsafe { Reg::from_ptr(self.0.add(36usize)) }
29703 }
29704 }
29705 pub mod regs {
29706 use crate::generic::*;
29707 #[doc = "configuration register 1"]
29708>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
29709 #[repr(transparent)]
29710 #[derive(Copy, Clone, Eq, PartialEq)]
29711 pub struct Cfgr1(pub u32);
29712 impl Cfgr1 {
29713 #[doc = "Firewall disable"]
29714 pub const fn fwdis(&self) -> bool {
29715 let val = (self.0 >> 0usize) & 0x01;
29716 val != 0
29717 }
29718 #[doc = "Firewall disable"]
29719 pub fn set_fwdis(&mut self, val: bool) {
29720 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
29721 }
29722 #[doc = "I/O analog switch voltage booster enable"]
29723 pub const fn boosten(&self) -> bool {
29724 let val = (self.0 >> 8usize) & 0x01;
29725 val != 0
29726 }
29727 #[doc = "I/O analog switch voltage booster enable"]
29728 pub fn set_boosten(&mut self, val: bool) {
29729 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
29730 }
29731 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
29732 pub const fn i2c_pb6_fmp(&self) -> bool {
29733 let val = (self.0 >> 16usize) & 0x01;
29734 val != 0
29735 }
29736 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"]
29737 pub fn set_i2c_pb6_fmp(&mut self, val: bool) {
29738 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
29739 }
29740 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
29741 pub const fn i2c_pb7_fmp(&self) -> bool {
29742 let val = (self.0 >> 17usize) & 0x01;
29743 val != 0
29744 }
29745 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"]
29746 pub fn set_i2c_pb7_fmp(&mut self, val: bool) {
29747 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
29748 }
29749 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
29750 pub const fn i2c_pb8_fmp(&self) -> bool {
29751 let val = (self.0 >> 18usize) & 0x01;
29752 val != 0
29753 }
29754 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"]
29755 pub fn set_i2c_pb8_fmp(&mut self, val: bool) {
29756 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
29757 }
29758 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
29759 pub const fn i2c_pb9_fmp(&self) -> bool {
29760 let val = (self.0 >> 19usize) & 0x01;
29761 val != 0
29762 }
29763 #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"]
29764 pub fn set_i2c_pb9_fmp(&mut self, val: bool) {
29765 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
29766 }
29767 #[doc = "I2C1 Fast-mode Plus driving capability activation"]
29768 pub const fn i2c1_fmp(&self) -> bool {
29769 let val = (self.0 >> 20usize) & 0x01;
29770 val != 0
29771 }
29772 #[doc = "I2C1 Fast-mode Plus driving capability activation"]
29773 pub fn set_i2c1_fmp(&mut self, val: bool) {
29774 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
29775 }
29776 #[doc = "I2C2 Fast-mode Plus driving capability activation"]
29777 pub const fn i2c2_fmp(&self) -> bool {
29778 let val = (self.0 >> 21usize) & 0x01;
29779 val != 0
29780 }
29781 #[doc = "I2C2 Fast-mode Plus driving capability activation"]
29782 pub fn set_i2c2_fmp(&mut self, val: bool) {
29783 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
29784 }
29785 #[doc = "I2C3 Fast-mode Plus driving capability activation"]
29786 pub const fn i2c3_fmp(&self) -> bool {
29787 let val = (self.0 >> 22usize) & 0x01;
29788 val != 0
29789 }
29790 #[doc = "I2C3 Fast-mode Plus driving capability activation"]
29791 pub fn set_i2c3_fmp(&mut self, val: bool) {
29792 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
29793 }
29794 #[doc = "Floating Point Unit interrupts enable bits"]
29795 pub const fn fpu_ie(&self) -> u8 {
29796 let val = (self.0 >> 26usize) & 0x3f;
29797 val as u8
29798 }
29799 #[doc = "Floating Point Unit interrupts enable bits"]
29800 pub fn set_fpu_ie(&mut self, val: u8) {
29801 self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize);
29802 }
29803 }
29804 impl Default for Cfgr1 {
29805 fn default() -> Cfgr1 {
29806 Cfgr1(0)
29807 }
29808 }
29809 #[doc = "SWPR"]
29810 #[repr(transparent)]
29811 #[derive(Copy, Clone, Eq, PartialEq)]
29812 pub struct Swpr(pub u32);
29813 impl Swpr {
29814 #[doc = "SRAWM2 write protection."]
29815 pub fn pwp(&self, n: usize) -> bool {
29816 assert!(n < 32usize);
29817 let offs = 0usize + n * 1usize;
29818 let val = (self.0 >> offs) & 0x01;
29819 val != 0
29820 }
29821 #[doc = "SRAWM2 write protection."]
29822 pub fn set_pwp(&mut self, n: usize, val: bool) {
29823 assert!(n < 32usize);
29824 let offs = 0usize + n * 1usize;
29825 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
29826 }
29827 }
29828 impl Default for Swpr {
29829 fn default() -> Swpr {
29830 Swpr(0)
29831 }
29832 }
29833 #[doc = "SKR"]
29834 #[repr(transparent)]
29835 #[derive(Copy, Clone, Eq, PartialEq)]
29836 pub struct Skr(pub u32);
29837 impl Skr {
29838 #[doc = "SRAM2 write protection key for software erase"]
29839 pub const fn key(&self) -> u8 {
29840 let val = (self.0 >> 0usize) & 0xff;
29841 val as u8
29842 }
29843 #[doc = "SRAM2 write protection key for software erase"]
29844 pub fn set_key(&mut self, val: u8) {
29845 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
29846 }
29847 }
29848 impl Default for Skr {
29849 fn default() -> Skr {
29850 Skr(0)
29851 }
29852 }
29853 #[doc = "SCSR"]
29854 #[repr(transparent)]
29855 #[derive(Copy, Clone, Eq, PartialEq)]
29856 pub struct Scsr(pub u32);
29857 impl Scsr {
29858 #[doc = "SRAM2 Erase"]
29859 pub const fn sram2er(&self) -> bool {
29860 let val = (self.0 >> 0usize) & 0x01;
29861 val != 0
29862 }
29863 #[doc = "SRAM2 Erase"]
29864 pub fn set_sram2er(&mut self, val: bool) {
29865 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
29866 }
29867 #[doc = "SRAM2 busy by erase operation"]
29868 pub const fn sram2bsy(&self) -> bool {
29869 let val = (self.0 >> 1usize) & 0x01;
29870 val != 0
29871 }
29872 #[doc = "SRAM2 busy by erase operation"]
29873 pub fn set_sram2bsy(&mut self, val: bool) {
29874 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
29875 }
29876 }
29877 impl Default for Scsr {
29878 fn default() -> Scsr {
29879 Scsr(0)
29880 }
29881 }
29882 #[doc = "CFGR2"]
29883 #[repr(transparent)]
29884 #[derive(Copy, Clone, Eq, PartialEq)]
29885 pub struct Cfgr2(pub u32);
29886 impl Cfgr2 {
29887 #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
29888 pub const fn cll(&self) -> bool {
29889 let val = (self.0 >> 0usize) & 0x01;
29890 val != 0
29891 }
29892 #[doc = "Cortex LOCKUP (Hardfault) output enable bit"]
29893 pub fn set_cll(&mut self, val: bool) {
29894 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
29895 }
29896 #[doc = "SRAM2 parity lock bit"]
29897 pub const fn spl(&self) -> bool {
29898 let val = (self.0 >> 1usize) & 0x01;
29899 val != 0
29900 }
29901 #[doc = "SRAM2 parity lock bit"]
29902 pub fn set_spl(&mut self, val: bool) {
29903 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
29904 }
29905 #[doc = "PVD lock enable bit"]
29906 pub const fn pvdl(&self) -> bool {
29907 let val = (self.0 >> 2usize) & 0x01;
29908 val != 0
29909 }
29910 #[doc = "PVD lock enable bit"]
29911 pub fn set_pvdl(&mut self, val: bool) {
29912 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
29913 }
29914 #[doc = "ECC Lock"]
29915 pub const fn eccl(&self) -> bool {
29916 let val = (self.0 >> 3usize) & 0x01;
29917 val != 0
29918 }
29919 #[doc = "ECC Lock"]
29920 pub fn set_eccl(&mut self, val: bool) {
29921 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
29922 }
29923 #[doc = "SRAM2 parity error flag"]
29924 pub const fn spf(&self) -> bool {
29925 let val = (self.0 >> 8usize) & 0x01;
29926 val != 0
29927 }
29928 #[doc = "SRAM2 parity error flag"]
29929 pub fn set_spf(&mut self, val: bool) {
29930 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
29931 }
29932 }
29933 impl Default for Cfgr2 {
29934 fn default() -> Cfgr2 {
29935 Cfgr2(0)
29936 }
29937 }
29938 #[doc = "memory remap register"]
29939 #[repr(transparent)]
29940 #[derive(Copy, Clone, Eq, PartialEq)]
29941 pub struct Memrmp(pub u32);
29942 impl Memrmp {
29943 #[doc = "Memory mapping selection"]
29944 pub const fn mem_mode(&self) -> u8 {
29945 let val = (self.0 >> 0usize) & 0x07;
29946 val as u8
29947 }
29948 #[doc = "Memory mapping selection"]
29949 pub fn set_mem_mode(&mut self, val: u8) {
29950 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
29951 }
29952 #[doc = "QUADSPI memory mapping swap"]
29953 pub const fn qfs(&self) -> bool {
29954 let val = (self.0 >> 3usize) & 0x01;
29955 val != 0
29956 }
29957 #[doc = "QUADSPI memory mapping swap"]
29958 pub fn set_qfs(&mut self, val: bool) {
29959 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
29960 }
29961 #[doc = "Flash Bank mode selection"]
29962 pub const fn fb_mode(&self) -> bool {
29963 let val = (self.0 >> 8usize) & 0x01;
29964 val != 0
29965 }
29966 #[doc = "Flash Bank mode selection"]
29967 pub fn set_fb_mode(&mut self, val: bool) {
29968 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
29969 }
29970 }
29971 impl Default for Memrmp {
29972 fn default() -> Memrmp {
29973 Memrmp(0)
29974 }
29975 }
29976 #[doc = "external interrupt configuration register 4"]
29977 #[repr(transparent)]
29978 #[derive(Copy, Clone, Eq, PartialEq)]
29979 pub struct Exticr(pub u32);
29980 impl Exticr {
29981 #[doc = "EXTI12 configuration bits"]
29982 pub fn exti(&self, n: usize) -> u8 {
29983 assert!(n < 4usize);
29984 let offs = 0usize + n * 4usize;
29985 let val = (self.0 >> offs) & 0x0f;
29986 val as u8
29987 }
29988 #[doc = "EXTI12 configuration bits"]
29989 pub fn set_exti(&mut self, n: usize, val: u8) {
29990 assert!(n < 4usize);
29991 let offs = 0usize + n * 4usize;
29992 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
29993 }
29994 }
29995 impl Default for Exticr {
29996 fn default() -> Exticr {
29997 Exticr(0)
29998 }
29999 }
30000 }
30001}
30002pub mod syscfg_h7 {
30003 use crate::generic::*;
30004 #[doc = "System configuration controller"]
30005 #[derive(Copy, Clone)]
30006 pub struct Syscfg(pub *mut u8);
30007 unsafe impl Send for Syscfg {}
30008 unsafe impl Sync for Syscfg {}
30009 impl Syscfg {
30010 #[doc = "peripheral mode configuration register"]
30011 pub fn pmcr(self) -> Reg<regs::Pmcr, RW> {
30012 unsafe { Reg::from_ptr(self.0.add(4usize)) }
30013 }
30014 #[doc = "external interrupt configuration register 1"]
30015 pub fn exticr(self, n: usize) -> Reg<regs::Exticr, RW> {
30016 assert!(n < 4usize);
30017 unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) }
30018 }
30019 #[doc = "compensation cell control/status register"]
30020 pub fn cccsr(self) -> Reg<regs::Cccsr, RW> {
30021 unsafe { Reg::from_ptr(self.0.add(32usize)) }
30022 }
30023 #[doc = "SYSCFG compensation cell value register"]
30024 pub fn ccvr(self) -> Reg<regs::Ccvr, R> {
30025 unsafe { Reg::from_ptr(self.0.add(36usize)) }
30026 }
30027 #[doc = "SYSCFG compensation cell code register"]
30028 pub fn cccr(self) -> Reg<regs::Cccr, RW> {
30029 unsafe { Reg::from_ptr(self.0.add(40usize)) }
30030 }
30031 #[doc = "SYSCFG power control register"]
30032 pub fn pwrcr(self) -> Reg<regs::Pwrcr, RW> {
30033 unsafe { Reg::from_ptr(self.0.add(44usize)) }
30034 }
30035 #[doc = "SYSCFG package register"]
30036 pub fn pkgr(self) -> Reg<regs::Pkgr, R> {
30037 unsafe { Reg::from_ptr(self.0.add(292usize)) }
30038 }
30039 #[doc = "SYSCFG user register 0"]
30040 pub fn ur0(self) -> Reg<regs::Ur0, R> {
30041 unsafe { Reg::from_ptr(self.0.add(768usize)) }
30042 }
30043 #[doc = "SYSCFG user register 2"]
30044 pub fn ur2(self) -> Reg<regs::Ur2, RW> {
30045 unsafe { Reg::from_ptr(self.0.add(776usize)) }
30046 }
30047 #[doc = "SYSCFG user register 3"]
30048 pub fn ur3(self) -> Reg<regs::Ur3, RW> {
30049 unsafe { Reg::from_ptr(self.0.add(780usize)) }
30050 }
30051 #[doc = "SYSCFG user register 4"]
30052 pub fn ur4(self) -> Reg<regs::Ur4, R> {
30053 unsafe { Reg::from_ptr(self.0.add(784usize)) }
30054 }
30055 #[doc = "SYSCFG user register 5"]
30056 pub fn ur5(self) -> Reg<regs::Ur5, R> {
30057 unsafe { Reg::from_ptr(self.0.add(788usize)) }
30058 }
30059 #[doc = "SYSCFG user register 6"]
30060 pub fn ur6(self) -> Reg<regs::Ur6, R> {
30061 unsafe { Reg::from_ptr(self.0.add(792usize)) }
30062 }
30063 #[doc = "SYSCFG user register 7"]
30064 pub fn ur7(self) -> Reg<regs::Ur7, R> {
30065 unsafe { Reg::from_ptr(self.0.add(796usize)) }
30066 }
30067 #[doc = "SYSCFG user register 8"]
30068 pub fn ur8(self) -> Reg<regs::Ur8, R> {
30069 unsafe { Reg::from_ptr(self.0.add(800usize)) }
30070 }
30071 #[doc = "SYSCFG user register 9"]
30072 pub fn ur9(self) -> Reg<regs::Ur9, R> {
30073 unsafe { Reg::from_ptr(self.0.add(804usize)) }
30074 }
30075 #[doc = "SYSCFG user register 10"]
30076 pub fn ur10(self) -> Reg<regs::Ur10, R> {
30077 unsafe { Reg::from_ptr(self.0.add(808usize)) }
30078 }
30079 #[doc = "SYSCFG user register 11"]
30080 pub fn ur11(self) -> Reg<regs::Ur11, R> {
30081 unsafe { Reg::from_ptr(self.0.add(812usize)) }
30082 }
30083 #[doc = "SYSCFG user register 12"]
30084 pub fn ur12(self) -> Reg<regs::Ur12, R> {
30085 unsafe { Reg::from_ptr(self.0.add(816usize)) }
30086 }
30087 #[doc = "SYSCFG user register 13"]
30088 pub fn ur13(self) -> Reg<regs::Ur13, R> {
30089 unsafe { Reg::from_ptr(self.0.add(820usize)) }
30090 }
30091 #[doc = "SYSCFG user register 14"]
30092 pub fn ur14(self) -> Reg<regs::Ur14, RW> {
30093 unsafe { Reg::from_ptr(self.0.add(824usize)) }
30094 }
30095 #[doc = "SYSCFG user register 15"]
30096 pub fn ur15(self) -> Reg<regs::Ur15, R> {
30097 unsafe { Reg::from_ptr(self.0.add(828usize)) }
30098 }
30099 #[doc = "SYSCFG user register 16"]
30100 pub fn ur16(self) -> Reg<regs::Ur16, R> {
30101 unsafe { Reg::from_ptr(self.0.add(832usize)) }
30102 }
30103 #[doc = "SYSCFG user register 17"]
30104 pub fn ur17(self) -> Reg<regs::Ur17, R> {
30105 unsafe { Reg::from_ptr(self.0.add(836usize)) }
30106 }
30107 }
30108 pub mod regs {
30109 use crate::generic::*;
30110 #[doc = "SYSCFG user register 10"]
30111 #[repr(transparent)]
30112 #[derive(Copy, Clone, Eq, PartialEq)]
30113 pub struct Ur10(pub u32);
30114 impl Ur10 {
30115 #[doc = "Protected area end address for bank 2"]
30116 pub const fn pa_end_2(&self) -> u16 {
30117 let val = (self.0 >> 0usize) & 0x0fff;
30118 val as u16
30119 }
30120 #[doc = "Protected area end address for bank 2"]
30121 pub fn set_pa_end_2(&mut self, val: u16) {
30122 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
30123 }
30124 #[doc = "Secured area start address for bank 2"]
30125 pub const fn sa_beg_2(&self) -> u16 {
30126 let val = (self.0 >> 16usize) & 0x0fff;
30127 val as u16
30128 }
30129<<<<<<< HEAD
30130 #[doc = "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
30131 pub const fn ckstop(&self) -> bool {
30132 let val = (self.0 >> 26usize) & 0x01;
30133 val != 0
30134 }
30135 #[doc = "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
30136 pub fn set_ckstop(&mut self, val: bool) {
30137 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
30138 }
30139 #[doc = "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
30140 pub const fn idmate(&self) -> bool {
30141 let val = (self.0 >> 27usize) & 0x01;
30142 val != 0
30143 }
30144 #[doc = "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
30145 pub fn set_idmate(&mut self, val: bool) {
30146 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
30147 }
30148 #[doc = "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
30149 pub const fn idmabtc(&self) -> bool {
30150 let val = (self.0 >> 28usize) & 0x01;
30151 val != 0
30152 }
30153 #[doc = "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."]
30154 pub fn set_idmabtc(&mut self, val: bool) {
30155 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
30156 }
30157 }
30158 impl Default for Star {
30159 fn default() -> Star {
30160 Star(0)
30161 }
30162 }
14061 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] 30163 #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."]
14062 #[repr(transparent)] 30164 #[repr(transparent)]
14063 #[derive(Copy, Clone, Eq, PartialEq)] 30165 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -14687,31 +30789,439 @@ pub mod sdmmc_v2 {
14687 impl Default for Dctrl { 30789 impl Default for Dctrl {
14688 fn default() -> Dctrl { 30790 fn default() -> Dctrl {
14689 Dctrl(0) 30791 Dctrl(0)
30792=======
30793 #[doc = "Secured area start address for bank 2"]
30794 pub fn set_sa_beg_2(&mut self, val: u16) {
30795 self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
14690 } 30796 }
14691 } 30797 }
14692 #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] 30798 impl Default for Ur10 {
30799 fn default() -> Ur10 {
30800 Ur10(0)
30801 }
30802 }
30803 #[doc = "SYSCFG user register 9"]
14693 #[repr(transparent)] 30804 #[repr(transparent)]
14694 #[derive(Copy, Clone, Eq, PartialEq)] 30805 #[derive(Copy, Clone, Eq, PartialEq)]
14695 pub struct Idmabase1r(pub u32); 30806 pub struct Ur9(pub u32);
14696 impl Idmabase1r { 30807 impl Ur9 {
14697 #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] 30808 #[doc = "Write protection for flash bank 2"]
14698are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] 30809 pub const fn wrpn_2(&self) -> u8 {
14699 pub const fn idmabase1(&self) -> u32 { 30810 let val = (self.0 >> 0usize) & 0xff;
14700 let val = (self.0 >> 0usize) & 0xffff_ffff; 30811 val as u8
14701 val as u32
14702 } 30812 }
14703 #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] 30813 #[doc = "Write protection for flash bank 2"]
14704are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] 30814 pub fn set_wrpn_2(&mut self, val: u8) {
14705 pub fn set_idmabase1(&mut self, val: u32) { 30815 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
14706 self.0 = 30816 }
14707 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); 30817 #[doc = "Protected area start address for bank 2"]
30818 pub const fn pa_beg_2(&self) -> u16 {
30819 let val = (self.0 >> 16usize) & 0x0fff;
30820 val as u16
30821 }
30822 #[doc = "Protected area start address for bank 2"]
30823 pub fn set_pa_beg_2(&mut self, val: u16) {
30824 self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
14708 } 30825 }
14709 } 30826 }
14710 impl Default for Idmabase1r { 30827 impl Default for Ur9 {
14711 fn default() -> Idmabase1r { 30828 fn default() -> Ur9 {
14712 Idmabase1r(0) 30829 Ur9(0)
14713 } 30830 }
14714 } 30831 }
30832 #[doc = "SYSCFG user register 14"]
30833 #[repr(transparent)]
30834 #[derive(Copy, Clone, Eq, PartialEq)]
30835 pub struct Ur14(pub u32);
30836 impl Ur14 {
30837 #[doc = "D1 Stop Reset"]
30838 pub const fn d1stprst(&self) -> bool {
30839 let val = (self.0 >> 0usize) & 0x01;
30840 val != 0
30841 }
30842 #[doc = "D1 Stop Reset"]
30843 pub fn set_d1stprst(&mut self, val: bool) {
30844 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
30845 }
30846 }
30847 impl Default for Ur14 {
30848 fn default() -> Ur14 {
30849 Ur14(0)
30850 }
30851 }
30852 #[doc = "SYSCFG power control register"]
30853 #[repr(transparent)]
30854 #[derive(Copy, Clone, Eq, PartialEq)]
30855 pub struct Pwrcr(pub u32);
30856 impl Pwrcr {
30857 #[doc = "Overdrive enable"]
30858 pub const fn oden(&self) -> u8 {
30859 let val = (self.0 >> 0usize) & 0x0f;
30860 val as u8
30861 }
30862 #[doc = "Overdrive enable"]
30863 pub fn set_oden(&mut self, val: u8) {
30864 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
30865 }
30866 }
30867 impl Default for Pwrcr {
30868 fn default() -> Pwrcr {
30869 Pwrcr(0)
30870 }
30871 }
30872 #[doc = "SYSCFG user register 5"]
30873 #[repr(transparent)]
30874 #[derive(Copy, Clone, Eq, PartialEq)]
30875 pub struct Ur5(pub u32);
30876 impl Ur5 {
30877 #[doc = "Mass erase secured area disabled for bank 1"]
30878 pub const fn mesad_1(&self) -> bool {
30879 let val = (self.0 >> 0usize) & 0x01;
30880 val != 0
30881 }
30882 #[doc = "Mass erase secured area disabled for bank 1"]
30883 pub fn set_mesad_1(&mut self, val: bool) {
30884 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
30885 }
30886 #[doc = "Write protection for flash bank 1"]
30887 pub const fn wrpn_1(&self) -> u8 {
30888 let val = (self.0 >> 16usize) & 0xff;
30889 val as u8
30890 }
30891 #[doc = "Write protection for flash bank 1"]
30892 pub fn set_wrpn_1(&mut self, val: u8) {
30893 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
30894 }
30895 }
30896 impl Default for Ur5 {
30897 fn default() -> Ur5 {
30898 Ur5(0)
30899 }
30900 }
30901 #[doc = "SYSCFG user register 11"]
30902 #[repr(transparent)]
30903 #[derive(Copy, Clone, Eq, PartialEq)]
30904 pub struct Ur11(pub u32);
30905 impl Ur11 {
30906 #[doc = "Secured area end address for bank 2"]
30907 pub const fn sa_end_2(&self) -> u16 {
30908 let val = (self.0 >> 0usize) & 0x0fff;
30909 val as u16
30910 }
30911 #[doc = "Secured area end address for bank 2"]
30912 pub fn set_sa_end_2(&mut self, val: u16) {
30913 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
30914 }
30915 #[doc = "Independent Watchdog 1 mode"]
30916 pub const fn iwdg1m(&self) -> bool {
30917 let val = (self.0 >> 16usize) & 0x01;
30918 val != 0
30919 }
30920 #[doc = "Independent Watchdog 1 mode"]
30921 pub fn set_iwdg1m(&mut self, val: bool) {
30922 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
30923 }
30924 }
30925 impl Default for Ur11 {
30926 fn default() -> Ur11 {
30927 Ur11(0)
30928 }
30929 }
30930 #[doc = "SYSCFG compensation cell value register"]
30931 #[repr(transparent)]
30932 #[derive(Copy, Clone, Eq, PartialEq)]
30933 pub struct Ccvr(pub u32);
30934 impl Ccvr {
30935 #[doc = "NMOS compensation value"]
30936 pub const fn ncv(&self) -> u8 {
30937 let val = (self.0 >> 0usize) & 0x0f;
30938 val as u8
30939 }
30940 #[doc = "NMOS compensation value"]
30941 pub fn set_ncv(&mut self, val: u8) {
30942 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
30943 }
30944 #[doc = "PMOS compensation value"]
30945 pub const fn pcv(&self) -> u8 {
30946 let val = (self.0 >> 4usize) & 0x0f;
30947 val as u8
30948 }
30949 #[doc = "PMOS compensation value"]
30950 pub fn set_pcv(&mut self, val: u8) {
30951 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
30952 }
30953 }
30954 impl Default for Ccvr {
30955 fn default() -> Ccvr {
30956 Ccvr(0)
30957 }
30958 }
30959 #[doc = "SYSCFG user register 7"]
30960 #[repr(transparent)]
30961 #[derive(Copy, Clone, Eq, PartialEq)]
30962 pub struct Ur7(pub u32);
30963 impl Ur7 {
30964 #[doc = "Secured area start address for bank 1"]
30965 pub const fn sa_beg_1(&self) -> u16 {
30966 let val = (self.0 >> 0usize) & 0x0fff;
30967 val as u16
30968 }
30969 #[doc = "Secured area start address for bank 1"]
30970 pub fn set_sa_beg_1(&mut self, val: u16) {
30971 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
30972 }
30973 #[doc = "Secured area end address for bank 1"]
30974 pub const fn sa_end_1(&self) -> u16 {
30975 let val = (self.0 >> 16usize) & 0x0fff;
30976 val as u16
30977 }
30978 #[doc = "Secured area end address for bank 1"]
30979 pub fn set_sa_end_1(&mut self, val: u16) {
30980 self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
30981 }
30982 }
30983 impl Default for Ur7 {
30984 fn default() -> Ur7 {
30985 Ur7(0)
30986 }
30987 }
30988 #[doc = "SYSCFG user register 12"]
30989 #[repr(transparent)]
30990 #[derive(Copy, Clone, Eq, PartialEq)]
30991 pub struct Ur12(pub u32);
30992 impl Ur12 {
30993 #[doc = "Secure mode"]
30994 pub const fn secure(&self) -> bool {
30995 let val = (self.0 >> 16usize) & 0x01;
30996 val != 0
30997 }
30998 #[doc = "Secure mode"]
30999 pub fn set_secure(&mut self, val: bool) {
31000 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
31001 }
31002 }
31003 impl Default for Ur12 {
31004 fn default() -> Ur12 {
31005 Ur12(0)
31006 }
31007 }
31008 #[doc = "SYSCFG user register 6"]
31009 #[repr(transparent)]
31010 #[derive(Copy, Clone, Eq, PartialEq)]
31011 pub struct Ur6(pub u32);
31012 impl Ur6 {
31013 #[doc = "Protected area start address for bank 1"]
31014 pub const fn pa_beg_1(&self) -> u16 {
31015 let val = (self.0 >> 0usize) & 0x0fff;
31016 val as u16
31017 }
31018 #[doc = "Protected area start address for bank 1"]
31019 pub fn set_pa_beg_1(&mut self, val: u16) {
31020 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
31021 }
31022 #[doc = "Protected area end address for bank 1"]
31023 pub const fn pa_end_1(&self) -> u16 {
31024 let val = (self.0 >> 16usize) & 0x0fff;
31025 val as u16
31026 }
31027 #[doc = "Protected area end address for bank 1"]
31028 pub fn set_pa_end_1(&mut self, val: u16) {
31029 self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize);
31030 }
31031 }
31032 impl Default for Ur6 {
31033 fn default() -> Ur6 {
31034 Ur6(0)
31035 }
31036 }
31037 #[doc = "peripheral mode configuration register"]
31038 #[repr(transparent)]
31039 #[derive(Copy, Clone, Eq, PartialEq)]
31040 pub struct Pmcr(pub u32);
31041 impl Pmcr {
31042 #[doc = "I2C1 Fm+"]
31043 pub const fn i2c1fmp(&self) -> bool {
31044 let val = (self.0 >> 0usize) & 0x01;
31045 val != 0
31046 }
31047 #[doc = "I2C1 Fm+"]
31048 pub fn set_i2c1fmp(&mut self, val: bool) {
31049 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
31050 }
31051 #[doc = "I2C2 Fm+"]
31052 pub const fn i2c2fmp(&self) -> bool {
31053 let val = (self.0 >> 1usize) & 0x01;
31054 val != 0
31055 }
31056 #[doc = "I2C2 Fm+"]
31057 pub fn set_i2c2fmp(&mut self, val: bool) {
31058 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
31059 }
31060 #[doc = "I2C3 Fm+"]
31061 pub const fn i2c3fmp(&self) -> bool {
31062 let val = (self.0 >> 2usize) & 0x01;
31063 val != 0
31064 }
31065 #[doc = "I2C3 Fm+"]
31066 pub fn set_i2c3fmp(&mut self, val: bool) {
31067 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
31068 }
31069 #[doc = "I2C4 Fm+"]
31070 pub const fn i2c4fmp(&self) -> bool {
31071 let val = (self.0 >> 3usize) & 0x01;
31072 val != 0
31073 }
31074 #[doc = "I2C4 Fm+"]
31075 pub fn set_i2c4fmp(&mut self, val: bool) {
31076 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
31077 }
31078 #[doc = "PB(6) Fm+"]
31079 pub const fn pb6fmp(&self) -> bool {
31080 let val = (self.0 >> 4usize) & 0x01;
31081 val != 0
31082 }
31083 #[doc = "PB(6) Fm+"]
31084 pub fn set_pb6fmp(&mut self, val: bool) {
31085 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
31086 }
31087 #[doc = "PB(7) Fast Mode Plus"]
31088 pub const fn pb7fmp(&self) -> bool {
31089 let val = (self.0 >> 5usize) & 0x01;
31090 val != 0
31091 }
31092 #[doc = "PB(7) Fast Mode Plus"]
31093 pub fn set_pb7fmp(&mut self, val: bool) {
31094 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
31095 }
31096 #[doc = "PB(8) Fast Mode Plus"]
31097 pub const fn pb8fmp(&self) -> bool {
31098 let val = (self.0 >> 6usize) & 0x01;
31099 val != 0
31100 }
31101 #[doc = "PB(8) Fast Mode Plus"]
31102 pub fn set_pb8fmp(&mut self, val: bool) {
31103 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
31104 }
31105 #[doc = "PB(9) Fm+"]
31106 pub const fn pb9fmp(&self) -> bool {
31107 let val = (self.0 >> 7usize) & 0x01;
31108 val != 0
31109 }
31110 #[doc = "PB(9) Fm+"]
31111 pub fn set_pb9fmp(&mut self, val: bool) {
31112 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
31113 }
31114 #[doc = "Booster Enable"]
31115 pub const fn booste(&self) -> bool {
31116 let val = (self.0 >> 8usize) & 0x01;
31117 val != 0
31118 }
31119 #[doc = "Booster Enable"]
31120 pub fn set_booste(&mut self, val: bool) {
31121 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
31122 }
31123 #[doc = "Analog switch supply voltage selection"]
31124 pub const fn boostvddsel(&self) -> bool {
31125 let val = (self.0 >> 9usize) & 0x01;
31126 val != 0
31127 }
31128 #[doc = "Analog switch supply voltage selection"]
31129 pub fn set_boostvddsel(&mut self, val: bool) {
31130 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
31131 }
31132 #[doc = "Ethernet PHY Interface Selection"]
31133 pub const fn epis(&self) -> u8 {
31134 let val = (self.0 >> 21usize) & 0x07;
31135 val as u8
31136 }
31137 #[doc = "Ethernet PHY Interface Selection"]
31138 pub fn set_epis(&mut self, val: u8) {
31139 self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize);
31140 }
31141 #[doc = "PA0 Switch Open"]
31142 pub const fn pa0so(&self) -> bool {
31143 let val = (self.0 >> 24usize) & 0x01;
31144 val != 0
31145 }
31146 #[doc = "PA0 Switch Open"]
31147 pub fn set_pa0so(&mut self, val: bool) {
31148 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
31149 }
31150 #[doc = "PA1 Switch Open"]
31151 pub const fn pa1so(&self) -> bool {
31152 let val = (self.0 >> 25usize) & 0x01;
31153 val != 0
31154 }
31155 #[doc = "PA1 Switch Open"]
31156 pub fn set_pa1so(&mut self, val: bool) {
31157 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
31158 }
31159 #[doc = "PC2 Switch Open"]
31160 pub const fn pc2so(&self) -> bool {
31161 let val = (self.0 >> 26usize) & 0x01;
31162 val != 0
31163 }
31164 #[doc = "PC2 Switch Open"]
31165 pub fn set_pc2so(&mut self, val: bool) {
31166 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
31167 }
31168 #[doc = "PC3 Switch Open"]
31169 pub const fn pc3so(&self) -> bool {
31170 let val = (self.0 >> 27usize) & 0x01;
31171 val != 0
31172 }
31173 #[doc = "PC3 Switch Open"]
31174 pub fn set_pc3so(&mut self, val: bool) {
31175 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
31176 }
31177 }
31178 impl Default for Pmcr {
31179 fn default() -> Pmcr {
31180 Pmcr(0)
31181 }
31182 }
31183 #[doc = "SYSCFG user register 15"]
31184 #[repr(transparent)]
31185 #[derive(Copy, Clone, Eq, PartialEq)]
31186 pub struct Ur15(pub u32);
31187 impl Ur15 {
31188 #[doc = "Freeze independent watchdog in Standby mode"]
31189 pub const fn fziwdgstb(&self) -> bool {
31190 let val = (self.0 >> 16usize) & 0x01;
31191 val != 0
31192 }
31193 #[doc = "Freeze independent watchdog in Standby mode"]
31194 pub fn set_fziwdgstb(&mut self, val: bool) {
31195 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
31196 }
31197 }
31198 impl Default for Ur15 {
31199 fn default() -> Ur15 {
31200 Ur15(0)
31201>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
31202 }
31203 }
31204 #[doc = "SYSCFG user register 3"]
31205 #[repr(transparent)]
31206 #[derive(Copy, Clone, Eq, PartialEq)]
31207 pub struct Ur3(pub u32);
31208 impl Ur3 {
31209 #[doc = "Boot Address 1"]
31210 pub const fn boot_add1(&self) -> u16 {
31211 let val = (self.0 >> 16usize) & 0xffff;
31212 val as u16
31213 }
31214 #[doc = "Boot Address 1"]
31215 pub fn set_boot_add1(&mut self, val: u16) {
31216 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
31217 }
31218 }
31219 impl Default for Ur3 {
31220 fn default() -> Ur3 {
31221 Ur3(0)
31222 }
31223 }
31224<<<<<<< HEAD
14715 #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] 31225 #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."]
14716 #[repr(transparent)] 31226 #[repr(transparent)]
14717 #[derive(Copy, Clone, Eq, PartialEq)] 31227 #[derive(Copy, Clone, Eq, PartialEq)]
@@ -14773,31 +31283,58 @@ are always 0 and read only). This register can be written by firmware when DPSM
14773 impl Default for Id { 31283 impl Default for Id {
14774 fn default() -> Id { 31284 fn default() -> Id {
14775 Id(0) 31285 Id(0)
31286=======
31287 #[doc = "SYSCFG user register 0"]
31288 #[repr(transparent)]
31289 #[derive(Copy, Clone, Eq, PartialEq)]
31290 pub struct Ur0(pub u32);
31291 impl Ur0 {
31292 #[doc = "Bank Swap"]
31293 pub const fn bks(&self) -> bool {
31294 let val = (self.0 >> 0usize) & 0x01;
31295 val != 0
31296 }
31297 #[doc = "Bank Swap"]
31298 pub fn set_bks(&mut self, val: bool) {
31299 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
31300 }
31301 #[doc = "Readout protection"]
31302 pub const fn rdp(&self) -> u8 {
31303 let val = (self.0 >> 16usize) & 0xff;
31304 val as u8
31305 }
31306 #[doc = "Readout protection"]
31307 pub fn set_rdp(&mut self, val: u8) {
31308 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
14776 } 31309 }
14777 } 31310 }
14778 #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] 31311 impl Default for Ur0 {
31312 fn default() -> Ur0 {
31313 Ur0(0)
31314>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
31315 }
31316 }
31317 #[doc = "SYSCFG package register"]
14779 #[repr(transparent)] 31318 #[repr(transparent)]
14780 #[derive(Copy, Clone, Eq, PartialEq)] 31319 #[derive(Copy, Clone, Eq, PartialEq)]
14781 pub struct Idmabase0r(pub u32); 31320 pub struct Pkgr(pub u32);
14782 impl Idmabase0r { 31321 impl Pkgr {
14783 #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] 31322 #[doc = "Package"]
14784are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] 31323 pub const fn pkg(&self) -> u8 {
14785 pub const fn idmabase0(&self) -> u32 { 31324 let val = (self.0 >> 0usize) & 0x0f;
14786 let val = (self.0 >> 0usize) & 0xffff_ffff; 31325 val as u8
14787 val as u32
14788 } 31326 }
14789 #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] 31327 #[doc = "Package"]
14790are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] 31328 pub fn set_pkg(&mut self, val: u8) {
14791 pub fn set_idmabase0(&mut self, val: u32) { 31329 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
14792 self.0 =
14793 (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
14794 } 31330 }
14795 } 31331 }
14796 impl Default for Idmabase0r { 31332 impl Default for Pkgr {
14797 fn default() -> Idmabase0r { 31333 fn default() -> Pkgr {
14798 Idmabase0r(0) 31334 Pkgr(0)
14799 } 31335 }
14800 } 31336 }
31337<<<<<<< HEAD
14801 } 31338 }
14802} 31339}
14803pub mod gpio_v1 { 31340pub mod gpio_v1 {
@@ -15430,6 +31967,686 @@ pub mod syscfg_l4 {
15430 impl Default for Memrmp { 31967 impl Default for Memrmp {
15431 fn default() -> Memrmp { 31968 fn default() -> Memrmp {
15432 Memrmp(0) 31969 Memrmp(0)
31970=======
31971 #[doc = "SYSCFG user register 8"]
31972 #[repr(transparent)]
31973 #[derive(Copy, Clone, Eq, PartialEq)]
31974 pub struct Ur8(pub u32);
31975 impl Ur8 {
31976 #[doc = "Mass erase protected area disabled for bank 2"]
31977 pub const fn mepad_2(&self) -> bool {
31978 let val = (self.0 >> 0usize) & 0x01;
31979 val != 0
31980 }
31981 #[doc = "Mass erase protected area disabled for bank 2"]
31982 pub fn set_mepad_2(&mut self, val: bool) {
31983 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
31984 }
31985 #[doc = "Mass erase secured area disabled for bank 2"]
31986 pub const fn mesad_2(&self) -> bool {
31987 let val = (self.0 >> 16usize) & 0x01;
31988 val != 0
31989 }
31990 #[doc = "Mass erase secured area disabled for bank 2"]
31991 pub fn set_mesad_2(&mut self, val: bool) {
31992 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
31993 }
31994 }
31995 impl Default for Ur8 {
31996 fn default() -> Ur8 {
31997 Ur8(0)
31998 }
31999 }
32000 #[doc = "SYSCFG user register 17"]
32001 #[repr(transparent)]
32002 #[derive(Copy, Clone, Eq, PartialEq)]
32003 pub struct Ur17(pub u32);
32004 impl Ur17 {
32005 #[doc = "I/O high speed / low voltage"]
32006 pub const fn io_hslv(&self) -> bool {
32007 let val = (self.0 >> 0usize) & 0x01;
32008 val != 0
32009 }
32010 #[doc = "I/O high speed / low voltage"]
32011 pub fn set_io_hslv(&mut self, val: bool) {
32012 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
32013 }
32014 }
32015 impl Default for Ur17 {
32016 fn default() -> Ur17 {
32017 Ur17(0)
32018 }
32019 }
32020 #[doc = "SYSCFG user register 4"]
32021 #[repr(transparent)]
32022 #[derive(Copy, Clone, Eq, PartialEq)]
32023 pub struct Ur4(pub u32);
32024 impl Ur4 {
32025 #[doc = "Mass Erase Protected Area Disabled for bank 1"]
32026 pub const fn mepad_1(&self) -> bool {
32027 let val = (self.0 >> 16usize) & 0x01;
32028 val != 0
32029 }
32030 #[doc = "Mass Erase Protected Area Disabled for bank 1"]
32031 pub fn set_mepad_1(&mut self, val: bool) {
32032 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
32033 }
32034 }
32035 impl Default for Ur4 {
32036 fn default() -> Ur4 {
32037 Ur4(0)
32038 }
32039 }
32040 #[doc = "external interrupt configuration register 2"]
32041 #[repr(transparent)]
32042 #[derive(Copy, Clone, Eq, PartialEq)]
32043 pub struct Exticr(pub u32);
32044 impl Exticr {
32045 #[doc = "EXTI x configuration (x = 4 to 7)"]
32046 pub fn exti(&self, n: usize) -> u8 {
32047 assert!(n < 4usize);
32048 let offs = 0usize + n * 4usize;
32049 let val = (self.0 >> offs) & 0x0f;
32050 val as u8
32051 }
32052 #[doc = "EXTI x configuration (x = 4 to 7)"]
32053 pub fn set_exti(&mut self, n: usize, val: u8) {
32054 assert!(n < 4usize);
32055 let offs = 0usize + n * 4usize;
32056 self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
32057 }
32058 }
32059 impl Default for Exticr {
32060 fn default() -> Exticr {
32061 Exticr(0)
32062 }
32063 }
32064 #[doc = "compensation cell control/status register"]
32065 #[repr(transparent)]
32066 #[derive(Copy, Clone, Eq, PartialEq)]
32067 pub struct Cccsr(pub u32);
32068 impl Cccsr {
32069 #[doc = "enable"]
32070 pub const fn en(&self) -> bool {
32071 let val = (self.0 >> 0usize) & 0x01;
32072 val != 0
32073 }
32074 #[doc = "enable"]
32075 pub fn set_en(&mut self, val: bool) {
32076 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
32077 }
32078 #[doc = "Code selection"]
32079 pub const fn cs(&self) -> bool {
32080 let val = (self.0 >> 1usize) & 0x01;
32081 val != 0
32082 }
32083 #[doc = "Code selection"]
32084 pub fn set_cs(&mut self, val: bool) {
32085 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
32086 }
32087 #[doc = "Compensation cell ready flag"]
32088 pub const fn ready(&self) -> bool {
32089 let val = (self.0 >> 8usize) & 0x01;
32090 val != 0
32091 }
32092 #[doc = "Compensation cell ready flag"]
32093 pub fn set_ready(&mut self, val: bool) {
32094 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
32095 }
32096 #[doc = "High-speed at low-voltage"]
32097 pub const fn hslv(&self) -> bool {
32098 let val = (self.0 >> 16usize) & 0x01;
32099 val != 0
32100 }
32101 #[doc = "High-speed at low-voltage"]
32102 pub fn set_hslv(&mut self, val: bool) {
32103 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
32104 }
32105 }
32106 impl Default for Cccsr {
32107 fn default() -> Cccsr {
32108 Cccsr(0)
32109 }
32110 }
32111 #[doc = "SYSCFG user register 13"]
32112 #[repr(transparent)]
32113 #[derive(Copy, Clone, Eq, PartialEq)]
32114 pub struct Ur13(pub u32);
32115 impl Ur13 {
32116 #[doc = "Secured DTCM RAM Size"]
32117 pub const fn sdrs(&self) -> u8 {
32118 let val = (self.0 >> 0usize) & 0x03;
32119 val as u8
32120 }
32121 #[doc = "Secured DTCM RAM Size"]
32122 pub fn set_sdrs(&mut self, val: u8) {
32123 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
32124 }
32125 #[doc = "D1 Standby reset"]
32126 pub const fn d1sbrst(&self) -> bool {
32127 let val = (self.0 >> 16usize) & 0x01;
32128 val != 0
32129 }
32130 #[doc = "D1 Standby reset"]
32131 pub fn set_d1sbrst(&mut self, val: bool) {
32132 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
32133 }
32134 }
32135 impl Default for Ur13 {
32136 fn default() -> Ur13 {
32137 Ur13(0)
32138 }
32139 }
32140 #[doc = "SYSCFG user register 2"]
32141 #[repr(transparent)]
32142 #[derive(Copy, Clone, Eq, PartialEq)]
32143 pub struct Ur2(pub u32);
32144 impl Ur2 {
32145 #[doc = "BOR_LVL Brownout Reset Threshold Level"]
32146 pub const fn borh(&self) -> u8 {
32147 let val = (self.0 >> 0usize) & 0x03;
32148 val as u8
32149 }
32150 #[doc = "BOR_LVL Brownout Reset Threshold Level"]
32151 pub fn set_borh(&mut self, val: u8) {
32152 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
32153 }
32154 #[doc = "Boot Address 0"]
32155 pub const fn boot_add0(&self) -> u16 {
32156 let val = (self.0 >> 16usize) & 0xffff;
32157 val as u16
32158 }
32159 #[doc = "Boot Address 0"]
32160 pub fn set_boot_add0(&mut self, val: u16) {
32161 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
32162 }
32163 }
32164 impl Default for Ur2 {
32165 fn default() -> Ur2 {
32166 Ur2(0)
32167 }
32168 }
32169 #[doc = "SYSCFG user register 16"]
32170 #[repr(transparent)]
32171 #[derive(Copy, Clone, Eq, PartialEq)]
32172 pub struct Ur16(pub u32);
32173 impl Ur16 {
32174 #[doc = "Freeze independent watchdog in Stop mode"]
32175 pub const fn fziwdgstp(&self) -> bool {
32176 let val = (self.0 >> 0usize) & 0x01;
32177 val != 0
32178 }
32179 #[doc = "Freeze independent watchdog in Stop mode"]
32180 pub fn set_fziwdgstp(&mut self, val: bool) {
32181 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
32182 }
32183 #[doc = "Private key programmed"]
32184 pub const fn pkp(&self) -> bool {
32185 let val = (self.0 >> 16usize) & 0x01;
32186 val != 0
32187 }
32188 #[doc = "Private key programmed"]
32189 pub fn set_pkp(&mut self, val: bool) {
32190 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
32191 }
32192 }
32193 impl Default for Ur16 {
32194 fn default() -> Ur16 {
32195 Ur16(0)
32196 }
32197 }
32198 #[doc = "SYSCFG compensation cell code register"]
32199 #[repr(transparent)]
32200 #[derive(Copy, Clone, Eq, PartialEq)]
32201 pub struct Cccr(pub u32);
32202 impl Cccr {
32203 #[doc = "NMOS compensation code"]
32204 pub const fn ncc(&self) -> u8 {
32205 let val = (self.0 >> 0usize) & 0x0f;
32206 val as u8
32207 }
32208 #[doc = "NMOS compensation code"]
32209 pub fn set_ncc(&mut self, val: u8) {
32210 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
32211 }
32212 #[doc = "PMOS compensation code"]
32213 pub const fn pcc(&self) -> u8 {
32214 let val = (self.0 >> 4usize) & 0x0f;
32215 val as u8
32216 }
32217 #[doc = "PMOS compensation code"]
32218 pub fn set_pcc(&mut self, val: u8) {
32219 self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize);
32220 }
32221 }
32222 impl Default for Cccr {
32223 fn default() -> Cccr {
32224 Cccr(0)
32225 }
32226 }
32227 }
32228}
32229pub mod gpio_v2 {
32230 use crate::generic::*;
32231 #[doc = "General-purpose I/Os"]
32232 #[derive(Copy, Clone)]
32233 pub struct Gpio(pub *mut u8);
32234 unsafe impl Send for Gpio {}
32235 unsafe impl Sync for Gpio {}
32236 impl Gpio {
32237 #[doc = "GPIO port mode register"]
32238 pub fn moder(self) -> Reg<regs::Moder, RW> {
32239 unsafe { Reg::from_ptr(self.0.add(0usize)) }
32240 }
32241 #[doc = "GPIO port output type register"]
32242 pub fn otyper(self) -> Reg<regs::Otyper, RW> {
32243 unsafe { Reg::from_ptr(self.0.add(4usize)) }
32244 }
32245 #[doc = "GPIO port output speed register"]
32246 pub fn ospeedr(self) -> Reg<regs::Ospeedr, RW> {
32247 unsafe { Reg::from_ptr(self.0.add(8usize)) }
32248 }
32249 #[doc = "GPIO port pull-up/pull-down register"]
32250 pub fn pupdr(self) -> Reg<regs::Pupdr, RW> {
32251 unsafe { Reg::from_ptr(self.0.add(12usize)) }
32252 }
32253 #[doc = "GPIO port input data register"]
32254 pub fn idr(self) -> Reg<regs::Idr, R> {
32255 unsafe { Reg::from_ptr(self.0.add(16usize)) }
32256 }
32257 #[doc = "GPIO port output data register"]
32258 pub fn odr(self) -> Reg<regs::Odr, RW> {
32259 unsafe { Reg::from_ptr(self.0.add(20usize)) }
32260 }
32261 #[doc = "GPIO port bit set/reset register"]
32262 pub fn bsrr(self) -> Reg<regs::Bsrr, W> {
32263 unsafe { Reg::from_ptr(self.0.add(24usize)) }
32264 }
32265 #[doc = "GPIO port configuration lock register"]
32266 pub fn lckr(self) -> Reg<regs::Lckr, RW> {
32267 unsafe { Reg::from_ptr(self.0.add(28usize)) }
32268 }
32269 #[doc = "GPIO alternate function register (low, high)"]
32270 pub fn afr(self, n: usize) -> Reg<regs::Afr, RW> {
32271 assert!(n < 2usize);
32272 unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) }
32273 }
32274 }
32275 pub mod vals {
32276 use crate::generic::*;
32277 #[repr(transparent)]
32278 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32279 pub struct Idr(pub u8);
32280 impl Idr {
32281 #[doc = "Input is logic low"]
32282 pub const LOW: Self = Self(0);
32283 #[doc = "Input is logic high"]
32284 pub const HIGH: Self = Self(0x01);
32285 }
32286 #[repr(transparent)]
32287 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32288 pub struct Ospeedr(pub u8);
32289 impl Ospeedr {
32290 #[doc = "Low speed"]
32291 pub const LOWSPEED: Self = Self(0);
32292 #[doc = "Medium speed"]
32293 pub const MEDIUMSPEED: Self = Self(0x01);
32294 #[doc = "High speed"]
32295 pub const HIGHSPEED: Self = Self(0x02);
32296 #[doc = "Very high speed"]
32297 pub const VERYHIGHSPEED: Self = Self(0x03);
32298 }
32299 #[repr(transparent)]
32300 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32301 pub struct Moder(pub u8);
32302 impl Moder {
32303 #[doc = "Input mode (reset state)"]
32304 pub const INPUT: Self = Self(0);
32305 #[doc = "General purpose output mode"]
32306 pub const OUTPUT: Self = Self(0x01);
32307 #[doc = "Alternate function mode"]
32308 pub const ALTERNATE: Self = Self(0x02);
32309 #[doc = "Analog mode"]
32310 pub const ANALOG: Self = Self(0x03);
32311 }
32312 #[repr(transparent)]
32313 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32314 pub struct Lckk(pub u8);
32315 impl Lckk {
32316 #[doc = "Port configuration lock key not active"]
32317 pub const NOTACTIVE: Self = Self(0);
32318 #[doc = "Port configuration lock key active"]
32319 pub const ACTIVE: Self = Self(0x01);
32320 }
32321 #[repr(transparent)]
32322 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32323 pub struct Bsw(pub u8);
32324 impl Bsw {
32325 #[doc = "Sets the corresponding ODRx bit"]
32326 pub const SET: Self = Self(0x01);
32327 }
32328 #[repr(transparent)]
32329 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32330 pub struct Brw(pub u8);
32331 impl Brw {
32332 #[doc = "Resets the corresponding ODRx bit"]
32333 pub const RESET: Self = Self(0x01);
32334 }
32335 #[repr(transparent)]
32336 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32337 pub struct Lck(pub u8);
32338 impl Lck {
32339 #[doc = "Port configuration not locked"]
32340 pub const UNLOCKED: Self = Self(0);
32341 #[doc = "Port configuration locked"]
32342 pub const LOCKED: Self = Self(0x01);
32343 }
32344 #[repr(transparent)]
32345 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32346 pub struct Afr(pub u8);
32347 impl Afr {
32348 #[doc = "AF0"]
32349 pub const AF0: Self = Self(0);
32350 #[doc = "AF1"]
32351 pub const AF1: Self = Self(0x01);
32352 #[doc = "AF2"]
32353 pub const AF2: Self = Self(0x02);
32354 #[doc = "AF3"]
32355 pub const AF3: Self = Self(0x03);
32356 #[doc = "AF4"]
32357 pub const AF4: Self = Self(0x04);
32358 #[doc = "AF5"]
32359 pub const AF5: Self = Self(0x05);
32360 #[doc = "AF6"]
32361 pub const AF6: Self = Self(0x06);
32362 #[doc = "AF7"]
32363 pub const AF7: Self = Self(0x07);
32364 #[doc = "AF8"]
32365 pub const AF8: Self = Self(0x08);
32366 #[doc = "AF9"]
32367 pub const AF9: Self = Self(0x09);
32368 #[doc = "AF10"]
32369 pub const AF10: Self = Self(0x0a);
32370 #[doc = "AF11"]
32371 pub const AF11: Self = Self(0x0b);
32372 #[doc = "AF12"]
32373 pub const AF12: Self = Self(0x0c);
32374 #[doc = "AF13"]
32375 pub const AF13: Self = Self(0x0d);
32376 #[doc = "AF14"]
32377 pub const AF14: Self = Self(0x0e);
32378 #[doc = "AF15"]
32379 pub const AF15: Self = Self(0x0f);
32380 }
32381 #[repr(transparent)]
32382 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32383 pub struct Ot(pub u8);
32384 impl Ot {
32385 #[doc = "Output push-pull (reset state)"]
32386 pub const PUSHPULL: Self = Self(0);
32387 #[doc = "Output open-drain"]
32388 pub const OPENDRAIN: Self = Self(0x01);
32389 }
32390 #[repr(transparent)]
32391 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32392 pub struct Odr(pub u8);
32393 impl Odr {
32394 #[doc = "Set output to logic low"]
32395 pub const LOW: Self = Self(0);
32396 #[doc = "Set output to logic high"]
32397 pub const HIGH: Self = Self(0x01);
32398 }
32399 #[repr(transparent)]
32400 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
32401 pub struct Pupdr(pub u8);
32402 impl Pupdr {
32403 #[doc = "No pull-up, pull-down"]
32404 pub const FLOATING: Self = Self(0);
32405 #[doc = "Pull-up"]
32406 pub const PULLUP: Self = Self(0x01);
32407 #[doc = "Pull-down"]
32408 pub const PULLDOWN: Self = Self(0x02);
32409 }
32410 }
32411 pub mod regs {
32412 use crate::generic::*;
32413 #[doc = "GPIO alternate function register"]
32414 #[repr(transparent)]
32415 #[derive(Copy, Clone, Eq, PartialEq)]
32416 pub struct Afr(pub u32);
32417 impl Afr {
32418 #[doc = "Alternate function selection for port x bit y (y = 0..15)"]
32419 pub fn afr(&self, n: usize) -> super::vals::Afr {
32420 assert!(n < 8usize);
32421 let offs = 0usize + n * 4usize;
32422 let val = (self.0 >> offs) & 0x0f;
32423 super::vals::Afr(val as u8)
32424 }
32425 #[doc = "Alternate function selection for port x bit y (y = 0..15)"]
32426 pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) {
32427 assert!(n < 8usize);
32428 let offs = 0usize + n * 4usize;
32429 self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs);
32430 }
32431 }
32432 impl Default for Afr {
32433 fn default() -> Afr {
32434 Afr(0)
32435 }
32436 }
32437 #[doc = "GPIO port output speed register"]
32438 #[repr(transparent)]
32439 #[derive(Copy, Clone, Eq, PartialEq)]
32440 pub struct Ospeedr(pub u32);
32441 impl Ospeedr {
32442 #[doc = "Port x configuration bits (y = 0..15)"]
32443 pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr {
32444 assert!(n < 16usize);
32445 let offs = 0usize + n * 2usize;
32446 let val = (self.0 >> offs) & 0x03;
32447 super::vals::Ospeedr(val as u8)
32448 }
32449 #[doc = "Port x configuration bits (y = 0..15)"]
32450 pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) {
32451 assert!(n < 16usize);
32452 let offs = 0usize + n * 2usize;
32453 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
32454 }
32455 }
32456 impl Default for Ospeedr {
32457 fn default() -> Ospeedr {
32458 Ospeedr(0)
32459 }
32460 }
32461 #[doc = "GPIO port output data register"]
32462 #[repr(transparent)]
32463 #[derive(Copy, Clone, Eq, PartialEq)]
32464 pub struct Odr(pub u32);
32465 impl Odr {
32466 #[doc = "Port output data (y = 0..15)"]
32467 pub fn odr(&self, n: usize) -> super::vals::Odr {
32468 assert!(n < 16usize);
32469 let offs = 0usize + n * 1usize;
32470 let val = (self.0 >> offs) & 0x01;
32471 super::vals::Odr(val as u8)
32472 }
32473 #[doc = "Port output data (y = 0..15)"]
32474 pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) {
32475 assert!(n < 16usize);
32476 let offs = 0usize + n * 1usize;
32477 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
32478 }
32479 }
32480 impl Default for Odr {
32481 fn default() -> Odr {
32482 Odr(0)
32483 }
32484 }
32485 #[doc = "GPIO port bit set/reset register"]
32486 #[repr(transparent)]
32487 #[derive(Copy, Clone, Eq, PartialEq)]
32488 pub struct Bsrr(pub u32);
32489 impl Bsrr {
32490 #[doc = "Port x set bit y (y= 0..15)"]
32491 pub fn bs(&self, n: usize) -> bool {
32492 assert!(n < 16usize);
32493 let offs = 0usize + n * 1usize;
32494 let val = (self.0 >> offs) & 0x01;
32495 val != 0
32496 }
32497 #[doc = "Port x set bit y (y= 0..15)"]
32498 pub fn set_bs(&mut self, n: usize, val: bool) {
32499 assert!(n < 16usize);
32500 let offs = 0usize + n * 1usize;
32501 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
32502 }
32503 #[doc = "Port x set bit y (y= 0..15)"]
32504 pub fn br(&self, n: usize) -> bool {
32505 assert!(n < 16usize);
32506 let offs = 16usize + n * 1usize;
32507 let val = (self.0 >> offs) & 0x01;
32508 val != 0
32509 }
32510 #[doc = "Port x set bit y (y= 0..15)"]
32511 pub fn set_br(&mut self, n: usize, val: bool) {
32512 assert!(n < 16usize);
32513 let offs = 16usize + n * 1usize;
32514 self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
32515 }
32516 }
32517 impl Default for Bsrr {
32518 fn default() -> Bsrr {
32519 Bsrr(0)
32520 }
32521 }
32522 #[doc = "GPIO port output type register"]
32523 #[repr(transparent)]
32524 #[derive(Copy, Clone, Eq, PartialEq)]
32525 pub struct Otyper(pub u32);
32526 impl Otyper {
32527 #[doc = "Port x configuration bits (y = 0..15)"]
32528 pub fn ot(&self, n: usize) -> super::vals::Ot {
32529 assert!(n < 16usize);
32530 let offs = 0usize + n * 1usize;
32531 let val = (self.0 >> offs) & 0x01;
32532 super::vals::Ot(val as u8)
32533 }
32534 #[doc = "Port x configuration bits (y = 0..15)"]
32535 pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) {
32536 assert!(n < 16usize);
32537 let offs = 0usize + n * 1usize;
32538 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
32539 }
32540 }
32541 impl Default for Otyper {
32542 fn default() -> Otyper {
32543 Otyper(0)
32544 }
32545 }
32546 #[doc = "GPIO port configuration lock register"]
32547 #[repr(transparent)]
32548 #[derive(Copy, Clone, Eq, PartialEq)]
32549 pub struct Lckr(pub u32);
32550 impl Lckr {
32551 #[doc = "Port x lock bit y (y= 0..15)"]
32552 pub fn lck(&self, n: usize) -> super::vals::Lck {
32553 assert!(n < 16usize);
32554 let offs = 0usize + n * 1usize;
32555 let val = (self.0 >> offs) & 0x01;
32556 super::vals::Lck(val as u8)
32557 }
32558 #[doc = "Port x lock bit y (y= 0..15)"]
32559 pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) {
32560 assert!(n < 16usize);
32561 let offs = 0usize + n * 1usize;
32562 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
32563 }
32564 #[doc = "Port x lock bit y (y= 0..15)"]
32565 pub const fn lckk(&self) -> super::vals::Lckk {
32566 let val = (self.0 >> 16usize) & 0x01;
32567 super::vals::Lckk(val as u8)
32568 }
32569 #[doc = "Port x lock bit y (y= 0..15)"]
32570 pub fn set_lckk(&mut self, val: super::vals::Lckk) {
32571 self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize);
32572 }
32573 }
32574 impl Default for Lckr {
32575 fn default() -> Lckr {
32576 Lckr(0)
32577 }
32578 }
32579 #[doc = "GPIO port pull-up/pull-down register"]
32580 #[repr(transparent)]
32581 #[derive(Copy, Clone, Eq, PartialEq)]
32582 pub struct Pupdr(pub u32);
32583 impl Pupdr {
32584 #[doc = "Port x configuration bits (y = 0..15)"]
32585 pub fn pupdr(&self, n: usize) -> super::vals::Pupdr {
32586 assert!(n < 16usize);
32587 let offs = 0usize + n * 2usize;
32588 let val = (self.0 >> offs) & 0x03;
32589 super::vals::Pupdr(val as u8)
32590 }
32591 #[doc = "Port x configuration bits (y = 0..15)"]
32592 pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) {
32593 assert!(n < 16usize);
32594 let offs = 0usize + n * 2usize;
32595 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
32596 }
32597 }
32598 impl Default for Pupdr {
32599 fn default() -> Pupdr {
32600 Pupdr(0)
32601 }
32602 }
32603 #[doc = "GPIO port mode register"]
32604 #[repr(transparent)]
32605 #[derive(Copy, Clone, Eq, PartialEq)]
32606 pub struct Moder(pub u32);
32607 impl Moder {
32608 #[doc = "Port x configuration bits (y = 0..15)"]
32609 pub fn moder(&self, n: usize) -> super::vals::Moder {
32610 assert!(n < 16usize);
32611 let offs = 0usize + n * 2usize;
32612 let val = (self.0 >> offs) & 0x03;
32613 super::vals::Moder(val as u8)
32614 }
32615 #[doc = "Port x configuration bits (y = 0..15)"]
32616 pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) {
32617 assert!(n < 16usize);
32618 let offs = 0usize + n * 2usize;
32619 self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs);
32620 }
32621 }
32622 impl Default for Moder {
32623 fn default() -> Moder {
32624 Moder(0)
32625 }
32626 }
32627 #[doc = "GPIO port input data register"]
32628 #[repr(transparent)]
32629 #[derive(Copy, Clone, Eq, PartialEq)]
32630 pub struct Idr(pub u32);
32631 impl Idr {
32632 #[doc = "Port input data (y = 0..15)"]
32633 pub fn idr(&self, n: usize) -> super::vals::Idr {
32634 assert!(n < 16usize);
32635 let offs = 0usize + n * 1usize;
32636 let val = (self.0 >> offs) & 0x01;
32637 super::vals::Idr(val as u8)
32638 }
32639 #[doc = "Port input data (y = 0..15)"]
32640 pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) {
32641 assert!(n < 16usize);
32642 let offs = 0usize + n * 1usize;
32643 self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs);
32644 }
32645 }
32646 impl Default for Idr {
32647 fn default() -> Idr {
32648 Idr(0)
32649>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
15433 } 32650 }
15434 } 32651 }
15435 } 32652 }
diff --git a/embassy-stm32/src/pac/stm32h742ag.rs b/embassy-stm32/src/pac/stm32h742ag.rs
index 87ef9faf5..eec02ca71 100644
--- a/embassy-stm32/src/pac/stm32h742ag.rs
+++ b/embassy-stm32/src/pac/stm32h742ag.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h742ai.rs b/embassy-stm32/src/pac/stm32h742ai.rs
index 87ef9faf5..eec02ca71 100644
--- a/embassy-stm32/src/pac/stm32h742ai.rs
+++ b/embassy-stm32/src/pac/stm32h742ai.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h742bg.rs b/embassy-stm32/src/pac/stm32h742bg.rs
index 87ef9faf5..eec02ca71 100644
--- a/embassy-stm32/src/pac/stm32h742bg.rs
+++ b/embassy-stm32/src/pac/stm32h742bg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h742bi.rs b/embassy-stm32/src/pac/stm32h742bi.rs
index 87ef9faf5..eec02ca71 100644
--- a/embassy-stm32/src/pac/stm32h742bi.rs
+++ b/embassy-stm32/src/pac/stm32h742bi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h742ig.rs b/embassy-stm32/src/pac/stm32h742ig.rs
index 87ef9faf5..eec02ca71 100644
--- a/embassy-stm32/src/pac/stm32h742ig.rs
+++ b/embassy-stm32/src/pac/stm32h742ig.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h742ii.rs b/embassy-stm32/src/pac/stm32h742ii.rs
index 87ef9faf5..eec02ca71 100644
--- a/embassy-stm32/src/pac/stm32h742ii.rs
+++ b/embassy-stm32/src/pac/stm32h742ii.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h742vg.rs b/embassy-stm32/src/pac/stm32h742vg.rs
index e70834d73..f066acad9 100644
--- a/embassy-stm32/src/pac/stm32h742vg.rs
+++ b/embassy-stm32/src/pac/stm32h742vg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -285,6 +286,7 @@ impl_spi_pin!(SPI4, MisoPin, PE5, 5);
285impl_spi_pin!(SPI4, MosiPin, PE6, 5); 286impl_spi_pin!(SPI4, MosiPin, PE6, 5);
286pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 287pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
287pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 288pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
289<<<<<<< HEAD
288pub use super::regs::dma_v2 as dma; 290pub use super::regs::dma_v2 as dma;
289pub use super::regs::exti_v1 as exti; 291pub use super::regs::exti_v1 as exti;
290pub use super::regs::gpio_v2 as gpio; 292pub use super::regs::gpio_v2 as gpio;
@@ -293,6 +295,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
293pub use super::regs::spi_v3 as spi; 295pub use super::regs::spi_v3 as spi;
294pub use super::regs::syscfg_h7 as syscfg; 296pub use super::regs::syscfg_h7 as syscfg;
295embassy_extras::peripherals!( 297embassy_extras::peripherals!(
298=======
299pub use regs::dma_v2 as dma;
300pub use regs::exti_v1 as exti;
301pub use regs::gpio_v2 as gpio;
302pub use regs::rcc_h7 as rcc;
303pub use regs::rng_v1 as rng;
304pub use regs::sdmmc_v2 as sdmmc;
305pub use regs::syscfg_h7 as syscfg;
306mod regs;
307use embassy_extras::peripherals;
308pub use regs::generic;
309peripherals!(
310>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
296 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 311 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
297 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 312 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
298 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 313 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -306,7 +321,11 @@ embassy_extras::peripherals!(
306 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 321 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
307 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 322 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
308 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 323 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
324<<<<<<< HEAD
309 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG 325 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
326=======
327 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
328>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
310); 329);
311pub fn DMA(n: u8) -> dma::Dma { 330pub fn DMA(n: u8) -> dma::Dma {
312 match n { 331 match n {
diff --git a/embassy-stm32/src/pac/stm32h742vi.rs b/embassy-stm32/src/pac/stm32h742vi.rs
index e70834d73..f066acad9 100644
--- a/embassy-stm32/src/pac/stm32h742vi.rs
+++ b/embassy-stm32/src/pac/stm32h742vi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -285,6 +286,7 @@ impl_spi_pin!(SPI4, MisoPin, PE5, 5);
285impl_spi_pin!(SPI4, MosiPin, PE6, 5); 286impl_spi_pin!(SPI4, MosiPin, PE6, 5);
286pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 287pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
287pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 288pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
289<<<<<<< HEAD
288pub use super::regs::dma_v2 as dma; 290pub use super::regs::dma_v2 as dma;
289pub use super::regs::exti_v1 as exti; 291pub use super::regs::exti_v1 as exti;
290pub use super::regs::gpio_v2 as gpio; 292pub use super::regs::gpio_v2 as gpio;
@@ -293,6 +295,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
293pub use super::regs::spi_v3 as spi; 295pub use super::regs::spi_v3 as spi;
294pub use super::regs::syscfg_h7 as syscfg; 296pub use super::regs::syscfg_h7 as syscfg;
295embassy_extras::peripherals!( 297embassy_extras::peripherals!(
298=======
299pub use regs::dma_v2 as dma;
300pub use regs::exti_v1 as exti;
301pub use regs::gpio_v2 as gpio;
302pub use regs::rcc_h7 as rcc;
303pub use regs::rng_v1 as rng;
304pub use regs::sdmmc_v2 as sdmmc;
305pub use regs::syscfg_h7 as syscfg;
306mod regs;
307use embassy_extras::peripherals;
308pub use regs::generic;
309peripherals!(
310>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
296 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 311 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
297 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 312 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
298 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 313 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -306,7 +321,11 @@ embassy_extras::peripherals!(
306 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 321 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
307 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 322 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
308 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 323 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
324<<<<<<< HEAD
309 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG 325 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
326=======
327 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
328>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
310); 329);
311pub fn DMA(n: u8) -> dma::Dma { 330pub fn DMA(n: u8) -> dma::Dma {
312 match n { 331 match n {
diff --git a/embassy-stm32/src/pac/stm32h742xg.rs b/embassy-stm32/src/pac/stm32h742xg.rs
index 87ef9faf5..eec02ca71 100644
--- a/embassy-stm32/src/pac/stm32h742xg.rs
+++ b/embassy-stm32/src/pac/stm32h742xg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h742xi.rs b/embassy-stm32/src/pac/stm32h742xi.rs
index 87ef9faf5..eec02ca71 100644
--- a/embassy-stm32/src/pac/stm32h742xi.rs
+++ b/embassy-stm32/src/pac/stm32h742xi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h742zg.rs b/embassy-stm32/src/pac/stm32h742zg.rs
index 87ef9faf5..eec02ca71 100644
--- a/embassy-stm32/src/pac/stm32h742zg.rs
+++ b/embassy-stm32/src/pac/stm32h742zg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h742zi.rs b/embassy-stm32/src/pac/stm32h742zi.rs
index 87ef9faf5..eec02ca71 100644
--- a/embassy-stm32/src/pac/stm32h742zi.rs
+++ b/embassy-stm32/src/pac/stm32h742zi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h743ag.rs b/embassy-stm32/src/pac/stm32h743ag.rs
index 48ff70f87..400002d93 100644
--- a/embassy-stm32/src/pac/stm32h743ag.rs
+++ b/embassy-stm32/src/pac/stm32h743ag.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h743ai.rs b/embassy-stm32/src/pac/stm32h743ai.rs
index 48ff70f87..400002d93 100644
--- a/embassy-stm32/src/pac/stm32h743ai.rs
+++ b/embassy-stm32/src/pac/stm32h743ai.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h743bg.rs b/embassy-stm32/src/pac/stm32h743bg.rs
index 48ff70f87..400002d93 100644
--- a/embassy-stm32/src/pac/stm32h743bg.rs
+++ b/embassy-stm32/src/pac/stm32h743bg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h743bi.rs b/embassy-stm32/src/pac/stm32h743bi.rs
index 48ff70f87..400002d93 100644
--- a/embassy-stm32/src/pac/stm32h743bi.rs
+++ b/embassy-stm32/src/pac/stm32h743bi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h743ig.rs b/embassy-stm32/src/pac/stm32h743ig.rs
index 48ff70f87..400002d93 100644
--- a/embassy-stm32/src/pac/stm32h743ig.rs
+++ b/embassy-stm32/src/pac/stm32h743ig.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h743ii.rs b/embassy-stm32/src/pac/stm32h743ii.rs
index 48ff70f87..400002d93 100644
--- a/embassy-stm32/src/pac/stm32h743ii.rs
+++ b/embassy-stm32/src/pac/stm32h743ii.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h743vg.rs b/embassy-stm32/src/pac/stm32h743vg.rs
index 23eb1ca73..ce0e64c78 100644
--- a/embassy-stm32/src/pac/stm32h743vg.rs
+++ b/embassy-stm32/src/pac/stm32h743vg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -285,6 +286,7 @@ impl_spi_pin!(SPI4, MisoPin, PE5, 5);
285impl_spi_pin!(SPI4, MosiPin, PE6, 5); 286impl_spi_pin!(SPI4, MosiPin, PE6, 5);
286pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 287pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
287pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 288pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
289<<<<<<< HEAD
288pub use super::regs::dma_v2 as dma; 290pub use super::regs::dma_v2 as dma;
289pub use super::regs::exti_v1 as exti; 291pub use super::regs::exti_v1 as exti;
290pub use super::regs::gpio_v2 as gpio; 292pub use super::regs::gpio_v2 as gpio;
@@ -293,6 +295,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
293pub use super::regs::spi_v3 as spi; 295pub use super::regs::spi_v3 as spi;
294pub use super::regs::syscfg_h7 as syscfg; 296pub use super::regs::syscfg_h7 as syscfg;
295embassy_extras::peripherals!( 297embassy_extras::peripherals!(
298=======
299pub use regs::dma_v2 as dma;
300pub use regs::exti_v1 as exti;
301pub use regs::gpio_v2 as gpio;
302pub use regs::rcc_h7 as rcc;
303pub use regs::rng_v1 as rng;
304pub use regs::sdmmc_v2 as sdmmc;
305pub use regs::syscfg_h7 as syscfg;
306mod regs;
307use embassy_extras::peripherals;
308pub use regs::generic;
309peripherals!(
310>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
296 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 311 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
297 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 312 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
298 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 313 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -306,7 +321,11 @@ embassy_extras::peripherals!(
306 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 321 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
307 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 322 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
308 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 323 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
324<<<<<<< HEAD
309 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG 325 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
326=======
327 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
328>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
310); 329);
311pub fn DMA(n: u8) -> dma::Dma { 330pub fn DMA(n: u8) -> dma::Dma {
312 match n { 331 match n {
diff --git a/embassy-stm32/src/pac/stm32h743vi.rs b/embassy-stm32/src/pac/stm32h743vi.rs
index 23eb1ca73..ce0e64c78 100644
--- a/embassy-stm32/src/pac/stm32h743vi.rs
+++ b/embassy-stm32/src/pac/stm32h743vi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -285,6 +286,7 @@ impl_spi_pin!(SPI4, MisoPin, PE5, 5);
285impl_spi_pin!(SPI4, MosiPin, PE6, 5); 286impl_spi_pin!(SPI4, MosiPin, PE6, 5);
286pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 287pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
287pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 288pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
289<<<<<<< HEAD
288pub use super::regs::dma_v2 as dma; 290pub use super::regs::dma_v2 as dma;
289pub use super::regs::exti_v1 as exti; 291pub use super::regs::exti_v1 as exti;
290pub use super::regs::gpio_v2 as gpio; 292pub use super::regs::gpio_v2 as gpio;
@@ -293,6 +295,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
293pub use super::regs::spi_v3 as spi; 295pub use super::regs::spi_v3 as spi;
294pub use super::regs::syscfg_h7 as syscfg; 296pub use super::regs::syscfg_h7 as syscfg;
295embassy_extras::peripherals!( 297embassy_extras::peripherals!(
298=======
299pub use regs::dma_v2 as dma;
300pub use regs::exti_v1 as exti;
301pub use regs::gpio_v2 as gpio;
302pub use regs::rcc_h7 as rcc;
303pub use regs::rng_v1 as rng;
304pub use regs::sdmmc_v2 as sdmmc;
305pub use regs::syscfg_h7 as syscfg;
306mod regs;
307use embassy_extras::peripherals;
308pub use regs::generic;
309peripherals!(
310>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
296 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 311 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
297 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 312 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
298 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 313 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -306,7 +321,11 @@ embassy_extras::peripherals!(
306 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 321 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
307 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 322 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
308 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 323 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
324<<<<<<< HEAD
309 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG 325 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
326=======
327 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
328>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
310); 329);
311pub fn DMA(n: u8) -> dma::Dma { 330pub fn DMA(n: u8) -> dma::Dma {
312 match n { 331 match n {
diff --git a/embassy-stm32/src/pac/stm32h743xg.rs b/embassy-stm32/src/pac/stm32h743xg.rs
index 48ff70f87..400002d93 100644
--- a/embassy-stm32/src/pac/stm32h743xg.rs
+++ b/embassy-stm32/src/pac/stm32h743xg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h743xi.rs b/embassy-stm32/src/pac/stm32h743xi.rs
index 48ff70f87..400002d93 100644
--- a/embassy-stm32/src/pac/stm32h743xi.rs
+++ b/embassy-stm32/src/pac/stm32h743xi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h743zg.rs b/embassy-stm32/src/pac/stm32h743zg.rs
index 48ff70f87..400002d93 100644
--- a/embassy-stm32/src/pac/stm32h743zg.rs
+++ b/embassy-stm32/src/pac/stm32h743zg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h743zi.rs b/embassy-stm32/src/pac/stm32h743zi.rs
index 48ff70f87..400002d93 100644
--- a/embassy-stm32/src/pac/stm32h743zi.rs
+++ b/embassy-stm32/src/pac/stm32h743zi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h745bg.rs b/embassy-stm32/src/pac/stm32h745bg.rs
index 3f32b6cc1..b0de7dfdf 100644
--- a/embassy-stm32/src/pac/stm32h745bg.rs
+++ b/embassy-stm32/src/pac/stm32h745bg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h745bi.rs b/embassy-stm32/src/pac/stm32h745bi.rs
index 3f32b6cc1..b0de7dfdf 100644
--- a/embassy-stm32/src/pac/stm32h745bi.rs
+++ b/embassy-stm32/src/pac/stm32h745bi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h745ig.rs b/embassy-stm32/src/pac/stm32h745ig.rs
index 3f32b6cc1..b0de7dfdf 100644
--- a/embassy-stm32/src/pac/stm32h745ig.rs
+++ b/embassy-stm32/src/pac/stm32h745ig.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h745ii.rs b/embassy-stm32/src/pac/stm32h745ii.rs
index 3f32b6cc1..b0de7dfdf 100644
--- a/embassy-stm32/src/pac/stm32h745ii.rs
+++ b/embassy-stm32/src/pac/stm32h745ii.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h745xg.rs b/embassy-stm32/src/pac/stm32h745xg.rs
index 3f32b6cc1..b0de7dfdf 100644
--- a/embassy-stm32/src/pac/stm32h745xg.rs
+++ b/embassy-stm32/src/pac/stm32h745xg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h745xi.rs b/embassy-stm32/src/pac/stm32h745xi.rs
index 3f32b6cc1..b0de7dfdf 100644
--- a/embassy-stm32/src/pac/stm32h745xi.rs
+++ b/embassy-stm32/src/pac/stm32h745xi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h745zg.rs b/embassy-stm32/src/pac/stm32h745zg.rs
index 3f32b6cc1..b0de7dfdf 100644
--- a/embassy-stm32/src/pac/stm32h745zg.rs
+++ b/embassy-stm32/src/pac/stm32h745zg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h745zi.rs b/embassy-stm32/src/pac/stm32h745zi.rs
index 3f32b6cc1..b0de7dfdf 100644
--- a/embassy-stm32/src/pac/stm32h745zi.rs
+++ b/embassy-stm32/src/pac/stm32h745zi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h747ag.rs b/embassy-stm32/src/pac/stm32h747ag.rs
index cef04c6a5..e9ea09cce 100644
--- a/embassy-stm32/src/pac/stm32h747ag.rs
+++ b/embassy-stm32/src/pac/stm32h747ag.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h747ai.rs b/embassy-stm32/src/pac/stm32h747ai.rs
index cef04c6a5..e9ea09cce 100644
--- a/embassy-stm32/src/pac/stm32h747ai.rs
+++ b/embassy-stm32/src/pac/stm32h747ai.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h747bg.rs b/embassy-stm32/src/pac/stm32h747bg.rs
index cef04c6a5..e9ea09cce 100644
--- a/embassy-stm32/src/pac/stm32h747bg.rs
+++ b/embassy-stm32/src/pac/stm32h747bg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h747bi.rs b/embassy-stm32/src/pac/stm32h747bi.rs
index cef04c6a5..e9ea09cce 100644
--- a/embassy-stm32/src/pac/stm32h747bi.rs
+++ b/embassy-stm32/src/pac/stm32h747bi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h747ig.rs b/embassy-stm32/src/pac/stm32h747ig.rs
index cef04c6a5..e9ea09cce 100644
--- a/embassy-stm32/src/pac/stm32h747ig.rs
+++ b/embassy-stm32/src/pac/stm32h747ig.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h747ii.rs b/embassy-stm32/src/pac/stm32h747ii.rs
index cef04c6a5..e9ea09cce 100644
--- a/embassy-stm32/src/pac/stm32h747ii.rs
+++ b/embassy-stm32/src/pac/stm32h747ii.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h747xg.rs b/embassy-stm32/src/pac/stm32h747xg.rs
index cef04c6a5..e9ea09cce 100644
--- a/embassy-stm32/src/pac/stm32h747xg.rs
+++ b/embassy-stm32/src/pac/stm32h747xg.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h747xi.rs b/embassy-stm32/src/pac/stm32h747xi.rs
index cef04c6a5..e9ea09cce 100644
--- a/embassy-stm32/src/pac/stm32h747xi.rs
+++ b/embassy-stm32/src/pac/stm32h747xi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h747zi.rs b/embassy-stm32/src/pac/stm32h747zi.rs
index 89ec9be39..2833c9a2f 100644
--- a/embassy-stm32/src/pac/stm32h747zi.rs
+++ b/embassy-stm32/src/pac/stm32h747zi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, RNG); 216impl_rng!(RNG, RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -285,6 +286,7 @@ impl_spi_pin!(SPI4, MisoPin, PE5, 5);
285impl_spi_pin!(SPI4, MosiPin, PE6, 5); 286impl_spi_pin!(SPI4, MosiPin, PE6, 5);
286pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 287pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
287pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 288pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
289<<<<<<< HEAD
288pub use super::regs::dma_v2 as dma; 290pub use super::regs::dma_v2 as dma;
289pub use super::regs::exti_v1 as exti; 291pub use super::regs::exti_v1 as exti;
290pub use super::regs::gpio_v2 as gpio; 292pub use super::regs::gpio_v2 as gpio;
@@ -293,6 +295,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
293pub use super::regs::spi_v3 as spi; 295pub use super::regs::spi_v3 as spi;
294pub use super::regs::syscfg_h7 as syscfg; 296pub use super::regs::syscfg_h7 as syscfg;
295embassy_extras::peripherals!( 297embassy_extras::peripherals!(
298=======
299pub use regs::dma_v2 as dma;
300pub use regs::exti_v1 as exti;
301pub use regs::gpio_v2 as gpio;
302pub use regs::rcc_h7 as rcc;
303pub use regs::rng_v1 as rng;
304pub use regs::sdmmc_v2 as sdmmc;
305pub use regs::syscfg_h7 as syscfg;
306mod regs;
307use embassy_extras::peripherals;
308pub use regs::generic;
309peripherals!(
310>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
296 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 311 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
297 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 312 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
298 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 313 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -306,7 +321,11 @@ embassy_extras::peripherals!(
306 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 321 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
307 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 322 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
308 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 323 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
324<<<<<<< HEAD
309 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG 325 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
326=======
327 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
328>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
310); 329);
311pub fn DMA(n: u8) -> dma::Dma { 330pub fn DMA(n: u8) -> dma::Dma {
312 match n { 331 match n {
diff --git a/embassy-stm32/src/pac/stm32h750ib.rs b/embassy-stm32/src/pac/stm32h750ib.rs
index 318356593..8ae43eaf3 100644
--- a/embassy-stm32/src/pac/stm32h750ib.rs
+++ b/embassy-stm32/src/pac/stm32h750ib.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h750vb.rs b/embassy-stm32/src/pac/stm32h750vb.rs
index 3d07ff7f9..c20b70fcd 100644
--- a/embassy-stm32/src/pac/stm32h750vb.rs
+++ b/embassy-stm32/src/pac/stm32h750vb.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -285,6 +286,7 @@ impl_spi_pin!(SPI4, MisoPin, PE5, 5);
285impl_spi_pin!(SPI4, MosiPin, PE6, 5); 286impl_spi_pin!(SPI4, MosiPin, PE6, 5);
286pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 287pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
287pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 288pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
289<<<<<<< HEAD
288pub use super::regs::dma_v2 as dma; 290pub use super::regs::dma_v2 as dma;
289pub use super::regs::exti_v1 as exti; 291pub use super::regs::exti_v1 as exti;
290pub use super::regs::gpio_v2 as gpio; 292pub use super::regs::gpio_v2 as gpio;
@@ -293,6 +295,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
293pub use super::regs::spi_v3 as spi; 295pub use super::regs::spi_v3 as spi;
294pub use super::regs::syscfg_h7 as syscfg; 296pub use super::regs::syscfg_h7 as syscfg;
295embassy_extras::peripherals!( 297embassy_extras::peripherals!(
298=======
299pub use regs::dma_v2 as dma;
300pub use regs::exti_v1 as exti;
301pub use regs::gpio_v2 as gpio;
302pub use regs::rcc_h7 as rcc;
303pub use regs::rng_v1 as rng;
304pub use regs::sdmmc_v2 as sdmmc;
305pub use regs::syscfg_h7 as syscfg;
306mod regs;
307use embassy_extras::peripherals;
308pub use regs::generic;
309peripherals!(
310>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
296 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 311 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
297 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 312 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
298 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 313 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -306,7 +321,11 @@ embassy_extras::peripherals!(
306 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 321 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
307 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 322 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
308 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 323 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
324<<<<<<< HEAD
309 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG 325 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
326=======
327 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
328>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
310); 329);
311pub fn DMA(n: u8) -> dma::Dma { 330pub fn DMA(n: u8) -> dma::Dma {
312 match n { 331 match n {
diff --git a/embassy-stm32/src/pac/stm32h750xb.rs b/embassy-stm32/src/pac/stm32h750xb.rs
index 318356593..8ae43eaf3 100644
--- a/embassy-stm32/src/pac/stm32h750xb.rs
+++ b/embassy-stm32/src/pac/stm32h750xb.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h750zb.rs b/embassy-stm32/src/pac/stm32h750zb.rs
index 318356593..8ae43eaf3 100644
--- a/embassy-stm32/src/pac/stm32h750zb.rs
+++ b/embassy-stm32/src/pac/stm32h750zb.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h753ai.rs b/embassy-stm32/src/pac/stm32h753ai.rs
index 318356593..8ae43eaf3 100644
--- a/embassy-stm32/src/pac/stm32h753ai.rs
+++ b/embassy-stm32/src/pac/stm32h753ai.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h753bi.rs b/embassy-stm32/src/pac/stm32h753bi.rs
index 318356593..8ae43eaf3 100644
--- a/embassy-stm32/src/pac/stm32h753bi.rs
+++ b/embassy-stm32/src/pac/stm32h753bi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h753ii.rs b/embassy-stm32/src/pac/stm32h753ii.rs
index 318356593..8ae43eaf3 100644
--- a/embassy-stm32/src/pac/stm32h753ii.rs
+++ b/embassy-stm32/src/pac/stm32h753ii.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h753vi.rs b/embassy-stm32/src/pac/stm32h753vi.rs
index 3d07ff7f9..c20b70fcd 100644
--- a/embassy-stm32/src/pac/stm32h753vi.rs
+++ b/embassy-stm32/src/pac/stm32h753vi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -285,6 +286,7 @@ impl_spi_pin!(SPI4, MisoPin, PE5, 5);
285impl_spi_pin!(SPI4, MosiPin, PE6, 5); 286impl_spi_pin!(SPI4, MosiPin, PE6, 5);
286pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 287pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
287pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 288pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
289<<<<<<< HEAD
288pub use super::regs::dma_v2 as dma; 290pub use super::regs::dma_v2 as dma;
289pub use super::regs::exti_v1 as exti; 291pub use super::regs::exti_v1 as exti;
290pub use super::regs::gpio_v2 as gpio; 292pub use super::regs::gpio_v2 as gpio;
@@ -293,6 +295,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
293pub use super::regs::spi_v3 as spi; 295pub use super::regs::spi_v3 as spi;
294pub use super::regs::syscfg_h7 as syscfg; 296pub use super::regs::syscfg_h7 as syscfg;
295embassy_extras::peripherals!( 297embassy_extras::peripherals!(
298=======
299pub use regs::dma_v2 as dma;
300pub use regs::exti_v1 as exti;
301pub use regs::gpio_v2 as gpio;
302pub use regs::rcc_h7 as rcc;
303pub use regs::rng_v1 as rng;
304pub use regs::sdmmc_v2 as sdmmc;
305pub use regs::syscfg_h7 as syscfg;
306mod regs;
307use embassy_extras::peripherals;
308pub use regs::generic;
309peripherals!(
310>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
296 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 311 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
297 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 312 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
298 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 313 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -306,7 +321,11 @@ embassy_extras::peripherals!(
306 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 321 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
307 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 322 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
308 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 323 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
324<<<<<<< HEAD
309 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG 325 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
326=======
327 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
328>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
310); 329);
311pub fn DMA(n: u8) -> dma::Dma { 330pub fn DMA(n: u8) -> dma::Dma {
312 match n { 331 match n {
diff --git a/embassy-stm32/src/pac/stm32h753xi.rs b/embassy-stm32/src/pac/stm32h753xi.rs
index 318356593..8ae43eaf3 100644
--- a/embassy-stm32/src/pac/stm32h753xi.rs
+++ b/embassy-stm32/src/pac/stm32h753xi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h753zi.rs b/embassy-stm32/src/pac/stm32h753zi.rs
index 318356593..8ae43eaf3 100644
--- a/embassy-stm32/src/pac/stm32h753zi.rs
+++ b/embassy-stm32/src/pac/stm32h753zi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h755bi.rs b/embassy-stm32/src/pac/stm32h755bi.rs
index 3df475104..4bc3119e3 100644
--- a/embassy-stm32/src/pac/stm32h755bi.rs
+++ b/embassy-stm32/src/pac/stm32h755bi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h755ii.rs b/embassy-stm32/src/pac/stm32h755ii.rs
index 3df475104..4bc3119e3 100644
--- a/embassy-stm32/src/pac/stm32h755ii.rs
+++ b/embassy-stm32/src/pac/stm32h755ii.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h755xi.rs b/embassy-stm32/src/pac/stm32h755xi.rs
index 3df475104..4bc3119e3 100644
--- a/embassy-stm32/src/pac/stm32h755xi.rs
+++ b/embassy-stm32/src/pac/stm32h755xi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h755zi.rs b/embassy-stm32/src/pac/stm32h755zi.rs
index 3df475104..4bc3119e3 100644
--- a/embassy-stm32/src/pac/stm32h755zi.rs
+++ b/embassy-stm32/src/pac/stm32h755zi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h757ai.rs b/embassy-stm32/src/pac/stm32h757ai.rs
index 73175e0ef..ba6c13000 100644
--- a/embassy-stm32/src/pac/stm32h757ai.rs
+++ b/embassy-stm32/src/pac/stm32h757ai.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h757bi.rs b/embassy-stm32/src/pac/stm32h757bi.rs
index 73175e0ef..ba6c13000 100644
--- a/embassy-stm32/src/pac/stm32h757bi.rs
+++ b/embassy-stm32/src/pac/stm32h757bi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h757ii.rs b/embassy-stm32/src/pac/stm32h757ii.rs
index 73175e0ef..ba6c13000 100644
--- a/embassy-stm32/src/pac/stm32h757ii.rs
+++ b/embassy-stm32/src/pac/stm32h757ii.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h757xi.rs b/embassy-stm32/src/pac/stm32h757xi.rs
index 73175e0ef..ba6c13000 100644
--- a/embassy-stm32/src/pac/stm32h757xi.rs
+++ b/embassy-stm32/src/pac/stm32h757xi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -296,6 +297,7 @@ impl_spi_pin!(SPI5, MisoPin, PJ11, 5);
296impl_spi_pin!(SPI5, SckPin, PK0, 5); 297impl_spi_pin!(SPI5, SckPin, PK0, 5);
297pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 298pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
298pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 299pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
300<<<<<<< HEAD
299pub use super::regs::dma_v2 as dma; 301pub use super::regs::dma_v2 as dma;
300pub use super::regs::exti_v1 as exti; 302pub use super::regs::exti_v1 as exti;
301pub use super::regs::gpio_v2 as gpio; 303pub use super::regs::gpio_v2 as gpio;
@@ -304,6 +306,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
304pub use super::regs::spi_v3 as spi; 306pub use super::regs::spi_v3 as spi;
305pub use super::regs::syscfg_h7 as syscfg; 307pub use super::regs::syscfg_h7 as syscfg;
306embassy_extras::peripherals!( 308embassy_extras::peripherals!(
309=======
310pub use regs::dma_v2 as dma;
311pub use regs::exti_v1 as exti;
312pub use regs::gpio_v2 as gpio;
313pub use regs::rcc_h7 as rcc;
314pub use regs::rng_v1 as rng;
315pub use regs::sdmmc_v2 as sdmmc;
316pub use regs::syscfg_h7 as syscfg;
317mod regs;
318use embassy_extras::peripherals;
319pub use regs::generic;
320peripherals!(
321>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
307 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 322 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
308 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 323 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
309 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 324 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -317,7 +332,11 @@ embassy_extras::peripherals!(
317 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 332 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
318 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 333 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
319 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 334 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
335<<<<<<< HEAD
320 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG 336 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG
337=======
338 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
339>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
321); 340);
322pub fn DMA(n: u8) -> dma::Dma { 341pub fn DMA(n: u8) -> dma::Dma {
323 match n { 342 match n {
diff --git a/embassy-stm32/src/pac/stm32h757zi.rs b/embassy-stm32/src/pac/stm32h757zi.rs
index 07f1c4336..e74380e8d 100644
--- a/embassy-stm32/src/pac/stm32h757zi.rs
+++ b/embassy-stm32/src/pac/stm32h757zi.rs
@@ -211,6 +211,7 @@ impl_gpio_pin!(PK12, 10, 12, EXTI12);
211impl_gpio_pin!(PK13, 10, 13, EXTI13); 211impl_gpio_pin!(PK13, 10, 13, EXTI13);
212impl_gpio_pin!(PK14, 10, 14, EXTI14); 212impl_gpio_pin!(PK14, 10, 14, EXTI14);
213impl_gpio_pin!(PK15, 10, 15, EXTI15); 213impl_gpio_pin!(PK15, 10, 15, EXTI15);
214pub const RCC: rcc::Rcc = rcc::Rcc(0x58024400 as _);
214pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); 215pub const RNG: rng::Rng = rng::Rng(0x48021800 as _);
215impl_rng!(RNG, HASH_RNG); 216impl_rng!(RNG, HASH_RNG);
216pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); 217pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _);
@@ -285,6 +286,7 @@ impl_spi_pin!(SPI4, MisoPin, PE5, 5);
285impl_spi_pin!(SPI4, MosiPin, PE6, 5); 286impl_spi_pin!(SPI4, MosiPin, PE6, 5);
286pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _); 287pub const SPI6: spi::Spi = spi::Spi(0x58001400 as _);
287pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); 288pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _);
289<<<<<<< HEAD
288pub use super::regs::dma_v2 as dma; 290pub use super::regs::dma_v2 as dma;
289pub use super::regs::exti_v1 as exti; 291pub use super::regs::exti_v1 as exti;
290pub use super::regs::gpio_v2 as gpio; 292pub use super::regs::gpio_v2 as gpio;
@@ -293,6 +295,19 @@ pub use super::regs::sdmmc_v2 as sdmmc;
293pub use super::regs::spi_v3 as spi; 295pub use super::regs::spi_v3 as spi;
294pub use super::regs::syscfg_h7 as syscfg; 296pub use super::regs::syscfg_h7 as syscfg;
295embassy_extras::peripherals!( 297embassy_extras::peripherals!(
298=======
299pub use regs::dma_v2 as dma;
300pub use regs::exti_v1 as exti;
301pub use regs::gpio_v2 as gpio;
302pub use regs::rcc_h7 as rcc;
303pub use regs::rng_v1 as rng;
304pub use regs::sdmmc_v2 as sdmmc;
305pub use regs::syscfg_h7 as syscfg;
306mod regs;
307use embassy_extras::peripherals;
308pub use regs::generic;
309peripherals!(
310>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
296 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, 311 EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
297 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, 312 EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
298 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, 313 DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
@@ -306,7 +321,11 @@ embassy_extras::peripherals!(
306 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, 321 PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
307 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, 322 PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
308 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, 323 PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
324<<<<<<< HEAD
309 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG 325 PK15, RNG, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SYSCFG
326=======
327 PK15, RCC, RNG, SDMMC1, SDMMC2, SYSCFG
328>>>>>>> 3baa749 (Add pac RCC for H7 (generated))
310); 329);
311pub fn DMA(n: u8) -> dma::Dma { 330pub fn DMA(n: u8) -> dma::Dma {
312 match n { 331 match n {
diff --git a/embassy-stm32/stm32-data b/embassy-stm32/stm32-data
Subproject dc3c92f0323bfe2967ecd8f92b2c53fb3dfb44f Subproject dc1cd90181c0deb2874f5145f76a03658f50d92
generated by cgit (git 2.34.1) at 2026-04-06 08:11:17 +0000