diff options
| author | Karun <[email protected]> | 2024-04-03 16:05:23 -0400 |
|---|---|---|
| committer | Karun <[email protected]> | 2024-04-03 16:05:23 -0400 |
| commit | 80aeea93fd9d34b95441b6900e658e86b5b18b03 (patch) | |
| tree | 1be3de56fc842346525c91311c60ffc1ac56100f | |
| parent | b3bbf42b8bf4d31dab66bf75d80389279b0502f2 (diff) | |
Configure dual-quad setting by constructor
| -rw-r--r-- | embassy-stm32/src/ospi/mod.rs | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/embassy-stm32/src/ospi/mod.rs b/embassy-stm32/src/ospi/mod.rs index bcdffc266..7020cf9ad 100644 --- a/embassy-stm32/src/ospi/mod.rs +++ b/embassy-stm32/src/ospi/mod.rs | |||
| @@ -23,9 +23,6 @@ pub struct Config { | |||
| 23 | /// Fifo threshold used by the peripheral to generate the interrupt indicating data | 23 | /// Fifo threshold used by the peripheral to generate the interrupt indicating data |
| 24 | /// or space is available in the FIFO | 24 | /// or space is available in the FIFO |
| 25 | pub fifo_threshold: FIFOThresholdLevel, | 25 | pub fifo_threshold: FIFOThresholdLevel, |
| 26 | /// Enables dual-quad mode which allows access to two devices simultaneously to | ||
| 27 | /// increase throughput | ||
| 28 | pub dual_quad: bool, | ||
| 29 | /// Indicates the type of external device connected | 26 | /// Indicates the type of external device connected |
| 30 | pub memory_type: MemoryType, // Need to add an additional enum to provide this public interface | 27 | pub memory_type: MemoryType, // Need to add an additional enum to provide this public interface |
| 31 | /// Defines the size of the external device connected to the OSPI corresponding | 28 | /// Defines the size of the external device connected to the OSPI corresponding |
| @@ -64,7 +61,6 @@ impl Default for Config { | |||
| 64 | fn default() -> Self { | 61 | fn default() -> Self { |
| 65 | Self { | 62 | Self { |
| 66 | fifo_threshold: FIFOThresholdLevel::_16Bytes, // 32 bytes FIFO, half capacity | 63 | fifo_threshold: FIFOThresholdLevel::_16Bytes, // 32 bytes FIFO, half capacity |
| 67 | dual_quad: false, | ||
| 68 | memory_type: MemoryType::Micron, | 64 | memory_type: MemoryType::Micron, |
| 69 | device_size: MemorySize::Other(0), | 65 | device_size: MemorySize::Other(0), |
| 70 | chip_select_high_time: ChipSelectHighTime::_5Cycle, | 66 | chip_select_high_time: ChipSelectHighTime::_5Cycle, |
| @@ -196,6 +192,10 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> { | |||
| 196 | d1.set_as_af_pull(d1.af_num(), AFType::Input, Pull::None); | 192 | d1.set_as_af_pull(d1.af_num(), AFType::Input, Pull::None); |
| 197 | d1.set_speed(crate::gpio::Speed::VeryHigh); | 193 | d1.set_speed(crate::gpio::Speed::VeryHigh); |
| 198 | 194 | ||
| 195 | T::REGS.cr().modify(|w| { | ||
| 196 | w.set_dmm(false); | ||
| 197 | }); | ||
| 198 | |||
| 199 | Self::new_inner( | 199 | Self::new_inner( |
| 200 | peri, | 200 | peri, |
| 201 | Some(d0.map_into()), | 201 | Some(d0.map_into()), |
| @@ -236,6 +236,10 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> { | |||
| 236 | d1.set_as_af_pull(d1.af_num(), AFType::OutputPushPull, Pull::None); | 236 | d1.set_as_af_pull(d1.af_num(), AFType::OutputPushPull, Pull::None); |
| 237 | d1.set_speed(crate::gpio::Speed::VeryHigh); | 237 | d1.set_speed(crate::gpio::Speed::VeryHigh); |
| 238 | 238 | ||
| 239 | T::REGS.cr().modify(|w| { | ||
| 240 | w.set_dmm(false); | ||
| 241 | }); | ||
| 242 | |||
| 239 | Self::new_inner( | 243 | Self::new_inner( |
| 240 | peri, | 244 | peri, |
| 241 | Some(d0.map_into()), | 245 | Some(d0.map_into()), |
| @@ -282,6 +286,10 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> { | |||
| 282 | d3.set_as_af_pull(d3.af_num(), AFType::OutputPushPull, Pull::None); | 286 | d3.set_as_af_pull(d3.af_num(), AFType::OutputPushPull, Pull::None); |
| 283 | d3.set_speed(crate::gpio::Speed::VeryHigh); | 287 | d3.set_speed(crate::gpio::Speed::VeryHigh); |
| 284 | 288 | ||
| 289 | T::REGS.cr().modify(|w| { | ||
| 290 | w.set_dmm(false); | ||
| 291 | }); | ||
| 292 | |||
| 285 | Self::new_inner( | 293 | Self::new_inner( |
| 286 | peri, | 294 | peri, |
| 287 | Some(d0.map_into()), | 295 | Some(d0.map_into()), |
| @@ -340,6 +348,10 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> { | |||
| 340 | d7.set_as_af_pull(d7.af_num(), AFType::OutputPushPull, Pull::None); | 348 | d7.set_as_af_pull(d7.af_num(), AFType::OutputPushPull, Pull::None); |
| 341 | d7.set_speed(crate::gpio::Speed::VeryHigh); | 349 | d7.set_speed(crate::gpio::Speed::VeryHigh); |
| 342 | 350 | ||
| 351 | T::REGS.cr().modify(|w| { | ||
| 352 | w.set_dmm(true); | ||
| 353 | }); | ||
| 354 | |||
| 343 | Self::new_inner( | 355 | Self::new_inner( |
| 344 | peri, | 356 | peri, |
| 345 | Some(d0.map_into()), | 357 | Some(d0.map_into()), |
| @@ -398,6 +410,10 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> { | |||
| 398 | d7.set_as_af_pull(d7.af_num(), AFType::OutputPushPull, Pull::None); | 410 | d7.set_as_af_pull(d7.af_num(), AFType::OutputPushPull, Pull::None); |
| 399 | d7.set_speed(crate::gpio::Speed::VeryHigh); | 411 | d7.set_speed(crate::gpio::Speed::VeryHigh); |
| 400 | 412 | ||
| 413 | T::REGS.cr().modify(|w| { | ||
| 414 | w.set_dmm(false); | ||
| 415 | }); | ||
| 416 | |||
| 401 | Self::new_inner( | 417 | Self::new_inner( |
| 402 | peri, | 418 | peri, |
| 403 | Some(d0.map_into()), | 419 | Some(d0.map_into()), |
| @@ -477,10 +493,6 @@ impl<'d, T: Instance, Dma> Ospi<'d, T, Dma> { | |||
| 477 | w.set_prescaler(config.clock_prescaler); | 493 | w.set_prescaler(config.clock_prescaler); |
| 478 | }); | 494 | }); |
| 479 | 495 | ||
| 480 | T::REGS.cr().modify(|w| { | ||
| 481 | w.set_dmm(config.dual_quad); | ||
| 482 | }); | ||
| 483 | |||
| 484 | T::REGS.tcr().modify(|w| { | 496 | T::REGS.tcr().modify(|w| { |
| 485 | w.set_sshift(match config.sample_shifting { | 497 | w.set_sshift(match config.sample_shifting { |
| 486 | true => vals::SampleShift::HALFCYCLE, | 498 | true => vals::SampleShift::HALFCYCLE, |
