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authorMaor Malka <[email protected]>2025-11-01 20:14:25 -0400
committerMaor Malka <[email protected]>2025-11-01 20:14:25 -0400
commit82158642e202cffbc527d672cdc33930bef5c78d (patch)
treef1caf160242dda63d9b973211fbbd783c07d5f4f
parent07549723afaea68f033aa688f1096dc46d9b192b (diff)
stm32/adc/ringbuffered_v3: lower visability for RingBufferedAdc::new
-rw-r--r--embassy-stm32/src/adc/ringbuffered_v3.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-stm32/src/adc/ringbuffered_v3.rs b/embassy-stm32/src/adc/ringbuffered_v3.rs
index b58630585..0aee309e3 100644
--- a/embassy-stm32/src/adc/ringbuffered_v3.rs
+++ b/embassy-stm32/src/adc/ringbuffered_v3.rs
@@ -16,7 +16,7 @@ pub struct RingBufferedAdc<'d, T: Instance> {
16} 16}
17 17
18impl<'d, T: Instance> RingBufferedAdc<'d, T> { 18impl<'d, T: Instance> RingBufferedAdc<'d, T> {
19 pub fn new(dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> Self { 19 pub(crate) fn new(dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> Self {
20 //dma side setup 20 //dma side setup
21 let opts = TransferOptions { 21 let opts = TransferOptions {
22 half_transfer_ir: true, 22 half_transfer_ir: true,