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authorMathias <[email protected]>2022-09-28 05:19:43 +0200
committerMathias <[email protected]>2022-09-28 05:19:43 +0200
commit823bd714fb6da94cf3b31c2066c398207228b4c6 (patch)
treeada80c9c3af0193e9c3604c072356c281541b886
parent9bb43ffe9adddb3497bb08d0730635fbd66cff94 (diff)
Add E-H1 uart blocking & nb implementation
-rw-r--r--embassy-stm32/src/usart/mod.rs73
1 files changed, 73 insertions, 0 deletions
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 6c2668748..5ee099348 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -359,6 +359,79 @@ mod eh1 {
359 impl<'d, T: BasicInstance, RxDma> embedded_hal_1::serial::ErrorType for UartRx<'d, T, RxDma> { 359 impl<'d, T: BasicInstance, RxDma> embedded_hal_1::serial::ErrorType for UartRx<'d, T, RxDma> {
360 type Error = Error; 360 type Error = Error;
361 } 361 }
362
363
364 impl<'d, T: BasicInstance, RxDma> embedded_hal_1::serial::nb::Read for UartRx<'d, T, RxDma> {
365 fn read(&mut self) -> nb::Result<u8, Self::Error> {
366 let r = T::regs();
367 unsafe {
368 let sr = sr(r).read();
369 if sr.pe() {
370 rdr(r).read_volatile();
371 Err(nb::Error::Other(Error::Parity))
372 } else if sr.fe() {
373 rdr(r).read_volatile();
374 Err(nb::Error::Other(Error::Framing))
375 } else if sr.ne() {
376 rdr(r).read_volatile();
377 Err(nb::Error::Other(Error::Noise))
378 } else if sr.ore() {
379 rdr(r).read_volatile();
380 Err(nb::Error::Other(Error::Overrun))
381 } else if sr.rxne() {
382 Ok(rdr(r).read_volatile())
383 } else {
384 Err(nb::Error::WouldBlock)
385 }
386 }
387 }
388 }
389
390 impl<'d, T: BasicInstance, TxDma> embedded_hal_1::serial::blocking::Write for UartTx<'d, T, TxDma> {
391 fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
392 self.blocking_write(buffer)
393 }
394
395 fn flush(&mut self) -> Result<(), Self::Error> {
396 self.blocking_flush()
397 }
398 }
399
400 impl<'d, T: BasicInstance, TxDma> embedded_hal_1::serial::nb::Write for UartTx<'d, T, TxDma> {
401 fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
402 self.blocking_write(&[char]).map_err(nb::Error::Other)
403 }
404
405 fn flush(&mut self) -> nb::Result<(), Self::Error> {
406 self.blocking_flush().map_err(nb::Error::Other)
407 }
408 }
409
410 impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_1::serial::nb::Read for Uart<'d, T, TxDma, RxDma> {
411 fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
412 embedded_hal_02::serial::Read::read(&mut self.rx)
413 }
414 }
415
416 impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_1::serial::blocking::Write for Uart<'d, T, TxDma, RxDma> {
417 fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
418 self.blocking_write(buffer)
419 }
420
421 fn flush(&mut self) -> Result<(), Self::Error> {
422 self.blocking_flush()
423 }
424 }
425
426 impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_1::serial::nb::Write for Uart<'d, T, TxDma, RxDma> {
427 fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
428 self.blocking_write(&[char]).map_err(nb::Error::Other)
429 }
430
431 fn flush(&mut self) -> nb::Result<(), Self::Error> {
432 self.blocking_flush().map_err(nb::Error::Other)
433 }
434 }
362} 435}
363 436
364#[cfg(all( 437#[cfg(all(