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authorHybridChild <[email protected]>2025-11-13 21:24:09 +0100
committerHybridChild <[email protected]>2025-11-13 21:24:09 +0100
commit82dcaf118100c883a95397e3f9867a4043a4de7b (patch)
tree45c8d1d630b7599fbb65220b36427b8c8857769d
parent42f38d5b3209134baa8bf424cdb754e1901ac0da (diff)
stm32: Run cargo fmt
-rw-r--r--embassy-stm32/src/i2c/v2.rs18
1 files changed, 11 insertions, 7 deletions
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 8f51627ff..61e550ad4 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -925,7 +925,13 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
925 timeout, 925 timeout,
926 )?; 926 )?;
927 } else { 927 } else {
928 Self::reload(self.info, total_len.min(255), (total_len > 255) || !last_slice, Stop::Software, timeout)?; 928 Self::reload(
929 self.info,
930 total_len.min(255),
931 (total_len > 255) || !last_slice,
932 Stop::Software,
933 timeout,
934 )?;
929 self.info.regs.cr1().modify(|w| w.set_tcie(true)); 935 self.info.regs.cr1().modify(|w| w.set_tcie(true));
930 } 936 }
931 } else if !(isr.tcr() || isr.tc()) { 937 } else if !(isr.tcr() || isr.tc()) {
@@ -1102,12 +1108,10 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
1102 let is_last = next.is_none(); 1108 let is_last = next.is_none();
1103 1109
1104 let fut = self.write_dma_internal( 1110 let fut = self.write_dma_internal(
1105 address, 1111 address, c, first, // first_slice
1106 c, 1112 is_last, // last_slice
1107 first, // first_slice 1113 is_last, // send_stop (only on last buffer)
1108 is_last, // last_slice 1114 false, // restart (false for all - they're one continuous write)
1109 is_last, // send_stop (only on last buffer)
1110 false, // restart (false for all - they're one continuous write)
1111 timeout, 1115 timeout,
1112 ); 1116 );
1113 timeout.with(fut).await?; 1117 timeout.with(fut).await?;