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authorDario Nieuwenhuis <[email protected]>2025-09-28 22:43:10 +0200
committerDario Nieuwenhuis <[email protected]>2025-09-28 22:54:13 +0200
commit864eaef3a3f7678bcc4ff20b5180b1ce50332fce (patch)
tree332718f0fd84026562d3ebd0b1acec60696a9479
parentb2727640ed5ff514ca2bbaacc058bfa546767e4d (diff)
nrf/usb: erase instance generics
-rw-r--r--embassy-nrf/CHANGELOG.md2
-rw-r--r--embassy-nrf/src/usb/mod.rs149
-rw-r--r--examples/nrf52840/src/bin/usb_ethernet.rs2
-rw-r--r--examples/nrf52840/src/bin/usb_serial.rs6
-rw-r--r--examples/nrf52840/src/bin/usb_serial_multitask.rs2
-rw-r--r--examples/nrf52840/src/bin/usb_serial_winusb.rs6
6 files changed, 87 insertions, 80 deletions
diff --git a/embassy-nrf/CHANGELOG.md b/embassy-nrf/CHANGELOG.md
index b8d03a1f8..21b299f36 100644
--- a/embassy-nrf/CHANGELOG.md
+++ b/embassy-nrf/CHANGELOG.md
@@ -8,7 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
8<!-- next-header --> 8<!-- next-header -->
9## Unreleased - ReleaseDate 9## Unreleased - ReleaseDate
10 10
11- changed: erase Instance type from Spim 11- changed: Remove `T: Instance` generic params in all drivers.
12- changed: nrf54l: Disable glitch detection and enable DC/DC in init. 12- changed: nrf54l: Disable glitch detection and enable DC/DC in init.
13- changed: Add embassy-net-driver-channel implementation for IEEE 802.15.4 13- changed: Add embassy-net-driver-channel implementation for IEEE 802.15.4
14- changed: add persist() method for gpio and ppi 14- changed: add persist() method for gpio and ppi
diff --git a/embassy-nrf/src/usb/mod.rs b/embassy-nrf/src/usb/mod.rs
index c6970fc0f..2a32fe922 100644
--- a/embassy-nrf/src/usb/mod.rs
+++ b/embassy-nrf/src/usb/mod.rs
@@ -86,17 +86,18 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
86} 86}
87 87
88/// USB driver. 88/// USB driver.
89pub struct Driver<'d, T: Instance, V: VbusDetect> { 89pub struct Driver<'d, V: VbusDetect> {
90 _p: Peri<'d, T>, 90 regs: pac::usbd::Usbd,
91 alloc_in: Allocator, 91 alloc_in: Allocator,
92 alloc_out: Allocator, 92 alloc_out: Allocator,
93 vbus_detect: V, 93 vbus_detect: V,
94 _phantom: PhantomData<&'d ()>,
94} 95}
95 96
96impl<'d, T: Instance, V: VbusDetect> Driver<'d, T, V> { 97impl<'d, V: VbusDetect> Driver<'d, V> {
97 /// Create a new USB driver. 98 /// Create a new USB driver.
98 pub fn new( 99 pub fn new<T: Instance>(
99 usb: Peri<'d, T>, 100 _usb: Peri<'d, T>,
100 _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd, 101 _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
101 vbus_detect: V, 102 vbus_detect: V,
102 ) -> Self { 103 ) -> Self {
@@ -104,19 +105,20 @@ impl<'d, T: Instance, V: VbusDetect> Driver<'d, T, V> {
104 unsafe { T::Interrupt::enable() }; 105 unsafe { T::Interrupt::enable() };
105 106
106 Self { 107 Self {
107 _p: usb, 108 regs: crate::pac::USBD,
108 alloc_in: Allocator::new(), 109 alloc_in: Allocator::new(),
109 alloc_out: Allocator::new(), 110 alloc_out: Allocator::new(),
110 vbus_detect, 111 vbus_detect,
112 _phantom: PhantomData,
111 } 113 }
112 } 114 }
113} 115}
114 116
115impl<'d, T: Instance, V: VbusDetect + 'd> driver::Driver<'d> for Driver<'d, T, V> { 117impl<'d, V: VbusDetect + 'd> driver::Driver<'d> for Driver<'d, V> {
116 type EndpointOut = Endpoint<'d, T, Out>; 118 type EndpointOut = Endpoint<'d, Out>;
117 type EndpointIn = Endpoint<'d, T, In>; 119 type EndpointIn = Endpoint<'d, In>;
118 type ControlPipe = ControlPipe<'d, T>; 120 type ControlPipe = ControlPipe<'d>;
119 type Bus = Bus<'d, T, V>; 121 type Bus = Bus<'d, V>;
120 122
121 fn alloc_endpoint_in( 123 fn alloc_endpoint_in(
122 &mut self, 124 &mut self,
@@ -127,12 +129,15 @@ impl<'d, T: Instance, V: VbusDetect + 'd> driver::Driver<'d> for Driver<'d, T, V
127 ) -> Result<Self::EndpointIn, driver::EndpointAllocError> { 129 ) -> Result<Self::EndpointIn, driver::EndpointAllocError> {
128 let index = self.alloc_in.allocate(ep_type, ep_addr)?; 130 let index = self.alloc_in.allocate(ep_type, ep_addr)?;
129 let ep_addr = EndpointAddress::from_parts(index, Direction::In); 131 let ep_addr = EndpointAddress::from_parts(index, Direction::In);
130 Ok(Endpoint::new(EndpointInfo { 132 Ok(Endpoint::new(
131 addr: ep_addr, 133 self.regs,
132 ep_type, 134 EndpointInfo {
133 max_packet_size: packet_size, 135 addr: ep_addr,
134 interval_ms, 136 ep_type,
135 })) 137 max_packet_size: packet_size,
138 interval_ms,
139 },
140 ))
136 } 141 }
137 142
138 fn alloc_endpoint_out( 143 fn alloc_endpoint_out(
@@ -144,39 +149,45 @@ impl<'d, T: Instance, V: VbusDetect + 'd> driver::Driver<'d> for Driver<'d, T, V
144 ) -> Result<Self::EndpointOut, driver::EndpointAllocError> { 149 ) -> Result<Self::EndpointOut, driver::EndpointAllocError> {
145 let index = self.alloc_out.allocate(ep_type, ep_addr)?; 150 let index = self.alloc_out.allocate(ep_type, ep_addr)?;
146 let ep_addr = EndpointAddress::from_parts(index, Direction::Out); 151 let ep_addr = EndpointAddress::from_parts(index, Direction::Out);
147 Ok(Endpoint::new(EndpointInfo { 152 Ok(Endpoint::new(
148 addr: ep_addr, 153 self.regs,
149 ep_type, 154 EndpointInfo {
150 max_packet_size: packet_size, 155 addr: ep_addr,
151 interval_ms, 156 ep_type,
152 })) 157 max_packet_size: packet_size,
158 interval_ms,
159 },
160 ))
153 } 161 }
154 162
155 fn start(self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) { 163 fn start(self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
156 ( 164 (
157 Bus { 165 Bus {
158 _p: unsafe { self._p.clone_unchecked() }, 166 regs: self.regs,
159 power_available: false, 167 power_available: false,
160 vbus_detect: self.vbus_detect, 168 vbus_detect: self.vbus_detect,
169 _phantom: PhantomData,
161 }, 170 },
162 ControlPipe { 171 ControlPipe {
163 _p: self._p, 172 regs: self.regs,
164 max_packet_size: control_max_packet_size, 173 max_packet_size: control_max_packet_size,
174 _phantom: PhantomData,
165 }, 175 },
166 ) 176 )
167 } 177 }
168} 178}
169 179
170/// USB bus. 180/// USB bus.
171pub struct Bus<'d, T: Instance, V: VbusDetect> { 181pub struct Bus<'d, V: VbusDetect> {
172 _p: Peri<'d, T>, 182 regs: pac::usbd::Usbd,
173 power_available: bool, 183 power_available: bool,
174 vbus_detect: V, 184 vbus_detect: V,
185 _phantom: PhantomData<&'d ()>,
175} 186}
176 187
177impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> { 188impl<'d, V: VbusDetect> driver::Bus for Bus<'d, V> {
178 async fn enable(&mut self) { 189 async fn enable(&mut self) {
179 let regs = T::regs(); 190 let regs = self.regs;
180 191
181 errata::pre_enable(); 192 errata::pre_enable();
182 193
@@ -215,14 +226,14 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
215 } 226 }
216 227
217 async fn disable(&mut self) { 228 async fn disable(&mut self) {
218 let regs = T::regs(); 229 let regs = self.regs;
219 regs.enable().write(|x| x.set_enable(false)); 230 regs.enable().write(|x| x.set_enable(false));
220 } 231 }
221 232
222 fn poll(&mut self) -> impl Future<Output = Event> { 233 fn poll(&mut self) -> impl Future<Output = Event> {
223 poll_fn(|cx| { 234 poll_fn(|cx| {
224 BUS_WAKER.register(cx.waker()); 235 BUS_WAKER.register(cx.waker());
225 let regs = T::regs(); 236 let regs = self.regs;
226 237
227 if regs.events_usbreset().read() != 0 { 238 if regs.events_usbreset().read() != 0 {
228 regs.events_usbreset().write_value(0); 239 regs.events_usbreset().write_value(0);
@@ -280,7 +291,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
280 } 291 }
281 292
282 fn endpoint_set_stalled(&mut self, ep_addr: EndpointAddress, stalled: bool) { 293 fn endpoint_set_stalled(&mut self, ep_addr: EndpointAddress, stalled: bool) {
283 let regs = T::regs(); 294 let regs = self.regs;
284 if ep_addr.index() == 0 { 295 if ep_addr.index() == 0 {
285 if stalled { 296 if stalled {
286 regs.tasks_ep0stall().write_value(1); 297 regs.tasks_ep0stall().write_value(1);
@@ -298,7 +309,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
298 } 309 }
299 310
300 fn endpoint_is_stalled(&mut self, ep_addr: EndpointAddress) -> bool { 311 fn endpoint_is_stalled(&mut self, ep_addr: EndpointAddress) -> bool {
301 let regs = T::regs(); 312 let regs = self.regs;
302 let i = ep_addr.index(); 313 let i = ep_addr.index();
303 match ep_addr.direction() { 314 match ep_addr.direction() {
304 Direction::Out => regs.halted().epout(i).read().getstatus() == vals::Getstatus::HALTED, 315 Direction::Out => regs.halted().epout(i).read().getstatus() == vals::Getstatus::HALTED,
@@ -307,7 +318,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
307 } 318 }
308 319
309 fn endpoint_set_enabled(&mut self, ep_addr: EndpointAddress, enabled: bool) { 320 fn endpoint_set_enabled(&mut self, ep_addr: EndpointAddress, enabled: bool) {
310 let regs = T::regs(); 321 let regs = self.regs;
311 322
312 let i = ep_addr.index(); 323 let i = ep_addr.index();
313 let mask = 1 << i; 324 let mask = 1 << i;
@@ -359,7 +370,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
359 370
360 #[inline] 371 #[inline]
361 async fn remote_wakeup(&mut self) -> Result<(), Unsupported> { 372 async fn remote_wakeup(&mut self) -> Result<(), Unsupported> {
362 let regs = T::regs(); 373 let regs = self.regs;
363 374
364 if regs.lowpower().read().lowpower() == vals::Lowpower::LOW_POWER { 375 if regs.lowpower().read().lowpower() == vals::Lowpower::LOW_POWER {
365 errata::pre_wakeup(); 376 errata::pre_wakeup();
@@ -368,7 +379,7 @@ impl<'d, T: Instance, V: VbusDetect> driver::Bus for Bus<'d, T, V> {
368 379
369 poll_fn(|cx| { 380 poll_fn(|cx| {
370 BUS_WAKER.register(cx.waker()); 381 BUS_WAKER.register(cx.waker());
371 let regs = T::regs(); 382 let regs = self.regs;
372 let r = regs.eventcause().read(); 383 let r = regs.eventcause().read();
373 384
374 if regs.events_usbreset().read() != 0 { 385 if regs.events_usbreset().read() != 0 {
@@ -441,21 +452,23 @@ impl EndpointDir for Out {
441} 452}
442 453
443/// USB endpoint. 454/// USB endpoint.
444pub struct Endpoint<'d, T: Instance, Dir> { 455pub struct Endpoint<'d, Dir> {
445 _phantom: PhantomData<(&'d mut T, Dir)>, 456 regs: pac::usbd::Usbd,
446 info: EndpointInfo, 457 info: EndpointInfo,
458 _phantom: PhantomData<(&'d (), Dir)>,
447} 459}
448 460
449impl<'d, T: Instance, Dir> Endpoint<'d, T, Dir> { 461impl<'d, Dir> Endpoint<'d, Dir> {
450 fn new(info: EndpointInfo) -> Self { 462 fn new(regs: pac::usbd::Usbd, info: EndpointInfo) -> Self {
451 Self { 463 Self {
464 regs,
452 info, 465 info,
453 _phantom: PhantomData, 466 _phantom: PhantomData,
454 } 467 }
455 } 468 }
456} 469}
457 470
458impl<'d, T: Instance, Dir: EndpointDir> driver::Endpoint for Endpoint<'d, T, Dir> { 471impl<'d, Dir: EndpointDir> driver::Endpoint for Endpoint<'d, Dir> {
459 fn info(&self) -> &EndpointInfo { 472 fn info(&self) -> &EndpointInfo {
460 &self.info 473 &self.info
461 } 474 }
@@ -466,14 +479,14 @@ impl<'d, T: Instance, Dir: EndpointDir> driver::Endpoint for Endpoint<'d, T, Dir
466} 479}
467 480
468#[allow(private_bounds)] 481#[allow(private_bounds)]
469impl<'d, T: Instance, Dir: EndpointDir> Endpoint<'d, T, Dir> { 482impl<'d, Dir: EndpointDir> Endpoint<'d, Dir> {
470 fn wait_enabled_state(&mut self, state: bool) -> impl Future<Output = ()> { 483 fn wait_enabled_state(&mut self, state: bool) -> impl Future<Output = ()> + use<'_, 'd, Dir> {
471 let i = self.info.addr.index(); 484 let i = self.info.addr.index();
472 assert!(i != 0); 485 assert!(i != 0);
473 486
474 poll_fn(move |cx| { 487 poll_fn(move |cx| {
475 Dir::waker(i).register(cx.waker()); 488 Dir::waker(i).register(cx.waker());
476 if Dir::is_enabled(T::regs(), i) == state { 489 if Dir::is_enabled(self.regs, i) == state {
477 Poll::Ready(()) 490 Poll::Ready(())
478 } else { 491 } else {
479 Poll::Pending 492 Poll::Pending
@@ -482,12 +495,12 @@ impl<'d, T: Instance, Dir: EndpointDir> Endpoint<'d, T, Dir> {
482 } 495 }
483 496
484 /// Wait for the endpoint to be disabled 497 /// Wait for the endpoint to be disabled
485 pub fn wait_disabled(&mut self) -> impl Future<Output = ()> { 498 pub fn wait_disabled(&mut self) -> impl Future<Output = ()> + use<'_, 'd, Dir> {
486 self.wait_enabled_state(false) 499 self.wait_enabled_state(false)
487 } 500 }
488} 501}
489 502
490impl<'d, T: Instance, Dir> Endpoint<'d, T, Dir> { 503impl<'d, Dir> Endpoint<'d, Dir> {
491 async fn wait_data_ready(&mut self) -> Result<(), ()> 504 async fn wait_data_ready(&mut self) -> Result<(), ()>
492 where 505 where
493 Dir: EndpointDir, 506 Dir: EndpointDir,
@@ -497,7 +510,7 @@ impl<'d, T: Instance, Dir> Endpoint<'d, T, Dir> {
497 poll_fn(|cx| { 510 poll_fn(|cx| {
498 Dir::waker(i).register(cx.waker()); 511 Dir::waker(i).register(cx.waker());
499 let r = READY_ENDPOINTS.load(Ordering::Acquire); 512 let r = READY_ENDPOINTS.load(Ordering::Acquire);
500 if !Dir::is_enabled(T::regs(), i) { 513 if !Dir::is_enabled(self.regs, i) {
501 Poll::Ready(Err(())) 514 Poll::Ready(Err(()))
502 } else if r & Dir::mask(i) != 0 { 515 } else if r & Dir::mask(i) != 0 {
503 Poll::Ready(Ok(())) 516 Poll::Ready(Ok(()))
@@ -514,9 +527,7 @@ impl<'d, T: Instance, Dir> Endpoint<'d, T, Dir> {
514 } 527 }
515} 528}
516 529
517unsafe fn read_dma<T: Instance>(i: usize, buf: &mut [u8]) -> Result<usize, EndpointError> { 530unsafe fn read_dma(regs: pac::usbd::Usbd, i: usize, buf: &mut [u8]) -> Result<usize, EndpointError> {
518 let regs = T::regs();
519
520 // Check that the packet fits into the buffer 531 // Check that the packet fits into the buffer
521 let size = regs.size().epout(i).read().0 as usize; 532 let size = regs.size().epout(i).read().0 as usize;
522 if size > buf.len() { 533 if size > buf.len() {
@@ -539,8 +550,7 @@ unsafe fn read_dma<T: Instance>(i: usize, buf: &mut [u8]) -> Result<usize, Endpo
539 Ok(size) 550 Ok(size)
540} 551}
541 552
542unsafe fn write_dma<T: Instance>(i: usize, buf: &[u8]) { 553unsafe fn write_dma(regs: pac::usbd::Usbd, i: usize, buf: &[u8]) {
543 let regs = T::regs();
544 assert!(buf.len() <= 64); 554 assert!(buf.len() <= 64);
545 555
546 let mut ram_buf: MaybeUninit<[u8; 64]> = MaybeUninit::uninit(); 556 let mut ram_buf: MaybeUninit<[u8; 64]> = MaybeUninit::uninit();
@@ -566,43 +576,44 @@ unsafe fn write_dma<T: Instance>(i: usize, buf: &[u8]) {
566 dma_end(); 576 dma_end();
567} 577}
568 578
569impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> { 579impl<'d> driver::EndpointOut for Endpoint<'d, Out> {
570 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> { 580 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
571 let i = self.info.addr.index(); 581 let i = self.info.addr.index();
572 assert!(i != 0); 582 assert!(i != 0);
573 583
574 self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?; 584 self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?;
575 585
576 unsafe { read_dma::<T>(i, buf) } 586 unsafe { read_dma(self.regs, i, buf) }
577 } 587 }
578} 588}
579 589
580impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> { 590impl<'d> driver::EndpointIn for Endpoint<'d, In> {
581 async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError> { 591 async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError> {
582 let i = self.info.addr.index(); 592 let i = self.info.addr.index();
583 assert!(i != 0); 593 assert!(i != 0);
584 594
585 self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?; 595 self.wait_data_ready().await.map_err(|_| EndpointError::Disabled)?;
586 596
587 unsafe { write_dma::<T>(i, buf) } 597 unsafe { write_dma(self.regs, i, buf) }
588 598
589 Ok(()) 599 Ok(())
590 } 600 }
591} 601}
592 602
593/// USB control pipe. 603/// USB control pipe.
594pub struct ControlPipe<'d, T: Instance> { 604pub struct ControlPipe<'d> {
595 _p: Peri<'d, T>, 605 regs: pac::usbd::Usbd,
596 max_packet_size: u16, 606 max_packet_size: u16,
607 _phantom: PhantomData<&'d ()>,
597} 608}
598 609
599impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> { 610impl<'d> driver::ControlPipe for ControlPipe<'d> {
600 fn max_packet_size(&self) -> usize { 611 fn max_packet_size(&self) -> usize {
601 usize::from(self.max_packet_size) 612 usize::from(self.max_packet_size)
602 } 613 }
603 614
604 async fn setup(&mut self) -> [u8; 8] { 615 async fn setup(&mut self) -> [u8; 8] {
605 let regs = T::regs(); 616 let regs = self.regs;
606 617
607 // Reset shorts 618 // Reset shorts
608 regs.shorts().write(|_| ()); 619 regs.shorts().write(|_| ());
@@ -611,7 +622,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
611 regs.intenset().write(|w| w.set_ep0setup(true)); 622 regs.intenset().write(|w| w.set_ep0setup(true));
612 poll_fn(|cx| { 623 poll_fn(|cx| {
613 EP0_WAKER.register(cx.waker()); 624 EP0_WAKER.register(cx.waker());
614 let regs = T::regs(); 625 let regs = self.regs;
615 if regs.events_ep0setup().read() != 0 { 626 if regs.events_ep0setup().read() != 0 {
616 Poll::Ready(()) 627 Poll::Ready(())
617 } else { 628 } else {
@@ -636,7 +647,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
636 } 647 }
637 648
638 async fn data_out(&mut self, buf: &mut [u8], _first: bool, _last: bool) -> Result<usize, EndpointError> { 649 async fn data_out(&mut self, buf: &mut [u8], _first: bool, _last: bool) -> Result<usize, EndpointError> {
639 let regs = T::regs(); 650 let regs = self.regs;
640 651
641 regs.events_ep0datadone().write_value(0); 652 regs.events_ep0datadone().write_value(0);
642 653
@@ -651,7 +662,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
651 }); 662 });
652 poll_fn(|cx| { 663 poll_fn(|cx| {
653 EP0_WAKER.register(cx.waker()); 664 EP0_WAKER.register(cx.waker());
654 let regs = T::regs(); 665 let regs = self.regs;
655 if regs.events_ep0datadone().read() != 0 { 666 if regs.events_ep0datadone().read() != 0 {
656 Poll::Ready(Ok(())) 667 Poll::Ready(Ok(()))
657 } else if regs.events_usbreset().read() != 0 { 668 } else if regs.events_usbreset().read() != 0 {
@@ -666,17 +677,17 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
666 }) 677 })
667 .await?; 678 .await?;
668 679
669 unsafe { read_dma::<T>(0, buf) } 680 unsafe { read_dma(self.regs, 0, buf) }
670 } 681 }
671 682
672 async fn data_in(&mut self, buf: &[u8], _first: bool, last: bool) -> Result<(), EndpointError> { 683 async fn data_in(&mut self, buf: &[u8], _first: bool, last: bool) -> Result<(), EndpointError> {
673 let regs = T::regs(); 684 let regs = self.regs;
674 regs.events_ep0datadone().write_value(0); 685 regs.events_ep0datadone().write_value(0);
675 686
676 regs.shorts().write(|w| w.set_ep0datadone_ep0status(last)); 687 regs.shorts().write(|w| w.set_ep0datadone_ep0status(last));
677 688
678 // This starts a TX on EP0. events_ep0datadone notifies when done. 689 // This starts a TX on EP0. events_ep0datadone notifies when done.
679 unsafe { write_dma::<T>(0, buf) } 690 unsafe { write_dma(self.regs, 0, buf) }
680 691
681 regs.intenset().write(|w| { 692 regs.intenset().write(|w| {
682 w.set_usbreset(true); 693 w.set_usbreset(true);
@@ -687,7 +698,7 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
687 poll_fn(|cx| { 698 poll_fn(|cx| {
688 cx.waker().wake_by_ref(); 699 cx.waker().wake_by_ref();
689 EP0_WAKER.register(cx.waker()); 700 EP0_WAKER.register(cx.waker());
690 let regs = T::regs(); 701 let regs = self.regs;
691 if regs.events_ep0datadone().read() != 0 { 702 if regs.events_ep0datadone().read() != 0 {
692 Poll::Ready(Ok(())) 703 Poll::Ready(Ok(()))
693 } else if regs.events_usbreset().read() != 0 { 704 } else if regs.events_usbreset().read() != 0 {
@@ -704,12 +715,12 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
704 } 715 }
705 716
706 async fn accept(&mut self) { 717 async fn accept(&mut self) {
707 let regs = T::regs(); 718 let regs = self.regs;
708 regs.tasks_ep0status().write_value(1); 719 regs.tasks_ep0status().write_value(1);
709 } 720 }
710 721
711 async fn reject(&mut self) { 722 async fn reject(&mut self) {
712 let regs = T::regs(); 723 let regs = self.regs;
713 regs.tasks_ep0stall().write_value(1); 724 regs.tasks_ep0stall().write_value(1);
714 } 725 }
715 726
diff --git a/examples/nrf52840/src/bin/usb_ethernet.rs b/examples/nrf52840/src/bin/usb_ethernet.rs
index 87aa4c6c5..a75b967b4 100644
--- a/examples/nrf52840/src/bin/usb_ethernet.rs
+++ b/examples/nrf52840/src/bin/usb_ethernet.rs
@@ -22,7 +22,7 @@ bind_interrupts!(struct Irqs {
22 RNG => rng::InterruptHandler<peripherals::RNG>; 22 RNG => rng::InterruptHandler<peripherals::RNG>;
23}); 23});
24 24
25type MyDriver = Driver<'static, peripherals::USBD, HardwareVbusDetect>; 25type MyDriver = Driver<'static, HardwareVbusDetect>;
26 26
27const MTU: usize = 1514; 27const MTU: usize = 1514;
28 28
diff --git a/examples/nrf52840/src/bin/usb_serial.rs b/examples/nrf52840/src/bin/usb_serial.rs
index 8d05df791..e7c2d0854 100644
--- a/examples/nrf52840/src/bin/usb_serial.rs
+++ b/examples/nrf52840/src/bin/usb_serial.rs
@@ -5,7 +5,7 @@ use defmt::{info, panic};
5use embassy_executor::Spawner; 5use embassy_executor::Spawner;
6use embassy_futures::join::join; 6use embassy_futures::join::join;
7use embassy_nrf::usb::vbus_detect::{HardwareVbusDetect, VbusDetect}; 7use embassy_nrf::usb::vbus_detect::{HardwareVbusDetect, VbusDetect};
8use embassy_nrf::usb::{Driver, Instance}; 8use embassy_nrf::usb::Driver;
9use embassy_nrf::{bind_interrupts, pac, peripherals, usb}; 9use embassy_nrf::{bind_interrupts, pac, peripherals, usb};
10use embassy_usb::class::cdc_acm::{CdcAcmClass, State}; 10use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
11use embassy_usb::driver::EndpointError; 11use embassy_usb::driver::EndpointError;
@@ -89,9 +89,7 @@ impl From<EndpointError> for Disconnected {
89 } 89 }
90} 90}
91 91
92async fn echo<'d, T: Instance + 'd, P: VbusDetect + 'd>( 92async fn echo<'d, V: VbusDetect + 'd>(class: &mut CdcAcmClass<'d, Driver<'d, V>>) -> Result<(), Disconnected> {
93 class: &mut CdcAcmClass<'d, Driver<'d, T, P>>,
94) -> Result<(), Disconnected> {
95 let mut buf = [0; 64]; 93 let mut buf = [0; 64];
96 loop { 94 loop {
97 let n = class.read_packet(&mut buf).await?; 95 let n = class.read_packet(&mut buf).await?;
diff --git a/examples/nrf52840/src/bin/usb_serial_multitask.rs b/examples/nrf52840/src/bin/usb_serial_multitask.rs
index 00a91a233..b6a983854 100644
--- a/examples/nrf52840/src/bin/usb_serial_multitask.rs
+++ b/examples/nrf52840/src/bin/usb_serial_multitask.rs
@@ -17,7 +17,7 @@ bind_interrupts!(struct Irqs {
17 CLOCK_POWER => usb::vbus_detect::InterruptHandler; 17 CLOCK_POWER => usb::vbus_detect::InterruptHandler;
18}); 18});
19 19
20type MyDriver = Driver<'static, peripherals::USBD, HardwareVbusDetect>; 20type MyDriver = Driver<'static, HardwareVbusDetect>;
21 21
22#[embassy_executor::task] 22#[embassy_executor::task]
23async fn usb_task(mut device: UsbDevice<'static, MyDriver>) { 23async fn usb_task(mut device: UsbDevice<'static, MyDriver>) {
diff --git a/examples/nrf52840/src/bin/usb_serial_winusb.rs b/examples/nrf52840/src/bin/usb_serial_winusb.rs
index 8a20ce673..e30e08a01 100644
--- a/examples/nrf52840/src/bin/usb_serial_winusb.rs
+++ b/examples/nrf52840/src/bin/usb_serial_winusb.rs
@@ -5,7 +5,7 @@ use defmt::{info, panic};
5use embassy_executor::Spawner; 5use embassy_executor::Spawner;
6use embassy_futures::join::join; 6use embassy_futures::join::join;
7use embassy_nrf::usb::vbus_detect::{HardwareVbusDetect, VbusDetect}; 7use embassy_nrf::usb::vbus_detect::{HardwareVbusDetect, VbusDetect};
8use embassy_nrf::usb::{Driver, Instance}; 8use embassy_nrf::usb::Driver;
9use embassy_nrf::{bind_interrupts, pac, peripherals, usb}; 9use embassy_nrf::{bind_interrupts, pac, peripherals, usb};
10use embassy_usb::class::cdc_acm::{CdcAcmClass, State}; 10use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
11use embassy_usb::driver::EndpointError; 11use embassy_usb::driver::EndpointError;
@@ -108,9 +108,7 @@ impl From<EndpointError> for Disconnected {
108 } 108 }
109} 109}
110 110
111async fn echo<'d, T: Instance + 'd, P: VbusDetect + 'd>( 111async fn echo<'d, V: VbusDetect + 'd>(class: &mut CdcAcmClass<'d, Driver<'d, V>>) -> Result<(), Disconnected> {
112 class: &mut CdcAcmClass<'d, Driver<'d, T, P>>,
113) -> Result<(), Disconnected> {
114 let mut buf = [0; 64]; 112 let mut buf = [0; 64];
115 loop { 113 loop {
116 let n = class.read_packet(&mut buf).await?; 114 let n = class.read_packet(&mut buf).await?;