diff options
| author | Dario Nieuwenhuis <[email protected]> | 2021-01-06 18:06:23 +0100 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-01-06 18:06:23 +0100 |
| commit | 896eb0ed5246a5888dda0c3985fc9147e83ba8f0 (patch) | |
| tree | 7fc857bc647fe8626c7d80e4bc03199ebdce5b5f | |
| parent | 61a7cf5c3d08f4e68d7136a4b9b9bf17c8538b97 (diff) | |
| parent | 66622de82a3406fbd943194701bea63453d00c35 (diff) | |
Merge pull request #16 from xoviat/fix-interrupts
fix set_handler context
| -rw-r--r-- | embassy-stm32f4/src/serial.rs | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/embassy-stm32f4/src/serial.rs b/embassy-stm32f4/src/serial.rs index cc55ef325..01348e32b 100644 --- a/embassy-stm32f4/src/serial.rs +++ b/embassy-stm32f4/src/serial.rs | |||
| @@ -88,9 +88,9 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> { | |||
| 88 | let (usart, _) = serial.release(); | 88 | let (usart, _) = serial.release(); |
| 89 | 89 | ||
| 90 | // Register ISR | 90 | // Register ISR |
| 91 | tx_int.set_handler(Self::on_tx_irq); | 91 | tx_int.set_handler(Self::on_tx_irq, core::ptr::null_mut()); |
| 92 | rx_int.set_handler(Self::on_rx_irq); | 92 | rx_int.set_handler(Self::on_rx_irq, core::ptr::null_mut()); |
| 93 | usart_int.set_handler(Self::on_rx_irq); | 93 | usart_int.set_handler(Self::on_rx_irq, core::ptr::null_mut()); |
| 94 | // usart_int.unpend(); | 94 | // usart_int.unpend(); |
| 95 | // usart_int.enable(); | 95 | // usart_int.enable(); |
| 96 | 96 | ||
| @@ -106,7 +106,7 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> { | |||
| 106 | } | 106 | } |
| 107 | } | 107 | } |
| 108 | 108 | ||
| 109 | unsafe fn on_tx_irq() { | 109 | unsafe fn on_tx_irq(_ctx: *mut ()) { |
| 110 | let s = &(*INSTANCE); | 110 | let s = &(*INSTANCE); |
| 111 | 111 | ||
| 112 | s.tx_int.disable(); | 112 | s.tx_int.disable(); |
| @@ -114,7 +114,7 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> { | |||
| 114 | STATE.tx_int.signal(()); | 114 | STATE.tx_int.signal(()); |
| 115 | } | 115 | } |
| 116 | 116 | ||
| 117 | unsafe fn on_rx_irq() { | 117 | unsafe fn on_rx_irq(_ctx: *mut ()) { |
| 118 | let s = &(*INSTANCE); | 118 | let s = &(*INSTANCE); |
| 119 | 119 | ||
| 120 | atomic::compiler_fence(Ordering::Acquire); | 120 | atomic::compiler_fence(Ordering::Acquire); |
| @@ -125,7 +125,7 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> { | |||
| 125 | STATE.rx_int.signal(()); | 125 | STATE.rx_int.signal(()); |
| 126 | } | 126 | } |
| 127 | 127 | ||
| 128 | unsafe fn on_usart_irq() { | 128 | unsafe fn on_usart_irq(_ctx: *mut ()) { |
| 129 | let s = &(*INSTANCE); | 129 | let s = &(*INSTANCE); |
| 130 | 130 | ||
| 131 | atomic::compiler_fence(Ordering::Acquire); | 131 | atomic::compiler_fence(Ordering::Acquire); |
