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authorDario Nieuwenhuis <[email protected]>2022-01-04 11:22:08 +0100
committerDario Nieuwenhuis <[email protected]>2022-01-04 13:31:30 +0100
commit89b009b11d7c45533f53a41c6586ba514cf7be58 (patch)
tree70c550e647b2a1754b50b20cd365bcc67939986d
parent5d2f40b337da8bd6af93425d8a1dcc9229fe1f6d (diff)
stm32h7/rcc: remove unneeded DMA enable settings.
These are automatically enabled by dma::init().
-rw-r--r--embassy-stm32/src/rcc/h7/mod.rs10
-rw-r--r--examples/stm32h7/src/bin/camera.rs2
-rw-r--r--examples/stm32h7/src/example_common.rs1
3 files changed, 0 insertions, 13 deletions
diff --git a/embassy-stm32/src/rcc/h7/mod.rs b/embassy-stm32/src/rcc/h7/mod.rs
index be7f440a1..cd493a80a 100644
--- a/embassy-stm32/src/rcc/h7/mod.rs
+++ b/embassy-stm32/src/rcc/h7/mod.rs
@@ -72,8 +72,6 @@ pub struct Config {
72 pub pll1: PllConfig, 72 pub pll1: PllConfig,
73 pub pll2: PllConfig, 73 pub pll2: PllConfig,
74 pub pll3: PllConfig, 74 pub pll3: PllConfig,
75 pub enable_dma1: bool,
76 pub enable_dma2: bool,
77} 75}
78 76
79pub struct Rcc<'d> { 77pub struct Rcc<'d> {
@@ -331,14 +329,6 @@ impl<'d> Rcc<'d> {
331 }); 329 });
332 while !SYSCFG.cccsr().read().ready() {} 330 while !SYSCFG.cccsr().read().ready() {}
333 331
334 if self.config.enable_dma1 {
335 RCC.ahb1enr().modify(|w| w.set_dma1en(true));
336 }
337
338 if self.config.enable_dma2 {
339 RCC.ahb1enr().modify(|w| w.set_dma2en(true));
340 }
341
342 CoreClocks { 332 CoreClocks {
343 hclk: Hertz(rcc_hclk), 333 hclk: Hertz(rcc_hclk),
344 pclk1: Hertz(rcc_pclk1), 334 pclk1: Hertz(rcc_pclk1),
diff --git a/examples/stm32h7/src/bin/camera.rs b/examples/stm32h7/src/bin/camera.rs
index 2fa742b83..d94592071 100644
--- a/examples/stm32h7/src/bin/camera.rs
+++ b/examples/stm32h7/src/bin/camera.rs
@@ -34,8 +34,6 @@ pub fn config() -> Config {
34 config.rcc.sys_ck = Some(400.mhz().into()); 34 config.rcc.sys_ck = Some(400.mhz().into());
35 config.rcc.hclk = Some(400.mhz().into()); 35 config.rcc.hclk = Some(400.mhz().into());
36 config.rcc.pll1.q_ck = Some(100.mhz().into()); 36 config.rcc.pll1.q_ck = Some(100.mhz().into());
37 config.rcc.enable_dma1 = true;
38 config.rcc.enable_dma2 = true;
39 config.rcc.pclk1 = Some(100.mhz().into()); 37 config.rcc.pclk1 = Some(100.mhz().into());
40 config.rcc.pclk2 = Some(100.mhz().into()); 38 config.rcc.pclk2 = Some(100.mhz().into());
41 config.rcc.pclk3 = Some(100.mhz().into()); 39 config.rcc.pclk3 = Some(100.mhz().into());
diff --git a/examples/stm32h7/src/example_common.rs b/examples/stm32h7/src/example_common.rs
index 2e26730fa..524bee6d9 100644
--- a/examples/stm32h7/src/example_common.rs
+++ b/examples/stm32h7/src/example_common.rs
@@ -23,6 +23,5 @@ pub fn config() -> Config {
23 let mut config = Config::default(); 23 let mut config = Config::default();
24 config.rcc.sys_ck = Some(400.mhz().into()); 24 config.rcc.sys_ck = Some(400.mhz().into());
25 config.rcc.pll1.q_ck = Some(100.mhz().into()); 25 config.rcc.pll1.q_ck = Some(100.mhz().into());
26 config.rcc.enable_dma1 = true;
27 config 26 config
28} 27}