aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorCarl St-Laurent <[email protected]>2023-06-08 20:46:48 -0400
committerCarl St-Laurent <[email protected]>2023-06-08 20:46:48 -0400
commit8ddeaddc674871db2125a7462c5b18eef938f497 (patch)
tree31f2fef109bc07d6e4ff7991f80fd4cc0ca8bd95
parent0915fb73b252b2b8ba6d3190c2537c3839246ec2 (diff)
Rename to follow ref manual and CubeIDE
-rw-r--r--embassy-stm32/src/rcc/g4.rs20
-rw-r--r--examples/stm32g4/src/bin/pll.rs4
2 files changed, 12 insertions, 12 deletions
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 3ba9e7eb0..2b52416b2 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -17,7 +17,7 @@ pub const LSI_FREQ: Hertz = Hertz(32_000);
17pub enum ClockSrc { 17pub enum ClockSrc {
18 HSE(Hertz), 18 HSE(Hertz),
19 HSI16, 19 HSI16,
20 PLL(PllSrc, PllM, PllN, PllClkDiv), 20 PLLCLK(PllSrc, PllM, PllN, PllR),
21} 21}
22 22
23/// AHB prescaler 23/// AHB prescaler
@@ -61,27 +61,27 @@ impl Into<Pllsrc> for PllSrc {
61} 61}
62 62
63#[derive(Clone, Copy)] 63#[derive(Clone, Copy)]
64pub enum PllClkDiv { 64pub enum PllR {
65 Div2, 65 Div2,
66 Div4, 66 Div4,
67 Div6, 67 Div6,
68 Div8, 68 Div8,
69} 69}
70 70
71impl PllClkDiv { 71impl PllR {
72 pub fn to_div(self) -> u32 { 72 pub fn to_div(self) -> u32 {
73 let val: u8 = self.into(); 73 let val: u8 = self.into();
74 (val as u32 + 1) * 2 74 (val as u32 + 1) * 2
75 } 75 }
76} 76}
77 77
78impl From<PllClkDiv> for u8 { 78impl From<PllR> for u8 {
79 fn from(val: PllClkDiv) -> u8 { 79 fn from(val: PllR) -> u8 {
80 match val { 80 match val {
81 PllClkDiv::Div2 => 0b00, 81 PllR::Div2 => 0b00,
82 PllClkDiv::Div4 => 0b01, 82 PllR::Div4 => 0b01,
83 PllClkDiv::Div6 => 0b10, 83 PllR::Div6 => 0b10,
84 PllClkDiv::Div8 => 0b11, 84 PllR::Div8 => 0b11,
85 } 85 }
86 } 86 }
87} 87}
@@ -260,7 +260,7 @@ pub(crate) unsafe fn init(config: Config) {
260 260
261 (freq.0, Sw::HSE) 261 (freq.0, Sw::HSE)
262 } 262 }
263 ClockSrc::PLL(src, prediv, mul, div) => { 263 ClockSrc::PLLCLK(src, prediv, mul, div) => {
264 let src_freq = match src { 264 let src_freq = match src {
265 PllSrc::HSI16 => { 265 PllSrc::HSI16 => {
266 // Enable HSI16 as clock source for PLL 266 // Enable HSI16 as clock source for PLL
diff --git a/examples/stm32g4/src/bin/pll.rs b/examples/stm32g4/src/bin/pll.rs
index bde30c284..8cee41e9b 100644
--- a/examples/stm32g4/src/bin/pll.rs
+++ b/examples/stm32g4/src/bin/pll.rs
@@ -4,7 +4,7 @@
4 4
5use defmt::*; 5use defmt::*;
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7use embassy_stm32::rcc::{ClockSrc, PllClkDiv, PllM, PllN, PllSrc}; 7use embassy_stm32::rcc::{ClockSrc, PllM, PllN, PllR, PllSrc};
8use embassy_stm32::Config; 8use embassy_stm32::Config;
9use embassy_time::{Duration, Timer}; 9use embassy_time::{Duration, Timer};
10use {defmt_rtt as _, panic_probe as _}; 10use {defmt_rtt as _, panic_probe as _};
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
14 let mut config = Config::default(); 14 let mut config = Config::default();
15 15
16 // Configure PLL to max frequency of 170 MHz 16 // Configure PLL to max frequency of 170 MHz
17 config.rcc.mux = ClockSrc::PLL(PllSrc::HSI16, PllM::Div4, PllN::Mul85, PllClkDiv::Div2); 17 config.rcc.mux = ClockSrc::PLLCLK(PllSrc::HSI16, PllM::Div4, PllN::Mul85, PllR::Div2);
18 18
19 let _p = embassy_stm32::init(config); 19 let _p = embassy_stm32::init(config);
20 info!("Hello World!"); 20 info!("Hello World!");