diff options
| author | pennae <[email protected]> | 2023-05-02 08:34:36 +0200 |
|---|---|---|
| committer | pennae <[email protected]> | 2023-05-02 08:43:04 +0200 |
| commit | 8fc92fdf6285190a1ba5ddf356958d49ed4225a3 (patch) | |
| tree | b15f345b46f59bd9fb9cb6bf6b115dd96ee8f7d8 | |
| parent | c6424fdc112776b5ceeef4a01c56b1479c2901c5 (diff) | |
rp/gpio: drop critical_section use
we don't need critical sections if we just use atomic access aliases.
| -rw-r--r-- | embassy-rp/src/gpio.rs | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs index 7a86418aa..66b9af04b 100644 --- a/embassy-rp/src/gpio.rs +++ b/embassy-rp/src/gpio.rs | |||
| @@ -9,7 +9,7 @@ use embassy_sync::waitqueue::AtomicWaker; | |||
| 9 | 9 | ||
| 10 | use crate::pac::common::{Reg, RW}; | 10 | use crate::pac::common::{Reg, RW}; |
| 11 | use crate::pac::SIO; | 11 | use crate::pac::SIO; |
| 12 | use crate::{interrupt, pac, peripherals, Peripheral}; | 12 | use crate::{interrupt, pac, peripherals, Peripheral, RegExt}; |
| 13 | 13 | ||
| 14 | const PIN_COUNT: usize = 30; | 14 | const PIN_COUNT: usize = 30; |
| 15 | const NEW_AW: AtomicWaker = AtomicWaker::new(); | 15 | const NEW_AW: AtomicWaker = AtomicWaker::new(); |
| @@ -158,13 +158,11 @@ unsafe fn IO_IRQ_BANK0() { | |||
| 158 | // we can just clear all interrupt enables for that pin without having | 158 | // we can just clear all interrupt enables for that pin without having |
| 159 | // to check which event was signalled. | 159 | // to check which event was signalled. |
| 160 | if event != 0 { | 160 | if event != 0 { |
| 161 | critical_section::with(|_| { | 161 | proc_intx.inte(pin / 8).write_clear(|w| { |
| 162 | proc_intx.inte(pin / 8).modify(|w| { | 162 | w.set_edge_high(pin_group, true); |
| 163 | w.set_edge_high(pin_group, false); | 163 | w.set_edge_low(pin_group, true); |
| 164 | w.set_edge_low(pin_group, false); | 164 | w.set_level_high(pin_group, true); |
| 165 | w.set_level_high(pin_group, false); | 165 | w.set_level_low(pin_group, true); |
| 166 | w.set_level_low(pin_group, false); | ||
| 167 | }); | ||
| 168 | }); | 166 | }); |
| 169 | INTERRUPT_WAKERS[pin as usize].wake(); | 167 | INTERRUPT_WAKERS[pin as usize].wake(); |
| 170 | } | 168 | } |
| @@ -202,8 +200,9 @@ impl<'d, T: Pin> InputFuture<'d, T> { | |||
| 202 | // Each INTR register is divided into 8 groups, one group for each | 200 | // Each INTR register is divided into 8 groups, one group for each |
| 203 | // pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, | 201 | // pin, and each group consists of LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, |
| 204 | // and EGDE_HIGH. | 202 | // and EGDE_HIGH. |
| 205 | critical_section::with(|_| { | 203 | pin.int_proc() |
| 206 | pin.int_proc().inte((pin.pin() / 8) as usize).modify(|w| match level { | 204 | .inte((pin.pin() / 8) as usize) |
| 205 | .write_set(|w| match level { | ||
| 207 | InterruptTrigger::LevelHigh => { | 206 | InterruptTrigger::LevelHigh => { |
| 208 | trace!("InputFuture::new enable LevelHigh for pin {}", pin.pin()); | 207 | trace!("InputFuture::new enable LevelHigh for pin {}", pin.pin()); |
| 209 | w.set_level_high(pin_group, true); | 208 | w.set_level_high(pin_group, true); |
| @@ -222,7 +221,6 @@ impl<'d, T: Pin> InputFuture<'d, T> { | |||
| 222 | w.set_edge_low(pin_group, true); | 221 | w.set_edge_low(pin_group, true); |
| 223 | } | 222 | } |
| 224 | }); | 223 | }); |
| 225 | }); | ||
| 226 | 224 | ||
| 227 | irq.enable(); | 225 | irq.enable(); |
| 228 | } | 226 | } |
