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authorelagil <[email protected]>2025-03-15 20:24:02 +0100
committerelagil <[email protected]>2025-03-15 20:24:14 +0100
commit8fef488738531b419565c35185dd82553ff52a80 (patch)
tree5d98ad4b1cbaab582e1a70e70b9c9ddbcd15a570
parent0b468ef29cc67e05aae01031604b746b1f21ffcd (diff)
refactor: USB read function restructure
-rw-r--r--embassy-stm32/src/usb/usb.rs33
1 files changed, 14 insertions, 19 deletions
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index cb97169ee..4675b3f1a 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -868,31 +868,26 @@ impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
868 868
869 let regs = T::regs(); 869 let regs = T::regs();
870 870
871 let packet_buffer = if self.info.ep_type == EndpointType::Isochronous { 871 let rx_len = if self.info.ep_type == EndpointType::Isochronous {
872 // Find the buffer, which is currently in use. Read from the OTHER buffer. 872 // Find the buffer, which is currently in use. Read from the OTHER buffer.
873 if regs.epr(index).read().dtog_rx() { 873 let packet_buffer = if regs.epr(index).read().dtog_rx() {
874 PacketBuffer::Tx 874 PacketBuffer::Tx
875 } else { 875 } else {
876 PacketBuffer::Rx 876 PacketBuffer::Rx
877 } 877 };
878 self.read_data_double_buffered(buf, packet_buffer)?
878 } else { 879 } else {
879 PacketBuffer::Rx 880 regs.epr(index).write(|w| {
880 }; 881 w.set_ep_type(convert_type(self.info.ep_type));
881 882 w.set_ea(self.info.addr.index() as _);
882 let rx_len = self.read_data_double_buffered(buf, packet_buffer)?;
883
884 regs.epr(index).write(|w| {
885 w.set_ep_type(convert_type(self.info.ep_type));
886 w.set_ea(self.info.addr.index() as _);
887 if self.info.ep_type == EndpointType::Isochronous {
888 w.set_stat_rx(Stat::from_bits(0)); // STAT_RX remains `VALID`.
889 } else {
890 w.set_stat_rx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits())); 883 w.set_stat_rx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
891 } 884 w.set_stat_tx(Stat::from_bits(0));
892 w.set_stat_tx(Stat::from_bits(0)); 885 w.set_ctr_rx(true); // don't clear
893 w.set_ctr_rx(true); // don't clear 886 w.set_ctr_tx(true); // don't clear
894 w.set_ctr_tx(true); // don't clear 887 });
895 }); 888
889 self.read_data(buf)?
890 };
896 trace!("READ OK, rx_len = {}", rx_len); 891 trace!("READ OK, rx_len = {}", rx_len);
897 892
898 Ok(rx_len) 893 Ok(rx_len)