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authorTorin Cooper-Bennun <[email protected]>2024-04-17 14:54:47 +0100
committerTorin Cooper-Bennun <[email protected]>2024-04-17 14:57:58 +0100
commit901bdfc7b8d8e1dc5d04b28a69feb50b99d0be57 (patch)
treee6d2f636e3540ac9e6e0bc19e341fb4a38acc45e
parentbab4affe7cd116f44eb378c8f32e58e6993adbf5 (diff)
stm32: can: fd: on_interrupt: simplify, rm redundant code
PED, PEA are never enabled in the interrupt enable code in peripheral.rs; no need to process the flags here
-rw-r--r--embassy-stm32/src/can/fdcan.rs52
1 files changed, 21 insertions, 31 deletions
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index e31821ca2..23a35168b 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -44,50 +44,40 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
44 44
45 let ir = regs.ir().read(); 45 let ir = regs.ir().read();
46 46
47 { 47 if ir.tc() {
48 if ir.tc() { 48 regs.ir().write(|w| w.set_tc(true));
49 regs.ir().write(|w| w.set_tc(true)); 49 }
50 } 50 if ir.tefn() {
51 if ir.tefn() { 51 regs.ir().write(|w| w.set_tefn(true));
52 regs.ir().write(|w| w.set_tefn(true)); 52 }
53 }
54 53
55 match &T::state().tx_mode { 54 match &T::state().tx_mode {
56 TxMode::NonBuffered(waker) => waker.wake(), 55 TxMode::NonBuffered(waker) => waker.wake(),
57 TxMode::ClassicBuffered(buf) => { 56 TxMode::ClassicBuffered(buf) => {
58 if !T::registers().tx_queue_is_full() { 57 if !T::registers().tx_queue_is_full() {
59 match buf.tx_receiver.try_receive() { 58 match buf.tx_receiver.try_receive() {
60 Ok(frame) => { 59 Ok(frame) => {
61 _ = T::registers().write(&frame); 60 _ = T::registers().write(&frame);
62 }
63 Err(_) => {}
64 } 61 }
62 Err(_) => {}
65 } 63 }
66 } 64 }
67 TxMode::FdBuffered(buf) => { 65 }
68 if !T::registers().tx_queue_is_full() { 66 TxMode::FdBuffered(buf) => {
69 match buf.tx_receiver.try_receive() { 67 if !T::registers().tx_queue_is_full() {
70 Ok(frame) => { 68 match buf.tx_receiver.try_receive() {
71 _ = T::registers().write(&frame); 69 Ok(frame) => {
72 } 70 _ = T::registers().write(&frame);
73 Err(_) => {}
74 } 71 }
72 Err(_) => {}
75 } 73 }
76 } 74 }
77 } 75 }
78 } 76 }
79 77
80 if ir.ped() || ir.pea() {
81 regs.ir().write(|w| {
82 w.set_ped(true);
83 w.set_pea(true);
84 });
85 }
86
87 if ir.rfn(0) { 78 if ir.rfn(0) {
88 T::state().rx_mode.on_interrupt::<T>(0); 79 T::state().rx_mode.on_interrupt::<T>(0);
89 } 80 }
90
91 if ir.rfn(1) { 81 if ir.rfn(1) {
92 T::state().rx_mode.on_interrupt::<T>(1); 82 T::state().rx_mode.on_interrupt::<T>(1);
93 } 83 }