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authorxoviat <[email protected]>2020-12-31 16:40:51 -0600
committerxoviat <[email protected]>2020-12-31 16:40:51 -0600
commit925ede848ec1fc3389b5bbd22d98d919c808bfe3 (patch)
tree04a4cbcf293e62f6c0fb401648a9a46dc9393879
parent308756f3663161ec283622e4942770f831cb61b6 (diff)
rename uarte as serial
-rw-r--r--embassy-stm32f4/src/serial.rs44
-rw-r--r--examples-stm32f4/src/serial.rs2
2 files changed, 26 insertions, 20 deletions
diff --git a/embassy-stm32f4/src/serial.rs b/embassy-stm32f4/src/serial.rs
index e414dc020..bb47a9301 100644
--- a/embassy-stm32f4/src/serial.rs
+++ b/embassy-stm32f4/src/serial.rs
@@ -1,4 +1,4 @@
1//! Async low power UARTE. 1//! Async low power Serial.
2//! 2//!
3//! The peripheral is autmatically enabled and disabled as required to save power. 3//! The peripheral is autmatically enabled and disabled as required to save power.
4//! Lowest power consumption can only be guaranteed if the send receive futures 4//! Lowest power consumption can only be guaranteed if the send receive futures
@@ -34,7 +34,7 @@ use crate::hal::rcc::Clocks;
34use crate::hal::serial::config::{ 34use crate::hal::serial::config::{
35 Config as SerialConfig, DmaConfig as SerialDmaConfig, Parity, StopBits, WordLength, 35 Config as SerialConfig, DmaConfig as SerialDmaConfig, Parity, StopBits, WordLength,
36}; 36};
37use crate::hal::serial::{Event as SerialEvent, Serial}; 37use crate::hal::serial::{Event as SerialEvent, Serial as HalSerial};
38use crate::hal::time::Bps; 38use crate::hal::time::Bps;
39 39
40use crate::interrupt; 40use crate::interrupt;
@@ -44,8 +44,8 @@ use crate::pac::{DMA2, USART1};
44 44
45use embedded_hal::digital::v2::OutputPin; 45use embedded_hal::digital::v2::OutputPin;
46 46
47/// Interface to the UARTE peripheral 47/// Interface to the Serial peripheral
48pub struct Uarte<USART: PeriAddress<MemSize = u8>, TSTREAM: Stream, RSTREAM: Stream> { 48pub struct Serial<USART: PeriAddress<MemSize = u8>, TSTREAM: Stream, RSTREAM: Stream> {
49 // tx_transfer: Transfer<Stream7<DMA2>, Channel4, USART1, MemoryToPeripheral, &mut [u8; 20]>, 49 // tx_transfer: Transfer<Stream7<DMA2>, Channel4, USART1, MemoryToPeripheral, &mut [u8; 20]>,
50 // rx_transfer: Transfer<Stream2<DMA2>, Channel4, USART1, PeripheralToMemory, &mut [u8; 20]>, 50 // rx_transfer: Transfer<Stream2<DMA2>, Channel4, USART1, PeripheralToMemory, &mut [u8; 20]>,
51 tx_stream: Option<TSTREAM>, 51 tx_stream: Option<TSTREAM>,
@@ -63,7 +63,7 @@ static STATE: State = State {
63 rx_done: Signal::new(), 63 rx_done: Signal::new(),
64}; 64};
65 65
66impl Uarte<USART1, Stream7<DMA2>, Stream2<DMA2>> { 66impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
67 pub fn new( 67 pub fn new(
68 rxd: PA10<Alternate<AF7>>, 68 rxd: PA10<Alternate<AF7>>,
69 txd: PA9<Alternate<AF7>>, 69 txd: PA9<Alternate<AF7>>,
@@ -73,7 +73,7 @@ impl Uarte<USART1, Stream7<DMA2>, Stream2<DMA2>> {
73 baudrate: Bps, 73 baudrate: Bps,
74 clocks: Clocks, 74 clocks: Clocks,
75 ) -> Self { 75 ) -> Self {
76 let serial = Serial::usart1( 76 let serial = HalSerial::usart1(
77 usart, 77 usart,
78 (txd, rxd), 78 (txd, rxd),
79 SerialConfig { 79 SerialConfig {
@@ -93,7 +93,7 @@ impl Uarte<USART1, Stream7<DMA2>, Stream2<DMA2>> {
93 93
94 let streams = StreamsTuple::new(dma); 94 let streams = StreamsTuple::new(dma);
95 95
96 Uarte { 96 Serial {
97 tx_stream: Some(streams.7), 97 tx_stream: Some(streams.7),
98 rx_stream: Some(streams.2), 98 rx_stream: Some(streams.2),
99 usart: Some(usart), 99 usart: Some(usart),
@@ -126,7 +126,7 @@ impl Uarte<USART1, Stream7<DMA2>, Stream2<DMA2>> {
126 ); 126 );
127 127
128 SendFuture { 128 SendFuture {
129 uarte: self, 129 Serial: self,
130 tx_transfer: Some(tx_transfer), 130 tx_transfer: Some(tx_transfer),
131 // tx_stream: Some(tx_stream), 131 // tx_stream: Some(tx_stream),
132 // usart: Some(usart), 132 // usart: Some(usart),
@@ -165,13 +165,13 @@ impl Uarte<USART1, Stream7<DMA2>, Stream2<DMA2>> {
165 ); 165 );
166 166
167 ReceiveFuture { 167 ReceiveFuture {
168 uarte: self, 168 Serial: self,
169 rx_transfer: Some(rx_transfer), 169 rx_transfer: Some(rx_transfer),
170 } 170 }
171 } 171 }
172} 172}
173 173
174/// Future for the [`LowPowerUarte::send()`] method. 174/// Future for the [`LowPowerSerial::send()`] method.
175pub struct SendFuture< 175pub struct SendFuture<
176 'a, 176 'a,
177 B: WriteBuffer<Word = u8> + 'static, 177 B: WriteBuffer<Word = u8> + 'static,
@@ -180,7 +180,7 @@ pub struct SendFuture<
180 RSTREAM: Stream, 180 RSTREAM: Stream,
181 CHANNEL, 181 CHANNEL,
182> { 182> {
183 uarte: &'a mut Uarte<USART, TSTREAM, RSTREAM>, 183 Serial: &'a mut Serial<USART, TSTREAM, RSTREAM>,
184 tx_transfer: Option<Transfer<TSTREAM, CHANNEL, USART, MemoryToPeripheral, B>>, 184 tx_transfer: Option<Transfer<TSTREAM, CHANNEL, USART, MemoryToPeripheral, B>>,
185} 185}
186 186
@@ -198,13 +198,16 @@ where
198 type Output = (); 198 type Output = ();
199 199
200 fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<()> { 200 fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<()> {
201 let Self { uarte, tx_transfer } = unsafe { self.get_unchecked_mut() }; 201 let Self {
202 Serial,
203 tx_transfer,
204 } = unsafe { self.get_unchecked_mut() };
202 let mut taken = tx_transfer.take().unwrap(); 205 let mut taken = tx_transfer.take().unwrap();
203 if Stream7::<DMA2>::get_transfer_complete_flag() { 206 if Stream7::<DMA2>::get_transfer_complete_flag() {
204 let (tx_stream, usart, buf, _) = taken.free(); 207 let (tx_stream, usart, buf, _) = taken.free();
205 208
206 uarte.tx_stream.replace(tx_stream); 209 Serial.tx_stream.replace(tx_stream);
207 uarte.usart.replace(usart); 210 Serial.usart.replace(usart);
208 211
209 Poll::Ready(()) 212 Poll::Ready(())
210 } else { 213 } else {
@@ -217,7 +220,7 @@ where
217 } 220 }
218} 221}
219 222
220/// Future for the [`Uarte::receive()`] method. 223/// Future for the [`Serial::receive()`] method.
221pub struct ReceiveFuture< 224pub struct ReceiveFuture<
222 'a, 225 'a,
223 B: WriteBuffer<Word = u8> + 'static, 226 B: WriteBuffer<Word = u8> + 'static,
@@ -226,7 +229,7 @@ pub struct ReceiveFuture<
226 RSTREAM: Stream, 229 RSTREAM: Stream,
227 CHANNEL, 230 CHANNEL,
228> { 231> {
229 uarte: &'a mut Uarte<USART, TSTREAM, RSTREAM>, 232 Serial: &'a mut Serial<USART, TSTREAM, RSTREAM>,
230 rx_transfer: Option<Transfer<RSTREAM, CHANNEL, USART, PeripheralToMemory, B>>, 233 rx_transfer: Option<Transfer<RSTREAM, CHANNEL, USART, PeripheralToMemory, B>>,
231} 234}
232 235
@@ -244,14 +247,17 @@ where
244 type Output = B; 247 type Output = B;
245 248
246 fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<B> { 249 fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<B> {
247 let Self { uarte, rx_transfer } = unsafe { self.get_unchecked_mut() }; 250 let Self {
251 Serial,
252 rx_transfer,
253 } = unsafe { self.get_unchecked_mut() };
248 let mut taken = rx_transfer.take().unwrap(); 254 let mut taken = rx_transfer.take().unwrap();
249 255
250 if Stream7::<DMA2>::get_transfer_complete_flag() { 256 if Stream7::<DMA2>::get_transfer_complete_flag() {
251 let (rx_stream, usart, buf, _) = rx_transfer.take().unwrap().free(); 257 let (rx_stream, usart, buf, _) = rx_transfer.take().unwrap().free();
252 258
253 uarte.rx_stream.replace(rx_stream); 259 Serial.rx_stream.replace(rx_stream);
254 uarte.usart.replace(usart); 260 Serial.usart.replace(usart);
255 261
256 Poll::Ready(buf) 262 Poll::Ready(buf)
257 } else { 263 } else {
diff --git a/examples-stm32f4/src/serial.rs b/examples-stm32f4/src/serial.rs
index f7fd525a9..1f5c0fb7a 100644
--- a/examples-stm32f4/src/serial.rs
+++ b/examples-stm32f4/src/serial.rs
@@ -26,7 +26,7 @@ async fn run(dp: stm32::Peripherals, cp: cortex_m::Peripherals) {
26 .pclk1(24.mhz()) 26 .pclk1(24.mhz())
27 .freeze(); 27 .freeze();
28 28
29 let mut serial = serial::Uarte::new( 29 let mut serial = serial::Serial::new(
30 gpioa.pa10.into_alternate_af7(), 30 gpioa.pa10.into_alternate_af7(),
31 gpioa.pa9.into_alternate_af7(), 31 gpioa.pa9.into_alternate_af7(),
32 dp.DMA2, 32 dp.DMA2,