Merge #655

655: common/serial/usb: fix hang when write buffer gets full and then the bus resets. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <[email protected]>

1 files changed, 27 insertions, 5 deletions

diff --git a/embassy-hal-common/src/usb/usb_serial.rs b/embassy-hal-common/src/usb/usb_serial.rs
index 2592d05a6..94f687890 100644
--- a/embassy-hal-common/src/usb/usb_serial.rs
+++ b/embassy-hal-common/src/usb/usb_serial.rs
@@ -167,6 +167,7 @@ impl<'bus, 'a, B: UsbBus> AsyncWrite for UsbSerial<'bus, 'a, B> {
 
         let write_buf = this.write_buf.push_buf();
         if write_buf.is_empty() {
+            trace!("buf full, registering waker");
             this.write_waker.register(cx.waker());
             return Poll::Pending;
         }
@@ -244,10 +245,18 @@ impl<'bus, 'a, B: UsbBus> UsbSerial<'bus, 'a, B> {
         };
 
         if !buf.is_empty() {
+            trace!("writing packet len {}", buf.len());
             let count = match self.inner.write_packet(buf) {
-                Ok(c) => c,
-                Err(UsbError::WouldBlock) => 0,
+                Ok(c) => {
+                    trace!("write packet: OK {}", c);
+                    c
+                }
+                Err(UsbError::WouldBlock) => {
+                    trace!("write packet: WouldBlock");
+                    0
+                }
                 Err(_) => {
+                    trace!("write packet: error");
                     self.write_error = true;
                     return;
                 }
@@ -260,11 +269,20 @@ impl<'bus, 'a, B: UsbBus> UsbSerial<'bus, 'a, B> {
             }
             self.write_buf.pop(count);
         } else if full_size_packets > 0 {
-            if let Err(e) = self.inner.write_packet(&[]) {
-                if !matches!(e, UsbError::WouldBlock) {
+            trace!("writing empty packet");
+            match self.inner.write_packet(&[]) {
+                Ok(_) => {
+                    trace!("write empty packet: OK");
+                }
+                Err(UsbError::WouldBlock) => {
+                    trace!("write empty packet: WouldBlock");
+                    return;
+                }
+                Err(_) => {
+                    trace!("write empty packet: Error");
                     self.write_error = true;
+                    return;
                 }
-                return;
             }
             self.write_state = WriteState::Idle;
         }
@@ -284,10 +302,14 @@ where
         self.read_buf.clear();
         self.write_buf.clear();
         self.write_state = WriteState::Idle;
+        self.read_waker.wake();
+        self.write_waker.wake();
     }
 
     fn endpoint_in_complete(&mut self, addr: EndpointAddress) {
+        trace!("DONE endpoint_in_complete");
         if addr == self.inner.write_ep_address() {
+            trace!("DONE writing packet, waking");
             self.write_waker.wake();
 
             self.flush_write();