stm32: Add i2c v2 transaction test

4 files changed, 109 insertions, 77 deletions

diff --git a/examples/stm32f0/Cargo.toml b/examples/stm32f0/Cargo.toml
index 177dd0ac2..a78873d21 100644
--- a/examples/stm32f0/Cargo.toml
+++ b/examples/stm32f0/Cargo.toml
@@ -16,7 +16,6 @@ panic-probe = { version = "1.0.0", features = ["print-defmt"] }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
-embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
 static_cell = "2"
 portable-atomic = { version = "1.5", features = ["unsafe-assume-single-core"] }
 
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index b92b47be2..fa757e276 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -35,6 +35,7 @@ stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac"
 stm32wba52cg = ["embassy-stm32/stm32wba52cg", "spi-v345", "chrono", "rng", "hash"]
 stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
 stm32f091rc = ["embassy-stm32/stm32f091rc", "cm0", "not-gpdma", "chrono"]
+stm32f072rb = ["embassy-stm32/stm32f072rb", "cm0", "not-gpdma", "chrono"]
 stm32h503rb = ["embassy-stm32/stm32h503rb", "spi-v345", "rng", "stop"]
 stm32h7s3l8 = ["embassy-stm32/stm32h7s3l8", "spi-v345", "rng", "cordic", "hash-v34"] # TODO: fdcan crashes, cryp dma hangs.
 stm32u083rc = ["embassy-stm32/stm32u083rc", "cm0", "rng", "chrono"]
@@ -160,6 +161,11 @@ path = "src/bin/hash.rs"
 required-features = [ "hash",]
 
 [[bin]]
+name = "i2c_v2"
+path = "src/bin/i2c_v2.rs"
+required-features = [ "stm32f072rb",]
+
+[[bin]]
 name = "rng"
 path = "src/bin/rng.rs"
 required-features = [ "rng",]
@@ -285,6 +291,7 @@ build = [
   { target = "thumbv7em-none-eabi", features = ["stm32wl55jc"], artifact-dir = "out/tests/stm32wl55jc" },
   { target = "thumbv7em-none-eabi", features = ["stm32h7s3l8"], artifact-dir = "out/tests/stm32h7s3l8" },
   { target = "thumbv6m-none-eabi", features = ["stm32f091rc"], artifact-dir = "out/tests/stm32f091rc" },
+  { target = "thumbv6m-none-eabi", features = ["stm32f072rb"], artifact-dir = "out/tests/stm32f072rb" },
   { target = "thumbv8m.main-none-eabihf", features = ["stm32h503rb"], artifact-dir = "out/tests/stm32h503rb" },
   { target = "thumbv6m-none-eabi", features = ["stm32u083rc"], artifact-dir = "out/tests/stm32u083rc" }
 ]
diff --git a/examples/stm32f0/src/bin/i2c_transaction_test.rs b/tests/stm32/src/bin/i2c_v2.rs
index 0ecc3e8b1..9a23e28e1 100644
--- a/examples/stm32f0/src/bin/i2c_transaction_test.rs
+++ b/tests/stm32/src/bin/i2c_v2.rs
@@ -1,75 +1,81 @@
 #![no_std]
 #![no_main]
-
-use defmt::*;
+// required-features: stm32f072rb
+//
+// Hardware Setup for NUCLEO-F072RB:
+// - I2C1 pins: PB8 (SCL), PB9 (SDA) on CN5 connector
+// - Connect to I2C slave device (e.g., Digilent Analog Discovery I2C slave, or EEPROM)
+// - Default slave address: 0x50
+// - Pull-up resistors: 4.7kΩ on both SCL and SDA
+// - CN5 Pin 5 (PB8/SCL) and CN5 Pin 9 (PB9/SDA)
+//
+// Analog Discovery Setup:
+// - Configure as I2C Slave at address 0x50
+// - DIO 0: SCL
+// - DIO 1: SDA
+// - Enable pull-ups or use external 4.7kΩ pull-up resistors
+
+#[path = "../common.rs"]
+mod common;
+
+use common::*;
 use embassy_executor::Spawner;
 use embassy_stm32::i2c::{Config, I2c, Master};
 use embassy_stm32::mode::Blocking;
 use embassy_stm32::time::Hertz;
-use embassy_stm32::{bind_interrupts, i2c, peripherals};
-use embassy_time::Timer;
+use embassy_time::block_for;
 use embedded_hal_1::i2c::Operation;
-use {defmt_rtt as _, panic_probe as _};
-
-bind_interrupts!(struct Irqs {
-    I2C1 => i2c::EventInterruptHandler<peripherals::I2C1>, i2c::ErrorInterruptHandler<peripherals::I2C1>;
-});
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
-    // For STM32F072RB on NUCLEO board
-    let p = embassy_stm32::init(Default::default());
+    let p = init();
+    info!("I2C v2 Transaction Test Starting...");
 
-    info!("I2C Transaction Test Starting...");
+    let mut i2c_peri = peri!(p, I2C);
+    let mut scl = peri!(p, I2C_SCL);
+    let mut sda = peri!(p, I2C_SDA);
 
-    // Initialize I2C1: PB6=SCL, PB7=SDA
     let mut config = Config::default();
     config.frequency = Hertz(100_000);
+
     let mut i2c = I2c::new_blocking(
-        p.I2C1,
-        p.PB8,  // SCL
-        p.PB9,  // SDA
+        i2c_peri.reborrow(),
+        scl.reborrow(),
+        sda.reborrow(),
         config,
     );
 
+    // I2C slave address for Analog Discovery or test EEPROM
     let slave_addr = 0x50u8;
 
-    // Wait for devices to initialize
-    Timer::after_millis(100).await;
+    // Wait for slave device to be ready
+    block_for(embassy_time::Duration::from_millis(100));
 
     info!("=== Test 1: Consecutive Writes (Should Merge) ===");
     test_consecutive_writes(&mut i2c, slave_addr);
-    Timer::after_millis(500).await;
 
     info!("=== Test 2: Consecutive Reads (Should Merge) ===");
     test_consecutive_reads(&mut i2c, slave_addr);
-    Timer::after_millis(500).await;
 
     info!("=== Test 3: Write then Read (RESTART) ===");
     test_write_then_read(&mut i2c, slave_addr);
-    Timer::after_millis(500).await;
 
     info!("=== Test 4: Read then Write (RESTART) ===");
     test_read_then_write(&mut i2c, slave_addr);
-    Timer::after_millis(500).await;
 
     info!("=== Test 5: Complex Mixed Sequence ===");
     test_mixed_sequence(&mut i2c, slave_addr);
-    Timer::after_millis(500).await;
 
     info!("=== Test 6: Single Operations ===");
     test_single_operations(&mut i2c, slave_addr);
 
-    info!("All tests complete!");
-
-    loop {
-        Timer::after_secs(1).await;
-    }
+    info!("Test OK");
+    cortex_m::asm::bkpt();
 }
 
-fn test_consecutive_writes(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
+fn test_consecutive_writes(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected on bus: START, ADDR+W, data1, data2, data3, STOP
-    // NO intermediate RESTART/STOP between writes
+    // NO intermediate RESTART/STOP between writes - they should be merged
     let data1 = [0x10, 0x11, 0x12];
     let data2 = [0x20, 0x21];
     let data3 = [0x30, 0x31, 0x32, 0x33];
@@ -81,17 +87,17 @@ fn test_consecutive_writes(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
     ];
 
     match i2c.blocking_transaction(addr, &mut ops) {
-        Ok(_) => info!("✓ Consecutive writes succeeded"),
-        Err(e) => warn!("✗ Consecutive writes failed: {:?}", e),
+        Ok(_) => info!("✓ Consecutive writes succeeded (merged 9 bytes)"),
+        Err(e) => {
+            error!("✗ Consecutive writes failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive writes");
+        }
     }
-
-    info!("Expected: START, ADDR+W, [9 bytes], STOP");
-    info!("Check Analog Discovery: No RESTART between writes");
 }
 
-fn test_consecutive_reads(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
+fn test_consecutive_reads(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected on bus: START, ADDR+R, data1, data2, data3, NACK, STOP
-    // NO intermediate RESTART/STOP between reads
+    // NO intermediate RESTART/STOP between reads - they should be merged
     let mut buf1 = [0u8; 4];
     let mut buf2 = [0u8; 3];
     let mut buf3 = [0u8; 2];
@@ -104,65 +110,59 @@ fn test_consecutive_reads(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
 
     match i2c.blocking_transaction(addr, &mut ops) {
         Ok(_) => {
-            info!("✓ Consecutive reads succeeded");
+            info!("✓ Consecutive reads succeeded (merged 9 bytes)");
             info!("  buf1: {:02x}", buf1);
             info!("  buf2: {:02x}", buf2);
             info!("  buf3: {:02x}", buf3);
         }
-        Err(e) => warn!("✗ Consecutive reads failed: {:?}", e),
+        Err(e) => {
+            error!("✗ Consecutive reads failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive reads");
+        }
     }
-
-    info!("Expected: START, ADDR+R, [9 bytes], NACK on last, STOP");
-    info!("Check Analog Discovery: No RESTART between reads");
 }
 
-fn test_write_then_read(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
+fn test_write_then_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected: START, ADDR+W, data, RESTART, ADDR+R, data, NACK, STOP
     let write_data = [0xAA, 0xBB];
     let mut read_buf = [0u8; 4];
 
-    let mut ops = [
-        Operation::Write(&write_data),
-        Operation::Read(&mut read_buf),
-    ];
+    let mut ops = [Operation::Write(&write_data), Operation::Read(&mut read_buf)];
 
     match i2c.blocking_transaction(addr, &mut ops) {
         Ok(_) => {
-            info!("✓ Write-then-read succeeded");
+            info!("✓ Write-then-read succeeded with RESTART");
             info!("  Written: {:02x}", write_data);
             info!("  Read: {:02x}", read_buf);
         }
-        Err(e) => warn!("✗ Write-then-read failed: {:?}", e),
+        Err(e) => {
+            error!("✗ Write-then-read failed: {:?}", e);
+            defmt::panic!("Test failed: write-then-read");
+        }
     }
-
-    info!("Expected: START, ADDR+W, [2 bytes], RESTART, ADDR+R, [4 bytes], NACK, STOP");
-    info!("Check Analog Discovery: RESTART between write and read");
 }
 
-fn test_read_then_write(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
+fn test_read_then_write(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected: START, ADDR+R, data, NACK, RESTART, ADDR+W, data, STOP
     let mut read_buf = [0u8; 3];
     let write_data = [0xCC, 0xDD, 0xEE];
 
-    let mut ops = [
-        Operation::Read(&mut read_buf),
-        Operation::Write(&write_data),
-    ];
+    let mut ops = [Operation::Read(&mut read_buf), Operation::Write(&write_data)];
 
     match i2c.blocking_transaction(addr, &mut ops) {
         Ok(_) => {
-            info!("✓ Read-then-write succeeded");
+            info!("✓ Read-then-write succeeded with RESTART");
             info!("  Read: {:02x}", read_buf);
             info!("  Written: {:02x}", write_data);
         }
-        Err(e) => warn!("✗ Read-then-write failed: {:?}", e),
+        Err(e) => {
+            error!("✗ Read-then-write failed: {:?}", e);
+            defmt::panic!("Test failed: read-then-write");
+        }
     }
-
-    info!("Expected: START, ADDR+R, [3 bytes], NACK, RESTART, ADDR+W, [3 bytes], STOP");
-    info!("Check Analog Discovery: RESTART between read and write");
 }
 
-fn test_mixed_sequence(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
+fn test_mixed_sequence(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Complex: W, W, R, R, W, R
     // Groups: [W,W] RESTART [R,R] RESTART [W] RESTART [R]
     let w1 = [0x01, 0x02];
@@ -184,28 +184,26 @@ fn test_mixed_sequence(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
     match i2c.blocking_transaction(addr, &mut ops) {
         Ok(_) => {
             info!("✓ Mixed sequence succeeded");
-            info!("  r1: {:02x}", r1);
-            info!("  r2: {:02x}", r2);
-            info!("  r3: {:02x}", r3);
+            info!("  Groups: [W4] RESTART [R4] RESTART [W1] RESTART [R1]");
+        }
+        Err(e) => {
+            error!("✗ Mixed sequence failed: {:?}", e);
+            defmt::panic!("Test failed: mixed sequence");
         }
-        Err(e) => warn!("✗ Mixed sequence failed: {:?}", e),
     }
-
-    info!("Expected sequence:");
-    info!("  START, ADDR+W, [4 bytes merged], RESTART,");
-    info!("  ADDR+R, [4 bytes merged], NACK, RESTART,");
-    info!("  ADDR+W, [1 byte], RESTART,");
-    info!("  ADDR+R, [1 byte], NACK, STOP");
 }
 
-fn test_single_operations(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
+fn test_single_operations(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Test single write
     let write_data = [0xFF];
     let mut ops = [Operation::Write(&write_data)];
 
     match i2c.blocking_transaction(addr, &mut ops) {
         Ok(_) => info!("✓ Single write succeeded"),
-        Err(e) => warn!("✗ Single write failed: {:?}", e),
+        Err(e) => {
+            error!("✗ Single write failed: {:?}", e);
+            defmt::panic!("Test failed: single write");
+        }
     }
 
     // Test single read
@@ -214,6 +212,9 @@ fn test_single_operations(i2c: &mut I2c<'static, Blocking, Master>, addr: u8) {
 
     match i2c.blocking_transaction(addr, &mut ops) {
         Ok(_) => info!("✓ Single read succeeded, data: 0x{:02x}", read_buf[0]),
-        Err(e) => warn!("✗ Single read failed: {:?}", e),
+        Err(e) => {
+            error!("✗ Single read failed: {:?}", e);
+            defmt::panic!("Test failed: single read");
+        }
     }
 }
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 096cce947..07b667ade 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -60,6 +60,8 @@ teleprobe_meta::target!(b"nucleo-stm32wl55jc");
 teleprobe_meta::target!(b"nucleo-stm32wba52cg");
 #[cfg(feature = "stm32f091rc")]
 teleprobe_meta::target!(b"nucleo-stm32f091rc");
+#[cfg(feature = "stm32f072rb")]
+teleprobe_meta::target!(b"nucleo-stm32f072rb");
 #[cfg(feature = "stm32h503rb")]
 teleprobe_meta::target!(b"nucleo-stm32h503rb");
 #[cfg(feature = "stm32h7s3l8")]
@@ -103,6 +105,14 @@ define_peris!(
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
     @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
 );
+#[cfg(feature = "stm32f072rb")]
+define_peris!(
+    UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
+    SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
+    I2C = I2C1, I2C_SCL = PB8, I2C_SDA = PB9,
+    @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
+    @irq I2C = {I2C1 => embassy_stm32::i2c::EventInterruptHandler<embassy_stm32::peripherals::I2C1>, embassy_stm32::i2c::ErrorInterruptHandler<embassy_stm32::peripherals::I2C1>;},
+);
 #[cfg(any(feature = "stm32f100rd", feature = "stm32f103c8", feature = "stm32f107vc"))]
 define_peris!(
     UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
@@ -325,6 +335,21 @@ pub fn config() -> Config {
         config.rcc.ahb_pre = AHBPrescaler::DIV1;
         config.rcc.apb1_pre = APBPrescaler::DIV1;
     }
+    #[cfg(feature = "stm32f072rb")]
+    {
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll = Some(Pll {
+            src: PllSource::HSE,
+            prediv: PllPreDiv::DIV1,
+            mul: PllMul::MUL6,
+        });
+        config.rcc.sys = Sysclk::PLL1_P;
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV1;
+    }
     #[cfg(feature = "stm32f103c8")]
     {
         config.rcc.hse = Some(Hse {