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authorGerzain Mata <[email protected]>2025-07-27 09:42:17 -0700
committerGerzain Mata <[email protected]>2025-07-27 09:56:02 -0700
commit982117f5b0650734aece226d93343a30ac3a0b65 (patch)
tree289ecf5122c9e6b4c733f8c30d17eb28d26f60ef
parentb9e643d5c2d7192143e91db83b9e8377f0fbcacc (diff)
Cargo fmt
-rw-r--r--embassy-stm32/src/rcc/wba.rs33
-rw-r--r--examples/stm32wba/src/bin/pwm.rs5
2 files changed, 20 insertions, 18 deletions
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index 5f9d4d30a..56ba7b58b 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -1,20 +1,18 @@
1pub use crate::pac::pwr::vals::Vos as VoltageScale; 1pub use crate::pac::pwr::vals::Vos as VoltageScale;
2use crate::pac::rcc::regs::Cfgr1; 2use crate::pac::rcc::regs::Cfgr1;
3#[cfg(all(peri_usb_otg_hs))]
4pub use crate::pac::rcc::vals::Otghssel;
5use crate::pac::rcc::vals::Pllrge;
3pub use crate::pac::rcc::vals::{ 6pub use crate::pac::rcc::vals::{
4 Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as Sysclk, Pllsrc as PllSource, 7 Hdiv5, Hpre as AHBPrescaler, Hpre5 as AHB5Prescaler, Hsepre as HsePrescaler, Plldiv as PllDiv, Pllm as PllPreDiv,
5 Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul, Hpre5 as AHB5Prescaler, Hdiv5, 8 Plln as PllMul, Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
6}; 9};
7use crate::pac::rcc::vals::Pllrge; 10#[cfg(all(peri_usb_otg_hs))]
11pub use crate::pac::{syscfg::vals::Usbrefcksel, SYSCFG};
8use crate::pac::{FLASH, RCC}; 12use crate::pac::{FLASH, RCC};
9use crate::rcc::LSI_FREQ; 13use crate::rcc::LSI_FREQ;
10use crate::time::Hertz; 14use crate::time::Hertz;
11 15
12#[cfg(all(peri_usb_otg_hs))]
13pub use crate::pac::rcc::vals::Otghssel;
14
15#[cfg(all(peri_usb_otg_hs))]
16pub use crate::pac::{syscfg::vals::Usbrefcksel, SYSCFG};
17
18/// HSI speed 16/// HSI speed
19pub const HSI_FREQ: Hertz = Hertz(16_000_000); 17pub const HSI_FREQ: Hertz = Hertz(16_000_000);
20// HSE speed 18// HSE speed
@@ -150,7 +148,7 @@ pub(crate) unsafe fn init(config: Config) {
150 HSE_FREQ 148 HSE_FREQ
151 }); 149 });
152 150
153 let pll_input = PllInput {hse, hsi }; 151 let pll_input = PllInput { hse, hsi };
154 152
155 let pll1 = init_pll(config.pll1, &pll_input, config.voltage_scale); 153 let pll1 = init_pll(config.pll1, &pll_input, config.voltage_scale);
156 154
@@ -231,7 +229,6 @@ pub(crate) unsafe fn init(config: Config) {
231 229
232 let hclk5 = sys_clk / config.ahb5_pre; 230 let hclk5 = sys_clk / config.ahb5_pre;
233 231
234
235 #[cfg(all(stm32wba, peri_usb_otg_hs))] 232 #[cfg(all(stm32wba, peri_usb_otg_hs))]
236 let usb_refck = match config.mux.otghssel { 233 let usb_refck = match config.mux.otghssel {
237 Otghssel::HSE => hse, 234 Otghssel::HSE => hse,
@@ -341,7 +338,7 @@ fn init_pll(config: Option<Pll>, input: &PllInput, voltage_range: VoltageScale)
341 // let vco_freq = ref_freq * pll.mul; 338 // let vco_freq = ref_freq * pll.mul;
342 // Calculate VCO frequency including fractional part: FVCO = Fref_ck × (N + FRAC/2^13) 339 // Calculate VCO frequency including fractional part: FVCO = Fref_ck × (N + FRAC/2^13)
343 let numerator = (ref_freq.0 as u64) * (((pll.mul as u64) + 1 << 13) + pll.frac.unwrap_or(0) as u64); 340 let numerator = (ref_freq.0 as u64) * (((pll.mul as u64) + 1 << 13) + pll.frac.unwrap_or(0) as u64);
344 let vco_hz = (numerator >> 13) as u32; 341 let vco_hz = (numerator >> 13) as u32;
345 let vco_freq = Hertz(vco_hz); 342 let vco_freq = Hertz(vco_hz);
346 assert!(vco_freq >= vco_min && vco_freq <= vco_max); 343 assert!(vco_freq >= vco_min && vco_freq <= vco_max);
347 344
@@ -362,7 +359,9 @@ fn init_pll(config: Option<Pll>, input: &PllInput, voltage_range: VoltageScale)
362 w.set_pllq(pll.divq.unwrap_or(PllDiv::DIV1)); 359 w.set_pllq(pll.divq.unwrap_or(PllDiv::DIV1));
363 w.set_pllr(pll.divr.unwrap_or(PllDiv::DIV1)); 360 w.set_pllr(pll.divr.unwrap_or(PllDiv::DIV1));
364 }); 361 });
365 RCC.pll1fracr().write(|w| {w.set_pllfracn(pll.frac.unwrap_or(0));}); 362 RCC.pll1fracr().write(|w| {
363 w.set_pllfracn(pll.frac.unwrap_or(0));
364 });
366 365
367 let input_range = match ref_freq.0 { 366 let input_range = match ref_freq.0 {
368 ..=8_000_000 => Pllrge::FREQ_4TO8MHZ, 367 ..=8_000_000 => Pllrge::FREQ_4TO8MHZ,
@@ -381,10 +380,12 @@ fn init_pll(config: Option<Pll>, input: &PllInput, voltage_range: VoltageScale)
381 }; 380 };
382 } 381 }
383 382
384 RCC.pll1cfgr().write(|w| {write_fields!(w);}); 383 RCC.pll1cfgr().write(|w| {
384 write_fields!(w);
385 });
385 386
386 // Enable PLL 387 // Enable PLL
387 pll_enable(true); 388 pll_enable(true);
388 389
389 PllOutput{ p, q, r } 390 PllOutput { p, q, r }
390} \ No newline at end of file 391}
diff --git a/examples/stm32wba/src/bin/pwm.rs b/examples/stm32wba/src/bin/pwm.rs
index 611d7c097..2c696834a 100644
--- a/examples/stm32wba/src/bin/pwm.rs
+++ b/examples/stm32wba/src/bin/pwm.rs
@@ -5,8 +5,9 @@ use defmt::*;
5use defmt_rtt as _; // global logger 5use defmt_rtt as _; // global logger
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7use embassy_stm32::gpio::OutputType; 7use embassy_stm32::gpio::OutputType;
8use embassy_stm32::rcc::{AHB5Prescaler, AHBPrescaler, APBPrescaler, Sysclk, VoltageScale}; 8use embassy_stm32::rcc::{
9use embassy_stm32::rcc::{PllDiv, PllMul, PllPreDiv, PllSource}; 9 AHB5Prescaler, AHBPrescaler, APBPrescaler, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk, VoltageScale,
10};
10use embassy_stm32::time::khz; 11use embassy_stm32::time::khz;
11use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm}; 12use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm};
12use embassy_stm32::Config; 13use embassy_stm32::Config;