nrf/uart: switch to new interrupt binding.

9 files changed, 206 insertions, 176 deletions

diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index ab639aeea..75f93f904 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -10,6 +10,7 @@
 
 use core::cmp::min;
 use core::future::poll_fn;
+use core::marker::PhantomData;
 use core::slice;
 use core::sync::atomic::{compiler_fence, AtomicU8, AtomicUsize, Ordering};
 use core::task::Poll;
@@ -23,7 +24,7 @@ pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Pari
 
 use crate::gpio::sealed::Pin;
 use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
-use crate::interrupt::InterruptExt;
+use crate::interrupt::{self, InterruptExt};
 use crate::ppi::{
     self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
 };
@@ -71,6 +72,113 @@ impl State {
     }
 }
 
+/// Interrupt handler.
+pub struct InterruptHandler<U: UarteInstance> {
+    _phantom: PhantomData<U>,
+}
+
+impl<U: UarteInstance> interrupt::Handler<U::Interrupt> for InterruptHandler<U> {
+    unsafe fn on_interrupt() {
+        //trace!("irq: start");
+        let r = U::regs();
+        let s = U::buffered_state();
+
+        let buf_len = s.rx_buf.len();
+        let half_len = buf_len / 2;
+        let mut tx = unsafe { s.tx_buf.reader() };
+        let mut rx = unsafe { s.rx_buf.writer() };
+
+        if r.events_error.read().bits() != 0 {
+            r.events_error.reset();
+            let errs = r.errorsrc.read();
+            r.errorsrc.write(|w| unsafe { w.bits(errs.bits()) });
+
+            if errs.overrun().bit() {
+                panic!("BufferedUarte overrun");
+            }
+        }
+
+        // Received some bytes, wake task.
+        if r.inten.read().rxdrdy().bit_is_set() && r.events_rxdrdy.read().bits() != 0 {
+            r.intenclr.write(|w| w.rxdrdy().clear());
+            r.events_rxdrdy.reset();
+            s.rx_waker.wake();
+        }
+
+        // If not RXing, start.
+        if s.rx_bufs.load(Ordering::Relaxed) == 0 {
+            let (ptr, len) = rx.push_buf();
+            if len >= half_len {
+                //trace!("  irq_rx: starting {:?}", half_len);
+                s.rx_bufs.store(1, Ordering::Relaxed);
+
+                // Set up the DMA read
+                r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
+                r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(half_len as _) });
+
+                // Start UARTE Receive transaction
+                r.tasks_startrx.write(|w| unsafe { w.bits(1) });
+                rx.push_done(half_len);
+                r.intenset.write(|w| w.rxstarted().set());
+            }
+        }
+
+        if r.events_rxstarted.read().bits() != 0 {
+            //trace!("  irq_rx: rxstarted");
+            let (ptr, len) = rx.push_buf();
+            if len >= half_len {
+                //trace!("  irq_rx: starting second {:?}", half_len);
+
+                // Set up the DMA read
+                r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
+                r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(half_len as _) });
+
+                let chn = s.rx_ppi_ch.load(Ordering::Relaxed);
+
+                ppi::regs().chenset.write(|w| unsafe { w.bits(1 << chn) });
+
+                rx.push_done(half_len);
+
+                r.events_rxstarted.reset();
+            } else {
+                //trace!("  irq_rx: rxstarted no buf");
+                r.intenclr.write(|w| w.rxstarted().clear());
+            }
+        }
+
+        // =============================
+
+        // TX end
+        if r.events_endtx.read().bits() != 0 {
+            r.events_endtx.reset();
+
+            let n = s.tx_count.load(Ordering::Relaxed);
+            //trace!("  irq_tx: endtx {:?}", n);
+            tx.pop_done(n);
+            s.tx_waker.wake();
+            s.tx_count.store(0, Ordering::Relaxed);
+        }
+
+        // If not TXing, start.
+        if s.tx_count.load(Ordering::Relaxed) == 0 {
+            let (ptr, len) = tx.pop_buf();
+            if len != 0 {
+                //trace!("  irq_tx: starting {:?}", len);
+                s.tx_count.store(len, Ordering::Relaxed);
+
+                // Set up the DMA write
+                r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
+                r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
+
+                // Start UARTE Transmit transaction
+                r.tasks_starttx.write(|w| unsafe { w.bits(1) });
+            }
+        }
+
+        //trace!("irq: end");
+    }
+}
+
 /// Buffered UARTE driver.
 pub struct BufferedUarte<'d, U: UarteInstance, T: TimerInstance> {
     _peri: PeripheralRef<'d, U>,
@@ -94,7 +202,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
         ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
         ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
         ppi_group: impl Peripheral<P = impl Group> + 'd,
-        irq: impl Peripheral<P = U::Interrupt> + 'd,
+        _irq: impl interrupt::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
         rxd: impl Peripheral<P = impl GpioPin> + 'd,
         txd: impl Peripheral<P = impl GpioPin> + 'd,
         config: Config,
@@ -108,7 +216,6 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
             ppi_ch1.map_into(),
             ppi_ch2.map_into(),
             ppi_group.map_into(),
-            irq,
             rxd.map_into(),
             txd.map_into(),
             None,
@@ -130,7 +237,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
         ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
         ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
         ppi_group: impl Peripheral<P = impl Group> + 'd,
-        irq: impl Peripheral<P = U::Interrupt> + 'd,
+        _irq: impl interrupt::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
         rxd: impl Peripheral<P = impl GpioPin> + 'd,
         txd: impl Peripheral<P = impl GpioPin> + 'd,
         cts: impl Peripheral<P = impl GpioPin> + 'd,
@@ -146,7 +253,6 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
             ppi_ch1.map_into(),
             ppi_ch2.map_into(),
             ppi_group.map_into(),
-            irq,
             rxd.map_into(),
             txd.map_into(),
             Some(cts.map_into()),
@@ -163,7 +269,6 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
         ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>,
         ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>,
         ppi_group: PeripheralRef<'d, AnyGroup>,
-        irq: impl Peripheral<P = U::Interrupt> + 'd,
         rxd: PeripheralRef<'d, AnyPin>,
         txd: PeripheralRef<'d, AnyPin>,
         cts: Option<PeripheralRef<'d, AnyPin>>,
@@ -172,7 +277,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
         rx_buffer: &'d mut [u8],
         tx_buffer: &'d mut [u8],
     ) -> Self {
-        into_ref!(peri, timer, irq);
+        into_ref!(peri, timer);
 
         assert!(rx_buffer.len() % 2 == 0);
 
@@ -257,10 +362,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
         ppi_ch2.disable();
         ppi_group.add_channel(&ppi_ch2);
 
-        irq.disable();
-        irq.set_handler(Self::on_interrupt);
-        irq.pend();
-        irq.enable();
+        unsafe { U::Interrupt::steal() }.pend();
+        unsafe { U::Interrupt::steal() }.enable();
 
         Self {
             _peri: peri,
@@ -275,106 +378,6 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
         unsafe { <U::Interrupt as Interrupt>::steal() }.pend()
     }
 
-    fn on_interrupt(_: *mut ()) {
-        //trace!("irq: start");
-        let r = U::regs();
-        let s = U::buffered_state();
-
-        let buf_len = s.rx_buf.len();
-        let half_len = buf_len / 2;
-        let mut tx = unsafe { s.tx_buf.reader() };
-        let mut rx = unsafe { s.rx_buf.writer() };
-
-        if r.events_error.read().bits() != 0 {
-            r.events_error.reset();
-            let errs = r.errorsrc.read();
-            r.errorsrc.write(|w| unsafe { w.bits(errs.bits()) });
-
-            if errs.overrun().bit() {
-                panic!("BufferedUarte overrun");
-            }
-        }
-
-        // Received some bytes, wake task.
-        if r.inten.read().rxdrdy().bit_is_set() && r.events_rxdrdy.read().bits() != 0 {
-            r.intenclr.write(|w| w.rxdrdy().clear());
-            r.events_rxdrdy.reset();
-            s.rx_waker.wake();
-        }
-
-        // If not RXing, start.
-        if s.rx_bufs.load(Ordering::Relaxed) == 0 {
-            let (ptr, len) = rx.push_buf();
-            if len >= half_len {
-                //trace!("  irq_rx: starting {:?}", half_len);
-                s.rx_bufs.store(1, Ordering::Relaxed);
-
-                // Set up the DMA read
-                r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
-                r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(half_len as _) });
-
-                // Start UARTE Receive transaction
-                r.tasks_startrx.write(|w| unsafe { w.bits(1) });
-                rx.push_done(half_len);
-                r.intenset.write(|w| w.rxstarted().set());
-            }
-        }
-
-        if r.events_rxstarted.read().bits() != 0 {
-            //trace!("  irq_rx: rxstarted");
-            let (ptr, len) = rx.push_buf();
-            if len >= half_len {
-                //trace!("  irq_rx: starting second {:?}", half_len);
-
-                // Set up the DMA read
-                r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
-                r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(half_len as _) });
-
-                let chn = s.rx_ppi_ch.load(Ordering::Relaxed);
-
-                ppi::regs().chenset.write(|w| unsafe { w.bits(1 << chn) });
-
-                rx.push_done(half_len);
-
-                r.events_rxstarted.reset();
-            } else {
-                //trace!("  irq_rx: rxstarted no buf");
-                r.intenclr.write(|w| w.rxstarted().clear());
-            }
-        }
-
-        // =============================
-
-        // TX end
-        if r.events_endtx.read().bits() != 0 {
-            r.events_endtx.reset();
-
-            let n = s.tx_count.load(Ordering::Relaxed);
-            //trace!("  irq_tx: endtx {:?}", n);
-            tx.pop_done(n);
-            s.tx_waker.wake();
-            s.tx_count.store(0, Ordering::Relaxed);
-        }
-
-        // If not TXing, start.
-        if s.tx_count.load(Ordering::Relaxed) == 0 {
-            let (ptr, len) = tx.pop_buf();
-            if len != 0 {
-                //trace!("  irq_tx: starting {:?}", len);
-                s.tx_count.store(len, Ordering::Relaxed);
-
-                // Set up the DMA write
-                r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
-                r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
-
-                // Start UARTE Transmit transaction
-                r.tasks_starttx.write(|w| unsafe { w.bits(1) });
-            }
-        }
-
-        //trace!("irq: end");
-    }
-
     /// Adjust the baud rate to the provided value.
     pub fn set_baudrate(&mut self, baudrate: Baudrate) {
         let r = U::regs();
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 00afbd059..3934d1b55 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -14,6 +14,7 @@
 #![macro_use]
 
 use core::future::poll_fn;
+use core::marker::PhantomData;
 use core::sync::atomic::{compiler_fence, Ordering};
 use core::task::Poll;
 
@@ -26,7 +27,7 @@ pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Pari
 use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
 use crate::gpio::sealed::Pin as _;
 use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
-use crate::interrupt::{Interrupt, InterruptExt};
+use crate::interrupt::{self, Interrupt, InterruptExt};
 use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task};
 use crate::timer::{Frequency, Instance as TimerInstance, Timer};
 use crate::util::slice_in_ram_or;
@@ -62,6 +63,27 @@ pub enum Error {
     BufferNotInRAM,
 }
 
+/// Interrupt handler.
+pub struct InterruptHandler<T: Instance> {
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        let r = T::regs();
+        let s = T::state();
+
+        if r.events_endrx.read().bits() != 0 {
+            s.endrx_waker.wake();
+            r.intenclr.write(|w| w.endrx().clear());
+        }
+        if r.events_endtx.read().bits() != 0 {
+            s.endtx_waker.wake();
+            r.intenclr.write(|w| w.endtx().clear());
+        }
+    }
+}
+
 /// UARTE driver.
 pub struct Uarte<'d, T: Instance> {
     tx: UarteTx<'d, T>,
@@ -86,19 +108,19 @@ impl<'d, T: Instance> Uarte<'d, T> {
     /// Create a new UARTE without hardware flow control
     pub fn new(
         uarte: impl Peripheral<P = T> + 'd,
-        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        _irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         rxd: impl Peripheral<P = impl GpioPin> + 'd,
         txd: impl Peripheral<P = impl GpioPin> + 'd,
         config: Config,
     ) -> Self {
         into_ref!(rxd, txd);
-        Self::new_inner(uarte, irq, rxd.map_into(), txd.map_into(), None, None, config)
+        Self::new_inner(uarte, rxd.map_into(), txd.map_into(), None, None, config)
     }
 
     /// Create a new UARTE with hardware flow control (RTS/CTS)
     pub fn new_with_rtscts(
         uarte: impl Peripheral<P = T> + 'd,
-        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        _irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         rxd: impl Peripheral<P = impl GpioPin> + 'd,
         txd: impl Peripheral<P = impl GpioPin> + 'd,
         cts: impl Peripheral<P = impl GpioPin> + 'd,
@@ -108,7 +130,6 @@ impl<'d, T: Instance> Uarte<'d, T> {
         into_ref!(rxd, txd, cts, rts);
         Self::new_inner(
             uarte,
-            irq,
             rxd.map_into(),
             txd.map_into(),
             Some(cts.map_into()),
@@ -119,14 +140,13 @@ impl<'d, T: Instance> Uarte<'d, T> {
 
     fn new_inner(
         uarte: impl Peripheral<P = T> + 'd,
-        irq: impl Peripheral<P = T::Interrupt> + 'd,
         rxd: PeripheralRef<'d, AnyPin>,
         txd: PeripheralRef<'d, AnyPin>,
         cts: Option<PeripheralRef<'d, AnyPin>>,
         rts: Option<PeripheralRef<'d, AnyPin>>,
         config: Config,
     ) -> Self {
-        into_ref!(uarte, irq);
+        into_ref!(uarte);
 
         let r = T::regs();
 
@@ -148,9 +168,8 @@ impl<'d, T: Instance> Uarte<'d, T> {
         }
         r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
 
-        irq.set_handler(Self::on_interrupt);
-        irq.unpend();
-        irq.enable();
+        unsafe { T::Interrupt::steal() }.unpend();
+        unsafe { T::Interrupt::steal() }.enable();
 
         let hardware_flow_control = match (rts.is_some(), cts.is_some()) {
             (false, false) => false,
@@ -238,20 +257,6 @@ impl<'d, T: Instance> Uarte<'d, T> {
         Event::from_reg(&r.events_endtx)
     }
 
-    fn on_interrupt(_: *mut ()) {
-        let r = T::regs();
-        let s = T::state();
-
-        if r.events_endrx.read().bits() != 0 {
-            s.endrx_waker.wake();
-            r.intenclr.write(|w| w.endrx().clear());
-        }
-        if r.events_endtx.read().bits() != 0 {
-            s.endtx_waker.wake();
-            r.intenclr.write(|w| w.endtx().clear());
-        }
-    }
-
     /// Read bytes until the buffer is filled.
     pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
         self.rx.read(buffer).await
@@ -308,34 +313,33 @@ impl<'d, T: Instance> UarteTx<'d, T> {
     /// Create a new tx-only UARTE without hardware flow control
     pub fn new(
         uarte: impl Peripheral<P = T> + 'd,
-        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        _irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         txd: impl Peripheral<P = impl GpioPin> + 'd,
         config: Config,
     ) -> Self {
         into_ref!(txd);
-        Self::new_inner(uarte, irq, txd.map_into(), None, config)
+        Self::new_inner(uarte, txd.map_into(), None, config)
     }
 
     /// Create a new tx-only UARTE with hardware flow control (RTS/CTS)
     pub fn new_with_rtscts(
         uarte: impl Peripheral<P = T> + 'd,
-        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        _irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         txd: impl Peripheral<P = impl GpioPin> + 'd,
         cts: impl Peripheral<P = impl GpioPin> + 'd,
         config: Config,
     ) -> Self {
         into_ref!(txd, cts);
-        Self::new_inner(uarte, irq, txd.map_into(), Some(cts.map_into()), config)
+        Self::new_inner(uarte, txd.map_into(), Some(cts.map_into()), config)
     }
 
     fn new_inner(
         uarte: impl Peripheral<P = T> + 'd,
-        irq: impl Peripheral<P = T::Interrupt> + 'd,
         txd: PeripheralRef<'d, AnyPin>,
         cts: Option<PeripheralRef<'d, AnyPin>>,
         config: Config,
     ) -> Self {
-        into_ref!(uarte, irq);
+        into_ref!(uarte);
 
         let r = T::regs();
 
@@ -354,9 +358,8 @@ impl<'d, T: Instance> UarteTx<'d, T> {
         let hardware_flow_control = cts.is_some();
         configure(r, config, hardware_flow_control);
 
-        irq.set_handler(Uarte::<T>::on_interrupt);
-        irq.unpend();
-        irq.enable();
+        unsafe { T::Interrupt::steal() }.unpend();
+        unsafe { T::Interrupt::steal() }.enable();
 
         let s = T::state();
         s.tx_rx_refcount.store(1, Ordering::Relaxed);
@@ -506,34 +509,33 @@ impl<'d, T: Instance> UarteRx<'d, T> {
     /// Create a new rx-only UARTE without hardware flow control
     pub fn new(
         uarte: impl Peripheral<P = T> + 'd,
-        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        _irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         rxd: impl Peripheral<P = impl GpioPin> + 'd,
         config: Config,
     ) -> Self {
         into_ref!(rxd);
-        Self::new_inner(uarte, irq, rxd.map_into(), None, config)
+        Self::new_inner(uarte, rxd.map_into(), None, config)
     }
 
     /// Create a new rx-only UARTE with hardware flow control (RTS/CTS)
     pub fn new_with_rtscts(
         uarte: impl Peripheral<P = T> + 'd,
-        irq: impl Peripheral<P = T::Interrupt> + 'd,
+        _irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         rxd: impl Peripheral<P = impl GpioPin> + 'd,
         rts: impl Peripheral<P = impl GpioPin> + 'd,
         config: Config,
     ) -> Self {
         into_ref!(rxd, rts);
-        Self::new_inner(uarte, irq, rxd.map_into(), Some(rts.map_into()), config)
+        Self::new_inner(uarte, rxd.map_into(), Some(rts.map_into()), config)
     }
 
     fn new_inner(
         uarte: impl Peripheral<P = T> + 'd,
-        irq: impl Peripheral<P = T::Interrupt> + 'd,
         rxd: PeripheralRef<'d, AnyPin>,
         rts: Option<PeripheralRef<'d, AnyPin>>,
         config: Config,
     ) -> Self {
-        into_ref!(uarte, irq);
+        into_ref!(uarte);
 
         let r = T::regs();
 
@@ -549,9 +551,8 @@ impl<'d, T: Instance> UarteRx<'d, T> {
         r.psel.txd.write(|w| w.connect().disconnected());
         r.psel.cts.write(|w| w.connect().disconnected());
 
-        irq.set_handler(Uarte::<T>::on_interrupt);
-        irq.unpend();
-        irq.enable();
+        unsafe { T::Interrupt::steal() }.unpend();
+        unsafe { T::Interrupt::steal() }.enable();
 
         let hardware_flow_control = rts.is_some();
         configure(r, config, hardware_flow_control);
diff --git a/examples/nrf52840/src/bin/buffered_uart.rs b/examples/nrf52840/src/bin/buffered_uart.rs
index 5b934b7d6..238695371 100644
--- a/examples/nrf52840/src/bin/buffered_uart.rs
+++ b/examples/nrf52840/src/bin/buffered_uart.rs
@@ -4,11 +4,15 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_nrf::buffered_uarte::BufferedUarte;
-use embassy_nrf::{interrupt, uarte};
+use embassy_nrf::buffered_uarte::{self, BufferedUarte};
+use embassy_nrf::{bind_interrupts, peripherals, uarte};
 use embedded_io::asynch::Write;
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(struct Irqs {
+    UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
@@ -19,14 +23,13 @@ async fn main(_spawner: Spawner) {
     let mut tx_buffer = [0u8; 4096];
     let mut rx_buffer = [0u8; 4096];
 
-    let irq = interrupt::take!(UARTE0_UART0);
     let mut u = BufferedUarte::new(
         p.UARTE0,
         p.TIMER0,
         p.PPI_CH0,
         p.PPI_CH1,
         p.PPI_GROUP0,
-        irq,
+        Irqs,
         p.P0_08,
         p.P0_06,
         config,
diff --git a/examples/nrf52840/src/bin/uart.rs b/examples/nrf52840/src/bin/uart.rs
index 600f7a6ef..50d5cab8c 100644
--- a/examples/nrf52840/src/bin/uart.rs
+++ b/examples/nrf52840/src/bin/uart.rs
@@ -4,9 +4,13 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_nrf::{interrupt, uarte};
+use embassy_nrf::{bind_interrupts, peripherals, uarte};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(struct Irqs {
+    UARTE0_UART0 => uarte::InterruptHandler<peripherals::UARTE0>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
@@ -14,8 +18,7 @@ async fn main(_spawner: Spawner) {
     config.parity = uarte::Parity::EXCLUDED;
     config.baudrate = uarte::Baudrate::BAUD115200;
 
-    let irq = interrupt::take!(UARTE0_UART0);
-    let mut uart = uarte::Uarte::new(p.UARTE0, irq, p.P0_08, p.P0_06, config);
+    let mut uart = uarte::Uarte::new(p.UARTE0, Irqs, p.P0_08, p.P0_06, config);
 
     info!("uarte initialized!");
 
diff --git a/examples/nrf52840/src/bin/uart_idle.rs b/examples/nrf52840/src/bin/uart_idle.rs
index 6af4f7097..e1f42fa6c 100644
--- a/examples/nrf52840/src/bin/uart_idle.rs
+++ b/examples/nrf52840/src/bin/uart_idle.rs
@@ -4,9 +4,14 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_nrf::{interrupt, uarte};
+use embassy_nrf::peripherals::UARTE0;
+use embassy_nrf::{bind_interrupts, uarte};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(struct Irqs {
+    UARTE0_UART0 => uarte::InterruptHandler<UARTE0>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
@@ -14,8 +19,7 @@ async fn main(_spawner: Spawner) {
     config.parity = uarte::Parity::EXCLUDED;
     config.baudrate = uarte::Baudrate::BAUD115200;
 
-    let irq = interrupt::take!(UARTE0_UART0);
-    let uart = uarte::Uarte::new(p.UARTE0, irq, p.P0_08, p.P0_06, config);
+    let uart = uarte::Uarte::new(p.UARTE0, Irqs, p.P0_08, p.P0_06, config);
     let (mut tx, mut rx) = uart.split_with_idle(p.TIMER0, p.PPI_CH0, p.PPI_CH1);
 
     info!("uarte initialized!");
diff --git a/examples/nrf52840/src/bin/uart_split.rs b/examples/nrf52840/src/bin/uart_split.rs
index 1adaf53fd..9979a1d53 100644
--- a/examples/nrf52840/src/bin/uart_split.rs
+++ b/examples/nrf52840/src/bin/uart_split.rs
@@ -6,13 +6,17 @@ use defmt::*;
 use embassy_executor::Spawner;
 use embassy_nrf::peripherals::UARTE0;
 use embassy_nrf::uarte::UarteRx;
-use embassy_nrf::{interrupt, uarte};
+use embassy_nrf::{bind_interrupts, uarte};
 use embassy_sync::blocking_mutex::raw::ThreadModeRawMutex;
 use embassy_sync::channel::Channel;
 use {defmt_rtt as _, panic_probe as _};
 
 static CHANNEL: Channel<ThreadModeRawMutex, [u8; 8], 1> = Channel::new();
 
+bind_interrupts!(struct Irqs {
+    UARTE0_UART0 => uarte::InterruptHandler<UARTE0>;
+});
+
 #[embassy_executor::main]
 async fn main(spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
@@ -20,8 +24,7 @@ async fn main(spawner: Spawner) {
     config.parity = uarte::Parity::EXCLUDED;
     config.baudrate = uarte::Baudrate::BAUD115200;
 
-    let irq = interrupt::take!(UARTE0_UART0);
-    let uart = uarte::Uarte::new(p.UARTE0, irq, p.P0_08, p.P0_06, config);
+    let uart = uarte::Uarte::new(p.UARTE0, Irqs, p.P0_08, p.P0_06, config);
     let (mut tx, rx) = uart.split();
 
     info!("uarte initialized!");
diff --git a/examples/nrf5340/src/bin/uart.rs b/examples/nrf5340/src/bin/uart.rs
index 5f448c2ba..d68539702 100644
--- a/examples/nrf5340/src/bin/uart.rs
+++ b/examples/nrf5340/src/bin/uart.rs
@@ -4,9 +4,14 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_nrf::{interrupt, uarte};
+use embassy_nrf::peripherals::SERIAL0;
+use embassy_nrf::{bind_interrupts, uarte};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(struct Irqs {
+    SERIAL0 => uarte::InterruptHandler<SERIAL0>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
@@ -14,8 +19,7 @@ async fn main(_spawner: Spawner) {
     config.parity = uarte::Parity::EXCLUDED;
     config.baudrate = uarte::Baudrate::BAUD115200;
 
-    let irq = interrupt::take!(SERIAL0);
-    let mut uart = uarte::Uarte::new(p.SERIAL0, irq, p.P1_00, p.P1_01, config);
+    let mut uart = uarte::Uarte::new(p.SERIAL0, Irqs, p.P1_00, p.P1_01, config);
 
     info!("uarte initialized!");
 
diff --git a/tests/nrf/src/bin/buffered_uart.rs b/tests/nrf/src/bin/buffered_uart.rs
index 0550b0bb7..e73d4f0b0 100644
--- a/tests/nrf/src/bin/buffered_uart.rs
+++ b/tests/nrf/src/bin/buffered_uart.rs
@@ -5,10 +5,14 @@
 use defmt::{assert_eq, *};
 use embassy_executor::Spawner;
 use embassy_futures::join::join;
-use embassy_nrf::buffered_uarte::BufferedUarte;
-use embassy_nrf::{interrupt, uarte};
+use embassy_nrf::buffered_uarte::{self, BufferedUarte};
+use embassy_nrf::{bind_interrupts, peripherals, uarte};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(struct Irqs {
+    UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let p = embassy_nrf::init(Default::default());
@@ -25,7 +29,7 @@ async fn main(_spawner: Spawner) {
         p.PPI_CH0,
         p.PPI_CH1,
         p.PPI_GROUP0,
-        interrupt::take!(UARTE0_UART0),
+        Irqs,
         p.P1_03,
         p.P1_02,
         config.clone(),
diff --git a/tests/nrf/src/bin/buffered_uart_spam.rs b/tests/nrf/src/bin/buffered_uart_spam.rs
index 57aaeca45..74eda6d01 100644
--- a/tests/nrf/src/bin/buffered_uart_spam.rs
+++ b/tests/nrf/src/bin/buffered_uart_spam.rs
@@ -7,14 +7,19 @@ use core::ptr::NonNull;
 
 use defmt::{assert_eq, *};
 use embassy_executor::Spawner;
-use embassy_nrf::buffered_uarte::BufferedUarte;
+use embassy_nrf::buffered_uarte::{self, BufferedUarte};
 use embassy_nrf::gpio::{Level, Output, OutputDrive};
 use embassy_nrf::ppi::{Event, Ppi, Task};
 use embassy_nrf::uarte::Uarte;
-use embassy_nrf::{interrupt, pac, uarte};
+use embassy_nrf::{bind_interrupts, pac, peripherals, uarte};
 use embassy_time::{Duration, Timer};
 use {defmt_rtt as _, panic_probe as _};
 
+bind_interrupts!(struct Irqs {
+    UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;
+    UARTE1 => uarte::InterruptHandler<peripherals::UARTE1>;
+});
+
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut p = embassy_nrf::init(Default::default());
@@ -33,7 +38,7 @@ async fn main(_spawner: Spawner) {
         p.PPI_CH0,
         p.PPI_CH1,
         p.PPI_GROUP0,
-        interrupt::take!(UARTE0_UART0),
+        Irqs,
         p.P1_03,
         p.P1_04,
         config.clone(),
@@ -49,7 +54,7 @@ async fn main(_spawner: Spawner) {
     // Tx spam in a loop.
     const NSPAM: usize = 17;
     static mut TX_BUF: [u8; NSPAM] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
-    let _spam = Uarte::new(p.UARTE1, interrupt::take!(UARTE1), p.P1_01, p.P1_02, config.clone());
+    let _spam = Uarte::new(p.UARTE1, Irqs, p.P1_01, p.P1_02, config.clone());
     let spam_peri: pac::UARTE1 = unsafe { mem::transmute(()) };
     let event = unsafe { Event::new_unchecked(NonNull::new_unchecked(&spam_peri.events_endtx as *const _ as _)) };
     let task = unsafe { Task::new_unchecked(NonNull::new_unchecked(&spam_peri.tasks_starttx as *const _ as _)) };