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authorDario Nieuwenhuis <[email protected]>2021-06-25 06:23:20 +0200
committerDario Nieuwenhuis <[email protected]>2021-06-25 06:24:14 +0200
commit9cf1d5b29cae76b39b709a65afbef00906bfdd8e (patch)
tree0a3efdedfa8c60b807149c40c8f6cbada52a2ead
parentc7c897bb72bd88eb404871c641de69a542d2b56d (diff)
rp/clocks: fix wrong PLL setup
-rw-r--r--embassy-rp/src/clocks.rs13
1 files changed, 7 insertions, 6 deletions
diff --git a/embassy-rp/src/clocks.rs b/embassy-rp/src/clocks.rs
index 71e738c4c..c3ca4cf69 100644
--- a/embassy-rp/src/clocks.rs
+++ b/embassy-rp/src/clocks.rs
@@ -155,15 +155,16 @@ unsafe fn configure_pll(
155 }); 155 });
156 p.fbdiv_int().write(|w| w.set_fbdiv_int(0)); 156 p.fbdiv_int().write(|w| w.set_fbdiv_int(0));
157 157
158 let ref_mhz = XOSC_MHZ / refdiv; 158 let ref_freq = XOSC_MHZ * 1_000_000 / refdiv;
159 p.cs().write(|w| w.set_refdiv(ref_mhz as _));
160 159
161 let fbdiv = vco_freq / (ref_mhz * 1_000_000); 160 let fbdiv = vco_freq / ref_freq;
162 assert!(fbdiv >= 16 && fbdiv <= 520); 161 assert!(fbdiv >= 16 && fbdiv <= 320);
163 assert!((post_div1 >= 1 && post_div1 <= 7) && (post_div2 >= 1 && post_div2 <= 7)); 162 assert!(post_div1 >= 1 && post_div1 <= 7);
163 assert!(post_div2 >= 1 && post_div2 <= 7);
164 assert!(post_div2 <= post_div1); 164 assert!(post_div2 <= post_div1);
165 assert!(ref_mhz <= (vco_freq / 16)); 165 assert!(ref_freq <= (vco_freq / 16));
166 166
167 p.cs().write(|w| w.set_refdiv(refdiv as _));
167 p.fbdiv_int().write(|w| w.set_fbdiv_int(fbdiv as _)); 168 p.fbdiv_int().write(|w| w.set_fbdiv_int(fbdiv as _));
168 169
169 p.pwr().modify(|w| { 170 p.pwr().modify(|w| {