diff options
| author | Richard Dodd <[email protected]> | 2021-05-05 18:25:14 +0100 |
|---|---|---|
| committer | Richard Dodd <[email protected]> | 2021-05-05 18:25:14 +0100 |
| commit | 9de12a0a7a3dc3bb95a3bdc09817ead8e8130269 (patch) | |
| tree | 001367f73fbaa1703e2e177147da513f78a92795 | |
| parent | 1ad18aa09a8f6aefafab0b9e29c2c31dc614a320 (diff) | |
Address issues in PR.
| -rw-r--r-- | embassy-nrf/src/spim.rs | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs index d233a8af8..3b5f7a070 100644 --- a/embassy-nrf/src/spim.rs +++ b/embassy-nrf/src/spim.rs | |||
| @@ -232,7 +232,6 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spim<'d, T> | |||
| 232 | compiler_fence(Ordering::SeqCst); | 232 | compiler_fence(Ordering::SeqCst); |
| 233 | 233 | ||
| 234 | let r = T::regs(); | 234 | let r = T::regs(); |
| 235 | let s = T::state(); | ||
| 236 | 235 | ||
| 237 | // Set up the DMA write. | 236 | // Set up the DMA write. |
| 238 | r.txd | 237 | r.txd |
| @@ -250,23 +249,20 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spim<'d, T> | |||
| 250 | .maxcnt | 249 | .maxcnt |
| 251 | .write(|w| unsafe { w.maxcnt().bits(words.len() as _) }); | 250 | .write(|w| unsafe { w.maxcnt().bits(words.len() as _) }); |
| 252 | 251 | ||
| 253 | // Reset and enable the event | 252 | // Disable the end event since we are busy-polling. |
| 254 | r.events_end.reset(); | 253 | r.events_end.reset(); |
| 255 | r.intenset.write(|w| w.end().set()); | ||
| 256 | 254 | ||
| 257 | // Start SPI transaction. | 255 | // Start SPI transaction. |
| 258 | r.tasks_start.write(|w| unsafe { w.bits(1) }); | 256 | r.tasks_start.write(|w| unsafe { w.bits(1) }); |
| 259 | 257 | ||
| 258 | // Wait for 'end' event. | ||
| 259 | while r.events_end.read().bits() == 0 {} | ||
| 260 | |||
| 260 | // Conservative compiler fence to prevent optimizations that do not | 261 | // Conservative compiler fence to prevent optimizations that do not |
| 261 | // take in to account actions by DMA. The fence has been placed here, | 262 | // take in to account actions by DMA. The fence has been placed here, |
| 262 | // after all possible DMA actions have completed. | 263 | // after all possible DMA actions have completed. |
| 263 | compiler_fence(Ordering::SeqCst); | 264 | compiler_fence(Ordering::SeqCst); |
| 264 | 265 | ||
| 265 | // Wait for 'end' event. | ||
| 266 | while r.events_end.read().bits() == 0 { | ||
| 267 | continue; | ||
| 268 | } | ||
| 269 | |||
| 270 | Ok(words) | 266 | Ok(words) |
| 271 | } | 267 | } |
| 272 | } | 268 | } |
