stm32/i2c: Fix v2 async transaction implementation

4 files changed, 363 insertions, 139 deletions

diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 3c43887c0..c9656d2c2 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -225,7 +225,14 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
     fn reload(info: &'static Info, length: usize, will_reload: bool, stop: Stop, timeout: Timeout) -> Result<(), Error> {
         assert!(length < 256 && length > 0);
 
-        while !info.regs.isr().read().tcr() {
+        // Wait for either TCR (Transfer Complete Reload) or TC (Transfer Complete)
+        // TCR occurs when RELOAD=1, TC occurs when RELOAD=0
+        // Both indicate the peripheral is ready for the next transfer
+        loop {
+            let isr = info.regs.isr().read();
+            if isr.tcr() || isr.tc() {
+                break;
+            }
             timeout.check()?;
         }
 
@@ -885,12 +892,12 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                         address,
                         total_len.min(255),
                         Stop::Software,
-                        (total_len > 255) || !last_slice,
+                        total_len > 255,
                         restart,
                         timeout,
                     )?;
                 } else {
-                    Self::reload(self.info, total_len.min(255), (total_len > 255) || !last_slice, Stop::Software, timeout)?;
+                    Self::reload(self.info, total_len.min(255), total_len > 255, Stop::Software, timeout)?;
                     self.info.regs.cr1().modify(|w| w.set_tcie(true));
                 }
             } else if !(isr.tcr() || isr.tc()) {
@@ -899,9 +906,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
             } else if remaining_len == 0 {
                 return Poll::Ready(Ok(()));
             } else {
-                let last_piece = (remaining_len <= 255) && last_slice;
-
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, Stop::Software, timeout) {
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), remaining_len > 255, Stop::Software, timeout) {
                     return Poll::Ready(Err(e));
                 }
                 self.info.regs.cr1().modify(|w| w.set_tcie(true));
@@ -913,10 +918,9 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
         .await?;
 
         dma_transfer.await;
-        if last_slice {
-            // This should be done already
-            self.wait_tc(timeout)?;
-        }
+
+        // Always wait for TC after DMA completes - needed for consecutive buffers
+        self.wait_tc(timeout)?;
 
         if last_slice & send_stop {
             self.master_stop();
@@ -1173,56 +1177,9 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
         is_last_group: bool,
         timeout: Timeout,
     ) -> Result<(), Error> {
-        // Calculate total bytes across all operations in this group
-        let total_bytes = Self::total_operation_bytes(operations);
-
-        if total_bytes == 0 {
-            // Handle empty write group using blocking call
-            if is_first_group {
-                Self::master_write(self.info, address, 0, Stop::Software, false, !is_first_group, timeout)?;
-            }
-            if is_last_group {
-                self.master_stop();
-            }
-            return Ok(());
-        }
-
-        let send_stop = is_last_group;
-
-        // Use DMA for each operation in the group
-        let mut first_in_group = true;
-        let mut remaining_operations = operations.len();
-
-        for operation in operations {
-            if let Operation::Write(buffer) = operation {
-                remaining_operations -= 1;
-                let is_last_in_group = remaining_operations == 0;
-
-                if buffer.is_empty() {
-                    // Skip empty buffers
-                    continue;
-                }
-
-                let fut = self.write_dma_internal(
-                    address,
-                    buffer,
-                    first_in_group && is_first_group,  // first_slice
-                    is_last_in_group && is_last_group, // last_slice
-                    send_stop && is_last_in_group,     // send_stop
-                    !is_first_group && first_in_group, // restart
-                    timeout,
-                );
-                timeout.with(fut).await?;
-                first_in_group = false;
-            }
-        }
-
-        // If not last group, wait for TC to enable RESTART
-        if !is_last_group {
-            self.wait_tc(timeout)?;
-        }
-
-        Ok(())
+        // For now, use blocking implementation for write groups
+        // This avoids complexity of handling multiple non-contiguous buffers with DMA
+        self.execute_write_group(address, operations, is_first_group, is_last_group, timeout)
     }
 
     async fn execute_read_group_async(
@@ -1255,10 +1212,10 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
             return Ok(());
         }
 
-        // For read operations, we need to handle them differently since read_dma_internal
-        // expects a single buffer. We'll iterate through operations and use DMA for each.
-        let mut total_remaining = total_bytes;
+        // Use DMA for read operations - need to handle multiple buffers
         let restart = !is_first_group;
+        let mut total_remaining = total_bytes;
+        let mut is_first_in_group = true;
 
         for operation in operations {
             if let Operation::Read(buffer) = operation {
@@ -1267,57 +1224,46 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                     continue;
                 }
 
-                let is_first_read = total_remaining == total_bytes;
                 let buf_len = buffer.len();
                 total_remaining -= buf_len;
-                let is_last_read = total_remaining == 0;
-
-                if is_first_read {
-                    // First read in the group
-                    let completed_chunks = buf_len / 255;
-                    let total_chunks = if completed_chunks * 255 == buf_len {
-                        completed_chunks
+                let is_last_in_group = total_remaining == 0;
+
+                // Perform DMA read
+                if is_first_in_group {
+                    // First buffer: use read_dma_internal which handles restart properly
+                    // Only use Automatic stop if this is the last buffer in the last group
+                    let stop_mode = if is_last_group && is_last_in_group {
+                        Stop::Automatic
                     } else {
-                        completed_chunks + 1
+                        Stop::Software
                     };
-                    let last_chunk_idx = total_chunks.saturating_sub(1);
 
-                    // Use master_read to initiate, then DMA for data
-                    Self::master_read(
-                        self.info,
+                    // We need a custom DMA read that respects our stop mode
+                    self.read_dma_group_internal(
                         address,
-                        buf_len.min(255),
-                        if is_last_group && is_last_read {
-                            Stop::Automatic
-                        } else {
-                            Stop::Software
-                        },
-                        last_chunk_idx != 0 || !is_last_read, // reload
+                        buffer,
                         restart,
+                        stop_mode,
                         timeout,
-                    )?;
-                }
-
-                // Use the existing read_dma_internal, but we need to handle the reload logic ourselves
-                // For simplicity with consecutive reads, fall back to blocking for now
-                // This maintains correctness while keeping complexity manageable
-                for (chunk_idx, chunk) in buffer.chunks_mut(255).enumerate() {
-                    let chunk_len = chunk.len();
-                    let is_very_last = total_remaining == 0 && chunk_len == chunk.len();
-
-                    if !is_first_read || chunk_idx != 0 {
-                        let stop = if is_last_group && is_very_last {
-                            Stop::Automatic
-                        } else {
-                            Stop::Software
-                        };
-                        Self::reload(self.info, chunk_len, !(is_last_group && is_very_last), stop, timeout)?;
-                    }
+                    )
+                    .await?;
+                    is_first_in_group = false;
+                } else {
+                    // Subsequent buffers: need to reload and continue
+                    let stop_mode = if is_last_group && is_last_in_group {
+                        Stop::Automatic
+                    } else {
+                        Stop::Software
+                    };
 
-                    for byte in chunk {
-                        self.wait_rxne(timeout)?;
-                        *byte = self.info.regs.rxdr().read().rxdata();
-                    }
+                    self.read_dma_group_internal(
+                        address,
+                        buffer,
+                        false, // no restart for subsequent buffers in same group
+                        stop_mode,
+                        timeout,
+                    )
+                    .await?;
                 }
             }
         }
@@ -1326,9 +1272,108 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
         if is_last_group {
             self.wait_stop(timeout)?;
         }
-        // For non-last read groups, don't wait for TC - the peripheral may hold SCL low
-        // in Software AUTOEND mode until the next START is issued. Just proceed directly
-        // to the next group which will issue RESTART and release the clock.
+
+        Ok(())
+    }
+
+    /// Internal DMA read helper for transaction groups
+    async fn read_dma_group_internal(
+        &mut self,
+        address: Address,
+        buffer: &mut [u8],
+        restart: bool,
+        stop_mode: Stop,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        let total_len = buffer.len();
+
+        let dma_transfer = unsafe {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(true);
+                w.set_tcie(true);
+                w.set_nackie(true);
+                w.set_errie(true);
+            });
+            let src = regs.rxdr().as_ptr() as *mut u8;
+
+            self.rx_dma.as_mut().unwrap().read(src, buffer, Default::default())
+        };
+
+        let mut remaining_len = total_len;
+
+        let on_drop = OnDrop::new(|| {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(false);
+                w.set_tcie(false);
+                w.set_nackie(false);
+                w.set_errie(false);
+            });
+            regs.icr().write(|w| {
+                w.set_nackcf(true);
+                w.set_berrcf(true);
+                w.set_arlocf(true);
+                w.set_ovrcf(true);
+            });
+        });
+
+        poll_fn(|cx| {
+            self.state.waker.register(cx.waker());
+
+            let isr = self.info.regs.isr().read();
+
+            if isr.nackf() {
+                return Poll::Ready(Err(Error::Nack));
+            }
+            if isr.arlo() {
+                return Poll::Ready(Err(Error::Arbitration));
+            }
+            if isr.berr() {
+                return Poll::Ready(Err(Error::Bus));
+            }
+            if isr.ovr() {
+                return Poll::Ready(Err(Error::Overrun));
+            }
+
+            if remaining_len == total_len {
+                Self::master_read(
+                    self.info,
+                    address,
+                    total_len.min(255),
+                    stop_mode,
+                    total_len > 255, // reload
+                    restart,
+                    timeout,
+                )?;
+                if total_len <= 255 {
+                    return Poll::Ready(Ok(()));
+                }
+            } else if isr.tcr() {
+                // Transfer Complete Reload - need to set up next chunk
+                let last_piece = remaining_len <= 255;
+
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, stop_mode, timeout) {
+                    return Poll::Ready(Err(e));
+                }
+                // Return here if we are on last chunk,
+                // end of transfer will be awaited with the DMA below
+                if last_piece {
+                    return Poll::Ready(Ok(()));
+                }
+                self.info.regs.cr1().modify(|w| w.set_tcie(true));
+            } else {
+                // poll_fn was woken without TCR interrupt
+                return Poll::Pending;
+            }
+
+            remaining_len = remaining_len.saturating_sub(255);
+            Poll::Pending
+        })
+        .await?;
+
+        dma_transfer.await;
+        drop(on_drop);
 
         Ok(())
     }
diff --git a/tests/stm32/build.rs b/tests/stm32/build.rs
index 556d77a20..34030c206 100644
--- a/tests/stm32/build.rs
+++ b/tests/stm32/build.rs
@@ -15,6 +15,7 @@ fn main() -> Result<(), Box<dyn Error>> {
         feature = "stm32c071rb", // 24 kb
         feature = "stm32l073rz", // 20 kb
         feature = "stm32h503rb", // 32 kb
+        feature = "stm32f072rb", // 16 kb - I2C v2 test with async too large for RAM
         // no VTOR, so interrupts can't work when running from RAM
         feature = "stm32f091rc",
     )) {
diff --git a/tests/stm32/src/bin/i2c_v2.rs b/tests/stm32/src/bin/i2c_v2.rs
index 9a23e28e1..087b8bbd9 100644
--- a/tests/stm32/src/bin/i2c_v2.rs
+++ b/tests/stm32/src/bin/i2c_v2.rs
@@ -7,7 +7,7 @@
 // - Connect to I2C slave device (e.g., Digilent Analog Discovery I2C slave, or EEPROM)
 // - Default slave address: 0x50
 // - Pull-up resistors: 4.7kΩ on both SCL and SDA
-// - CN5 Pin 5 (PB8/SCL) and CN5 Pin 9 (PB9/SDA)
+// - CN5 Pin 10 (PB8/SCL) and CN5 Pin 9 (PB9/SDA)
 //
 // Analog Discovery Setup:
 // - Configure as I2C Slave at address 0x50
@@ -21,9 +21,9 @@ mod common;
 use common::*;
 use embassy_executor::Spawner;
 use embassy_stm32::i2c::{Config, I2c, Master};
-use embassy_stm32::mode::Blocking;
+use embassy_stm32::mode::{Async, Blocking};
 use embassy_stm32::time::Hertz;
-use embassy_time::block_for;
+use embassy_time::Timer;
 use embedded_hal_1::i2c::Operation;
 
 #[embassy_executor::main]
@@ -38,42 +38,80 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     config.frequency = Hertz(100_000);
 
-    let mut i2c = I2c::new_blocking(
-        i2c_peri.reborrow(),
-        scl.reborrow(),
-        sda.reborrow(),
-        config,
-    );
-
     // I2C slave address for Analog Discovery or test EEPROM
     let slave_addr = 0x50u8;
 
     // Wait for slave device to be ready
-    block_for(embassy_time::Duration::from_millis(100));
+    Timer::after_millis(100).await;
+
+    // ========== BLOCKING TESTS ==========
+    info!("========== BLOCKING TRANSACTION TESTS ==========");
+    {
+        let mut i2c = I2c::new_blocking(
+            i2c_peri.reborrow(),
+            scl.reborrow(),
+            sda.reborrow(),
+            config,
+        );
+
+        info!("=== Test 1: Consecutive Writes (Should Merge) ===");
+        test_consecutive_writes_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 2: Consecutive Reads (Should Merge) ===");
+        test_consecutive_reads_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 3: Write then Read (RESTART) ===");
+        test_write_then_read_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 4: Read then Write (RESTART) ===");
+        test_read_then_write_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 5: Complex Mixed Sequence ===");
+        test_mixed_sequence_blocking(&mut i2c, slave_addr);
+
+        info!("=== Test 6: Single Operations ===");
+        test_single_operations_blocking(&mut i2c, slave_addr);
+
+        info!("Blocking tests OK");
+    }
+
+    Timer::after_millis(100).await;
+
+    // ========== ASYNC TESTS ==========
+    info!("========== ASYNC TRANSACTION TESTS (DMA) ==========");
+    {
+        let tx_dma = peri!(p, I2C_TX_DMA);
+        let rx_dma = peri!(p, I2C_RX_DMA);
+        let irq = irqs!(I2C);
 
-    info!("=== Test 1: Consecutive Writes (Should Merge) ===");
-    test_consecutive_writes(&mut i2c, slave_addr);
+        let mut i2c = I2c::new(i2c_peri, scl, sda, irq, tx_dma, rx_dma, config);
 
-    info!("=== Test 2: Consecutive Reads (Should Merge) ===");
-    test_consecutive_reads(&mut i2c, slave_addr);
+        info!("=== Test 1: Consecutive Writes (Should Merge) ===");
+        test_consecutive_writes_async(&mut i2c, slave_addr).await;
 
-    info!("=== Test 3: Write then Read (RESTART) ===");
-    test_write_then_read(&mut i2c, slave_addr);
+        info!("=== Test 2: Consecutive Reads (Should Merge) ===");
+        test_consecutive_reads_async(&mut i2c, slave_addr).await;
 
-    info!("=== Test 4: Read then Write (RESTART) ===");
-    test_read_then_write(&mut i2c, slave_addr);
+        info!("=== Test 3: Write then Read (RESTART) ===");
+        test_write_then_read_async(&mut i2c, slave_addr).await;
 
-    info!("=== Test 5: Complex Mixed Sequence ===");
-    test_mixed_sequence(&mut i2c, slave_addr);
+        info!("=== Test 4: Read then Write (RESTART) ===");
+        test_read_then_write_async(&mut i2c, slave_addr).await;
 
-    info!("=== Test 6: Single Operations ===");
-    test_single_operations(&mut i2c, slave_addr);
+        info!("=== Test 5: Complex Mixed Sequence ===");
+        test_mixed_sequence_async(&mut i2c, slave_addr).await;
 
-    info!("Test OK");
+        info!("=== Test 6: Single Operations ===");
+        test_single_operations_async(&mut i2c, slave_addr).await;
+
+        info!("Async tests OK");
+    }
+
+    info!("All tests OK");
     cortex_m::asm::bkpt();
 }
 
-fn test_consecutive_writes(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_consecutive_writes_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected on bus: START, ADDR+W, data1, data2, data3, STOP
     // NO intermediate RESTART/STOP between writes - they should be merged
     let data1 = [0x10, 0x11, 0x12];
@@ -95,7 +133,7 @@ fn test_consecutive_writes(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     }
 }
 
-fn test_consecutive_reads(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_consecutive_reads_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected on bus: START, ADDR+R, data1, data2, data3, NACK, STOP
     // NO intermediate RESTART/STOP between reads - they should be merged
     let mut buf1 = [0u8; 4];
@@ -122,7 +160,7 @@ fn test_consecutive_reads(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     }
 }
 
-fn test_write_then_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_write_then_read_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected: START, ADDR+W, data, RESTART, ADDR+R, data, NACK, STOP
     let write_data = [0xAA, 0xBB];
     let mut read_buf = [0u8; 4];
@@ -142,7 +180,7 @@ fn test_write_then_read(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     }
 }
 
-fn test_read_then_write(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_read_then_write_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Expected: START, ADDR+R, data, NACK, RESTART, ADDR+W, data, STOP
     let mut read_buf = [0u8; 3];
     let write_data = [0xCC, 0xDD, 0xEE];
@@ -162,7 +200,7 @@ fn test_read_then_write(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     }
 }
 
-fn test_mixed_sequence(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_mixed_sequence_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Complex: W, W, R, R, W, R
     // Groups: [W,W] RESTART [R,R] RESTART [W] RESTART [R]
     let w1 = [0x01, 0x02];
@@ -193,7 +231,7 @@ fn test_mixed_sequence(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     }
 }
 
-fn test_single_operations(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
+fn test_single_operations_blocking(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
     // Test single write
     let write_data = [0xFF];
     let mut ops = [Operation::Write(&write_data)];
@@ -218,3 +256,143 @@ fn test_single_operations(i2c: &mut I2c<'_, Blocking, Master>, addr: u8) {
         }
     }
 }
+
+// ==================== ASYNC TEST FUNCTIONS ====================
+
+async fn test_consecutive_writes_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let data1 = [0x10, 0x11, 0x12];
+    let data2 = [0x20, 0x21];
+    let data3 = [0x30, 0x31, 0x32, 0x33];
+
+    let mut ops = [
+        Operation::Write(&data1),
+        Operation::Write(&data2),
+        Operation::Write(&data3),
+    ];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Consecutive writes succeeded (merged 9 bytes)"),
+        Err(e) => {
+            error!("✗ Consecutive writes failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive writes");
+        }
+    }
+}
+
+async fn test_consecutive_reads_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let mut buf1 = [0u8; 4];
+    let mut buf2 = [0u8; 3];
+    let mut buf3 = [0u8; 2];
+
+    let mut ops = [
+        Operation::Read(&mut buf1),
+        Operation::Read(&mut buf2),
+        Operation::Read(&mut buf3),
+    ];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Consecutive reads succeeded (merged 9 bytes)");
+            info!("  buf1: {:02x}", buf1);
+            info!("  buf2: {:02x}", buf2);
+            info!("  buf3: {:02x}", buf3);
+        }
+        Err(e) => {
+            error!("✗ Consecutive reads failed: {:?}", e);
+            defmt::panic!("Test failed: consecutive reads");
+        }
+    }
+}
+
+async fn test_write_then_read_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let write_data = [0xAA, 0xBB];
+    let mut read_buf = [0u8; 4];
+
+    let mut ops = [Operation::Write(&write_data), Operation::Read(&mut read_buf)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Write-then-read succeeded with RESTART");
+            info!("  Written: {:02x}", write_data);
+            info!("  Read: {:02x}", read_buf);
+        }
+        Err(e) => {
+            error!("✗ Write-then-read failed: {:?}", e);
+            defmt::panic!("Test failed: write-then-read");
+        }
+    }
+}
+
+async fn test_read_then_write_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let mut read_buf = [0u8; 3];
+    let write_data = [0xCC, 0xDD, 0xEE];
+
+    let mut ops = [Operation::Read(&mut read_buf), Operation::Write(&write_data)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Read-then-write succeeded with RESTART");
+            info!("  Read: {:02x}", read_buf);
+            info!("  Written: {:02x}", write_data);
+        }
+        Err(e) => {
+            error!("✗ Read-then-write failed: {:?}", e);
+            defmt::panic!("Test failed: read-then-write");
+        }
+    }
+}
+
+async fn test_mixed_sequence_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    let w1 = [0x01, 0x02];
+    let w2 = [0x03, 0x04];
+    let mut r1 = [0u8; 2];
+    let mut r2 = [0u8; 2];
+    let w3 = [0x05];
+    let mut r3 = [0u8; 1];
+
+    let mut ops = [
+        Operation::Write(&w1),
+        Operation::Write(&w2),
+        Operation::Read(&mut r1),
+        Operation::Read(&mut r2),
+        Operation::Write(&w3),
+        Operation::Read(&mut r3),
+    ];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => {
+            info!("✓ Mixed sequence succeeded");
+            info!("  Groups: [W4] RESTART [R4] RESTART [W1] RESTART [R1]");
+        }
+        Err(e) => {
+            error!("✗ Mixed sequence failed: {:?}", e);
+            defmt::panic!("Test failed: mixed sequence");
+        }
+    }
+}
+
+async fn test_single_operations_async(i2c: &mut I2c<'_, Async, Master>, addr: u8) {
+    // Test single write
+    let write_data = [0xFF];
+    let mut ops = [Operation::Write(&write_data)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Single write succeeded"),
+        Err(e) => {
+            error!("✗ Single write failed: {:?}", e);
+            defmt::panic!("Test failed: single write");
+        }
+    }
+
+    // Test single read
+    let mut read_buf = [0u8; 1];
+    let mut ops = [Operation::Read(&mut read_buf)];
+
+    match i2c.transaction(addr, &mut ops).await {
+        Ok(_) => info!("✓ Single read succeeded, data: 0x{:02x}", read_buf[0]),
+        Err(e) => {
+            error!("✗ Single read failed: {:?}", e);
+            defmt::panic!("Test failed: single read");
+        }
+    }
+}
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 07b667ade..de06cb267 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -109,7 +109,7 @@ define_peris!(
 define_peris!(
     UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
-    I2C = I2C1, I2C_SCL = PB8, I2C_SDA = PB9,
+    I2C = I2C1, I2C_SCL = PB8, I2C_SDA = PB9, I2C_TX_DMA = DMA1_CH6, I2C_RX_DMA = DMA1_CH7,
     @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
     @irq I2C = {I2C1 => embassy_stm32::i2c::EventInterruptHandler<embassy_stm32::peripherals::I2C1>, embassy_stm32::i2c::ErrorInterruptHandler<embassy_stm32::peripherals::I2C1>;},
 );