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authorMatthew W. Samsonoff <[email protected]>2022-10-03 13:03:42 -0400
committerGrant Miller <[email protected]>2023-04-05 14:34:24 -0500
commita0b60966106f96e2915d429319a347e239eb1a5f (patch)
tree757efd4919c5b5a86dfb159058981bc726851a00
parent7e9e628eb9e63598a7d15ecae21af5a94ee93be4 (diff)
Put ADC input pin into analog mode
-rw-r--r--embassy-stm32/src/adc/v1.rs6
1 files changed, 5 insertions, 1 deletions
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 923a1d97a..224d17178 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -236,7 +236,10 @@ impl<'d, T: Instance> Adc<'d, T> {
236 } 236 }
237 } 237 }
238 238
239 pub fn read(&mut self, pin: &mut impl AdcPin<T>) -> u16 { 239 pub fn read<P>(&mut self, pin: &mut P) -> u16
240 where
241 P: AdcPin<T> + crate::gpio::sealed::Pin,
242 {
240 unsafe { 243 unsafe {
241 // A.7.2 ADC enable sequence code example 244 // A.7.2 ADC enable sequence code example
242 if T::regs().isr().read().adrdy() { 245 if T::regs().isr().read().adrdy() {
@@ -252,6 +255,7 @@ impl<'d, T: Instance> Adc<'d, T> {
252 255
253 T::regs().cfgr1().modify(|reg| reg.set_res(self.resolution.res())); 256 T::regs().cfgr1().modify(|reg| reg.set_res(self.resolution.res()));
254 Self::set_channel_sample_time(pin.channel(), self.sample_time); 257 Self::set_channel_sample_time(pin.channel(), self.sample_time);
258 pin.set_as_analog();
255 T::regs() 259 T::regs()
256 .chselr() 260 .chselr()
257 .write(|reg| reg.set_chselx(pin.channel() as usize, true)); 261 .write(|reg| reg.set_chselx(pin.channel() as usize, true));