aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGrant Miller <[email protected]>2021-12-14 16:05:39 -0600
committerGrant Miller <[email protected]>2021-12-14 17:46:25 -0600
commita13a7a661604f4fa626c27a3330acb194912f66e (patch)
tree1dff5abb68e3e557bb5bf69fcc90128c58256343
parente75cb1a56498a2f0b48e63426e9c10c6520aead0 (diff)
Replace wait_for_idle with spin_until_idle
-rw-r--r--embassy-stm32/src/spi/mod.rs20
-rw-r--r--embassy-stm32/src/spi/v1.rs18
-rw-r--r--embassy-stm32/src/spi/v2.rs28
-rw-r--r--embassy-stm32/src/spi/v3.rs23
4 files changed, 46 insertions, 43 deletions
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index f47347265..a2a475e2b 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -431,6 +431,26 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
431 } 431 }
432} 432}
433 433
434fn spin_until_idle(regs: Regs) {
435 #[cfg(any(spi_v1, spi_f1))]
436 unsafe {
437 while regs.sr().read().bsy() {}
438 }
439
440 #[cfg(spi_v2)]
441 unsafe {
442 while regs.sr().read().ftlvl() > 0 {}
443 while regs.sr().read().frlvl() > 0 {}
444 while regs.sr().read().bsy() {}
445 }
446
447 #[cfg(spi_v3)]
448 unsafe {
449 while !regs.sr().read().txc() {}
450 while regs.sr().read().rxplvl().0 > 0 {}
451 }
452}
453
434trait Word { 454trait Word {
435 const WORDSIZE: WordSize; 455 const WORDSIZE: WordSize;
436} 456}
diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs
index 98f05770b..943592617 100644
--- a/embassy-stm32/src/spi/v1.rs
+++ b/embassy-stm32/src/spi/v1.rs
@@ -2,7 +2,7 @@
2 2
3pub use embedded_hal::blocking; 3pub use embedded_hal::blocking;
4pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; 4pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
5use futures::future::join3; 5use futures::future::join;
6 6
7use super::*; 7use super::*;
8 8
@@ -76,7 +76,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
76 }); 76 });
77 } 77 }
78 78
79 join3(tx_f, rx_f, Self::wait_for_idle()).await; 79 join(tx_f, rx_f).await;
80
81 spin_until_idle(T::regs());
80 82
81 unsafe { 83 unsafe {
82 T::regs().cr2().modify(|reg| { 84 T::regs().cr2().modify(|reg| {
@@ -134,7 +136,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
134 }); 136 });
135 } 137 }
136 138
137 join3(tx_f, rx_f, Self::wait_for_idle()).await; 139 join(tx_f, rx_f).await;
140
141 spin_until_idle(T::regs());
138 142
139 unsafe { 143 unsafe {
140 T::regs().cr2().modify(|reg| { 144 T::regs().cr2().modify(|reg| {
@@ -148,12 +152,4 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
148 152
149 Ok(()) 153 Ok(())
150 } 154 }
151
152 async fn wait_for_idle() {
153 unsafe {
154 while T::regs().sr().read().bsy() {
155 // spin
156 }
157 }
158 }
159} 155}
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index 286976329..d9f5b46fe 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -1,7 +1,7 @@
1#![macro_use] 1#![macro_use]
2 2
3pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; 3pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
4use futures::future::{join, join3}; 4use futures::future::join;
5 5
6use super::*; 6use super::*;
7 7
@@ -35,7 +35,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
35 }); 35 });
36 } 36 }
37 37
38 join(f, Self::wait_for_idle()).await; 38 f.await;
39
40 spin_until_idle(T::regs());
39 41
40 unsafe { 42 unsafe {
41 T::regs().cr2().modify(|reg| { 43 T::regs().cr2().modify(|reg| {
@@ -89,7 +91,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
89 }); 91 });
90 } 92 }
91 93
92 join3(tx_f, rx_f, Self::wait_for_idle()).await; 94 join(tx_f, rx_f).await;
95
96 spin_until_idle(T::regs());
93 97
94 unsafe { 98 unsafe {
95 T::regs().cr2().modify(|reg| { 99 T::regs().cr2().modify(|reg| {
@@ -152,7 +156,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
152 }); 156 });
153 } 157 }
154 158
155 join3(tx_f, rx_f, Self::wait_for_idle()).await; 159 join(tx_f, rx_f).await;
160
161 spin_until_idle(T::regs());
156 162
157 unsafe { 163 unsafe {
158 T::regs().cr2().modify(|reg| { 164 T::regs().cr2().modify(|reg| {
@@ -166,18 +172,4 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
166 172
167 Ok(()) 173 Ok(())
168 } 174 }
169
170 async fn wait_for_idle() {
171 unsafe {
172 while T::regs().sr().read().ftlvl() > 0 {
173 // spin
174 }
175 while T::regs().sr().read().frlvl() > 0 {
176 // spin
177 }
178 while T::regs().sr().read().bsy() {
179 // spin
180 }
181 }
182 }
183} 175}
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs
index c31415a2f..a3e39b213 100644
--- a/embassy-stm32/src/spi/v3.rs
+++ b/embassy-stm32/src/spi/v3.rs
@@ -1,7 +1,7 @@
1#![macro_use] 1#![macro_use]
2 2
3pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; 3pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
4use futures::future::join3; 4use futures::future::join;
5 5
6use super::*; 6use super::*;
7 7
@@ -95,7 +95,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
95 }); 95 });
96 } 96 }
97 97
98 join3(tx_f, rx_f, Self::wait_for_idle()).await; 98 join(tx_f, rx_f).await;
99
100 spin_until_idle(T::regs());
101
99 unsafe { 102 unsafe {
100 T::regs().cfg1().modify(|reg| { 103 T::regs().cfg1().modify(|reg| {
101 reg.set_rxdmaen(false); 104 reg.set_rxdmaen(false);
@@ -159,7 +162,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
159 }); 162 });
160 } 163 }
161 164
162 join3(tx_f, rx_f, Self::wait_for_idle()).await; 165 join(tx_f, rx_f).await;
166
167 spin_until_idle(T::regs());
168
163 unsafe { 169 unsafe {
164 T::regs().cfg1().modify(|reg| { 170 T::regs().cfg1().modify(|reg| {
165 reg.set_rxdmaen(false); 171 reg.set_rxdmaen(false);
@@ -171,15 +177,4 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
171 } 177 }
172 Ok(()) 178 Ok(())
173 } 179 }
174
175 async fn wait_for_idle() {
176 unsafe {
177 while !T::regs().sr().read().txc() {
178 // spin
179 }
180 while T::regs().sr().read().rxplvl().0 > 0 {
181 // spin
182 }
183 }
184 }
185} 180}