diff options
| author | WillaWillNot <[email protected]> | 2025-11-10 17:03:50 -0500 |
|---|---|---|
| committer | WillaWillNot <[email protected]> | 2025-11-10 17:29:21 -0500 |
| commit | a3b037ff9d328eb92e0ded1320466f6e1b59e893 (patch) | |
| tree | d9e1e78914804e9929f2195dba3f5e72447fbacb | |
| parent | f6fe96841160e33bf2550907993c7e22ec0f63ad (diff) | |
Added TXDR flush via TXE set to the drop guard for write_dma_internal_slave; factored in remaining DMA transfers for the return values for write_dma_internal_slave and read_dma_internal_slave
| -rw-r--r-- | embassy-stm32/CHANGELOG.md | 1 | ||||
| -rw-r--r-- | embassy-stm32/src/i2c/v2.rs | 9 |
2 files changed, 9 insertions, 1 deletions
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md index 8a53c9f03..33c7b5da5 100644 --- a/embassy-stm32/CHANGELOG.md +++ b/embassy-stm32/CHANGELOG.md | |||
| @@ -53,6 +53,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 | |||
| 53 | - feat: stm32/spi: added support for slave mode ([#4388](https://github.com/embassy-rs/embassy/pull/4388)) | 53 | - feat: stm32/spi: added support for slave mode ([#4388](https://github.com/embassy-rs/embassy/pull/4388)) |
| 54 | - chore: Updated stm32-metapac and stm32-data dependencies | 54 | - chore: Updated stm32-metapac and stm32-data dependencies |
| 55 | - adc: reogranize and cleanup somewhat. require sample_time to be passed on conversion | 55 | - adc: reogranize and cleanup somewhat. require sample_time to be passed on conversion |
| 56 | - fix: stm32/i2c v2 slave: prevent misaligned reads, error false positives, and incorrect counts of bytes read/written | ||
| 56 | 57 | ||
| 57 | ## 0.4.0 - 2025-08-26 | 58 | ## 0.4.0 - 2025-08-26 |
| 58 | 59 | ||
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs index 57a7acee7..4527e55b9 100644 --- a/embassy-stm32/src/i2c/v2.rs +++ b/embassy-stm32/src/i2c/v2.rs | |||
| @@ -1235,6 +1235,7 @@ impl<'d> I2c<'d, Async, MultiMaster> { | |||
| 1235 | regs.cr1().modify(|w| w.set_tcie(true)); | 1235 | regs.cr1().modify(|w| w.set_tcie(true)); |
| 1236 | Poll::Pending | 1236 | Poll::Pending |
| 1237 | } else if isr.stopf() { | 1237 | } else if isr.stopf() { |
| 1238 | remaining_len = remaining_len.saturating_add(dma_transfer.get_remaining_transfers() as usize); | ||
| 1238 | regs.icr().write(|reg| reg.set_stopcf(true)); | 1239 | regs.icr().write(|reg| reg.set_stopcf(true)); |
| 1239 | let poll = Poll::Ready(Ok(total_len - remaining_len)); | 1240 | let poll = Poll::Ready(Ok(total_len - remaining_len)); |
| 1240 | poll | 1241 | poll |
| @@ -1274,7 +1275,8 @@ impl<'d> I2c<'d, Async, MultiMaster> { | |||
| 1274 | w.set_txdmaen(false); | 1275 | w.set_txdmaen(false); |
| 1275 | w.set_stopie(false); | 1276 | w.set_stopie(false); |
| 1276 | w.set_tcie(false); | 1277 | w.set_tcie(false); |
| 1277 | }) | 1278 | }); |
| 1279 | regs.isr().write(|w| w.set_txe(true)); | ||
| 1278 | }); | 1280 | }); |
| 1279 | 1281 | ||
| 1280 | let state = self.state; | 1282 | let state = self.state; |
| @@ -1297,6 +1299,11 @@ impl<'d> I2c<'d, Async, MultiMaster> { | |||
| 1297 | self.info.regs.cr1().modify(|w| w.set_tcie(true)); | 1299 | self.info.regs.cr1().modify(|w| w.set_tcie(true)); |
| 1298 | Poll::Pending | 1300 | Poll::Pending |
| 1299 | } else if isr.stopf() { | 1301 | } else if isr.stopf() { |
| 1302 | let mut leftover_bytes = dma_transfer.get_remaining_transfers(); | ||
| 1303 | if !self.info.regs.isr().read().txe() { | ||
| 1304 | leftover_bytes = leftover_bytes.saturating_add(1); | ||
| 1305 | } | ||
| 1306 | remaining_len = remaining_len.saturating_add(leftover_bytes as usize); | ||
| 1300 | self.info.regs.icr().write(|reg| reg.set_stopcf(true)); | 1307 | self.info.regs.icr().write(|reg| reg.set_stopcf(true)); |
| 1301 | if remaining_len > 0 { | 1308 | if remaining_len > 0 { |
| 1302 | dma_transfer.request_pause(); | 1309 | dma_transfer.request_pause(); |
